Chapter 3: Analysis of Three-Level Inverter

3.1 Introduction: - The power electronics device which converts DC power to AC power

at required output voltage and frequency level is known as an inverter. Two categories

into which inverters can be broadly classified are two level inverters and multilevel

inverters. One advantage that multilevel inverters have compared to two level inverters is

minimum harmonic distortion. A multilevel inverter can be utilized for multipurpose

applications, such as an active power filter, a static VAR compensator and machine drive

for sinusoidal and trapezoidal current applications. Some drawbacks to the multilevel

inverters are the need for isolated power supplies for each one of the stages, the fact that

they are a lot harder to build, they are more expensive, and they are more difficult to

control in software.

This chapter focuses on the analysis of a three-level inverter. Full analysis for the three-

level inverter is given. Desirable voltage and frequency have been achieved; however,

harmonics distortion should be investigated during three-level inverter operation.

When AC loads are fed through inverters, an output voltage of required

magnitude and frequency has to be achieved. A variable output voltage can be obtained

by varying the input DC voltage and maintaining the gain of the inverter constant. On the

other hand, if the DC input voltage is fixed and it is not controllable, a variable output

voltage can be obtained by varying the gain of the inverter, which is normally

accomplished by pulse-width-modulation (PWM) control within the inverter. The

inverters which produce an output voltage or a current with medium or low rate power

are known as two level inverters. In high-power and high-voltage applications these two-

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level inverters have some limitations in operating at high frequency mainly due to

switching losses and constraints of device rating. This is where three level inverters are

advantageous. Increasing the number of voltage levels in the inverter without requiring

higher rating on individual devices which can increase power rating.

The pulse width modulation (PWM) strategies are the most effective to control multilevel

inverters. Even though space vector modulation (SVPWM) is complicated, it is the

preferred method to reduce power losses by decreasing the power electronics devices

switching frequency, which can be limited by pulse width modulation. Different aspects

of the three-level NPC inverter will be discussed including the inverter topology. The

operation theory will be discussed with the aspect of space vector pulse width

modulation. Three-level inverter NPC inverter is shown in Fig. 3.1. Each leg contains

four active switches S1 to S4 with antiparallel diodes D1 to D4.

The capacitors at the DC side are used to split the DC input into two, to provide a neutral

point Z. The clamping diodes can be defined as the diodes connected to the neutral point,

DZ1, DZ2. When switches S2 and S3 are connected, the output terminal A can be taken to

the neutral through one of the clamping diodes. The voltage applied to each of the DC

capacitors is E, and it equals half of the total DC voltage Vd .

3.2 Three-level inverter operation (analysis of SVPWM)

Figure 3.1 Three-level NPC inverter

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3.2.1 Switching States

Switching states that are shown in Fig. 3.1 can represent the operating status of the

switches in the three-level NPC inverter. When switching state is 1, it is indicated that

upper two switches in leg A connected and the inverter terminal voltage v AZ , which

means the voltage for terminal A with respect to the neutral point Z, is +E, whereas -1

denotes that the lower two switches are on, which means v AZ = -E. When switching state

0, it indicates that the inner two switches S2 and S3 are connected and v AZ =0 through

the clamping diode, depending on the direction of the load current i A .

When D Z1 is turn on, the load current will be positive ( i A > 0 ) and the terminal A will

be connected to the neutral point Z through the conduction of D Z1 and S2 . Table 3.1

shows switching status for leg A. Leg B and leg C have the same concept.

Table 3.1 Definition of Switching States

Switching Device Switching Status (Phase A) Inverter Terminal Voltage
State S1 S2 S3 S4 v AZ
1 On On Off Off E
0 Off On On Off 0
-1 Off Off On On -E

3.2.2 Space Vector Modulation

3.2.2.1 Stationary Space Vectors

Three switching states [1], [0] and [-1] can represent the operation of each leg. By taking

all three phases into account, the inverter has a total of 27 possible switching states.

Table3.2 shows the possibility of three phase switching states that are represented by

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three letters in square brackets for the inverter phases A, B, and C. Table 3.2 shows the

27 switching states that are shown in Fig. 3.2. The voltage has four groups.

I. Zero vector ( V0 ), representing three switching states [1 1 1], [0 0 0] and

[-1 -1 -1]. The magnitude of V0 is Zero.

II. Small vector ( V1 to V6 ), all having a magnitude of Vd /3. Each small sector has

two switching states, one containing [1] and the other containing [-1] and they

classified into P- or N- type small vector.

3
III. Medium vectors ( V7 to V12 ), whose magnitude is Vd .
3

2
IV. Large vectors (V13 to V18), all having a magnitude of Vd .
3

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 Table 3.2 Voltage and Switching States
Vector Vector
Space Vector Switching State
Classification Magnitude
V0 [1 1 1] [-1 -1 -1] [0 0 0] Zero vector 0

P-type N-type

V1 V1P [1 0 0]

V1N [0 -1 -1]

V2P [1 1 0]
V2
V2 N [0 0 -1]

Small vector
V3P [0 1 0]
V3 1
V3 N [-1 0 -1] Vd
3
V4P [0 1 1]
V4
V4 N [-1 0 0]

V5P [0 0 1]
V5
V5 N [-1 -1 0]

V6 P [1 0 1]
V6
V6 N [0 -1 0]

V7 [1 0 -1]

V8 [0 1 -1]
Medium vector

V9 [-1 1 0] 3
Vd
V10 [-1 0 1] 3
V11 [0 -1 1]

V12 [1 -1 0]

V13 [1 -1 -1]

V14 [1 1 -1]
Large vector

V15 [-1 1 -1] 2

Vd
3
V16 [-1 1 1]

V17 [-1 -1 1]

V18 [1 -1 1]

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 Figure 3.2 Space vector diagram of the three-level inverter

Figure 3.3 Division of sectors and regions for three-level inverter

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3.2.2.2 Determining the sector

is calculated and then the sector, in which the command vector V * is located, is

determined as follows:

If is between 0 o < 60 o , then Vref will be in sec tor I.

If is between 60 o < 120 o , then Vref will be in sec tor II.

If is between 120 o < 180 o , then Vref will be in sec tor III.

If is between 180 o < 240 o , then Vref will be in sec tor IV.

If is between 240 o < 300 o , then Vref will be in sec tor V.

If is between 300 o < 360 o , then Vref will be in sec tor VI.

3.2.3 Time Calculation

The space vector diagram that is shown in Fig. 3.2 can be used to calculate the time

for each sector (I to VI). Each sector has four regions (1 to 4), as shown in fig. 3.3,

with the switching states of all vectors.

By using the same strategy that was used in chapter two, the sum of the voltage

multiplied by the interval of chose space vector equals the product of the reference

voltage Vref and sampling period T S . To illustrate, when reference voltage is located

in region 2 of sector I then the nearest vectors to reference voltage are

V1 , V7 , and V2 as shown in Fig. 3.4, and the next equations explain the relationship

between times and voltages :-

V1T a + V7 Tb + V2 Tc = Vref TS
( 3.1 )
T a +Tb + Tc = TS

Where T a , Tb , and Tc are the times for V1 , V7 , and V2 respectively.

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 1 1 -1

110
1 0 -1
0 0 -1

1 -1 -1
0 -1 -1

Figure 3.4 Voltage vector I and their times

From Fig. 4 voltage sectors V1 , V2 , and V7 can be observed as follow:-

r 1
V1 = 3 Vd

r 1 j / 3

V2 = Vd e
3
(3. 2 )
r
V7 = 3 Vd e j / 6
3
r
Vref = Vref e j

By substituting equation (3.2) into (3.1)

1 3 1
Vd Ta + Vd cos + jsin Tb + Vd cos + jsin Tc = Vref (cos + jsin )TS ( 3.3 )
3 3 6 6 3 3 3

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From equation (3.3) real part and imaginary part can be determined by following

equations

V
Ta + Tb + Tc = 3 ref (cos ) TS
3 1
Re
2 2 Vd

( 3.4 )

Vref
Im
3
Tb +
3
Tc = 3 (sin )T
2 2 Vd

By solving equation (3. 4) with the equation for total time TS = Ta + Tb + Tc .

Ta = TS [1 2m a sin ]


Tb = TS 2 m a sin + 1 for 0 (3 . 5 )
3 3


Tc = TS 1 2 m a sin 3 +

Where m a is the modulation index and can be expressed as follow:-

Vref
ma = 3 ( 3 .6 )
Vd

The maximum value for Vref can be derived at medium vector voltage

( V7 , V8 , V9 , V10 , V11 , and V12 )

3
V ref ,max = Vd ( 3.7 )
3

By solving both equations (3.6) and (3.7) together, the maximum value for

modulation index can be expressed as follow:-

Vref ,max
m a ,max = 3 =1 (3.8 )
Vd

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 And the modulation index can be given as below

0 ma 1 (3. 9 )
r
The equations for the calculation of times for Vref in sector I can are given in table 3.3 as

below.

Table 3.3 Time calculation for Vref in sector I

Region Ta Tb Tc

r r TS 1 2m a sin + r
1 V1 TS 2m a sin V0 3 V2 TS [2m a sin ]
3

r r TS 2m a sin + 1 r
2 V1 TS [1 2m a sin ] V7 3 V2 TS 1 2m a sin
3

r
r TS 2 2m a sin + r TS 2m a sin 1
3 V1 3 V7 TS [2m a sin ] V13
3

r
r r TS 2 2m a sin +
4
V14 TS [2m a sin 1] V7 TS 2m a sin V2 3
3

The times can be calculated for sectors (II to VI) by using the equations in table 3.3 with

multiple of / 3 subtracted from the actual angular displacement , such that modified

angle falls into the range between zero and / 3 for use in the equations as in chapter two.

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 r
3.2.4 Relationship between Vref Location and Time
r
By using the example in Fig. 3.8, the relationship can be observed between Vref location
r
and time. By assuming the location of Vref at point Q located at the center of region 3.
r
Because the distances for the nearest vectors V1 , V7 , and V13 from Q are the same, the

times for these vectors should be identical.

Three triangles in region 3 are equilibrium triangles. From triangle V0 , X, and Q

Vref =0.509175 Vd , and = 10 .89 o . By substituting in equation (3.6), m a = 0.882 and

Ta = Tb = Tc = 0.3333 TS from the equations in table 3.3.

Figure 3.5 An example to determine the relationship between the location of Vref and times

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3.2.5 The Switching States by Using Switching Sequence.

By considering the switching transition and using sequences direction, shown in Fig. 3.6.

and Fig. 3.7, the direction of the switching sequences for all regions in six sectors can be

derived and the switching orders are given in the tables below, which are obtained for

each region located in sectors I to VI, if all switching states in each region are used.

Tables 3.4 shows thirteen segments of region 1 for each sector, Table 3.5 shows nine

segments of region 2 for each sector, Table 3.6 shows seven segments of region 3 for

each sector and Table 3.7 shows seven segments of region 4 for each sector.

Figure 3.6 Switching sequence for three-level SVPWM inverter

Figure 3.7 Sectors and their regions for three-level inverter

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 Table 3.4 thirteen segments of region 1 for all sectors
Switching Segments
Sector
1 2 3 4 5 6 7 8 9 10 11 12 13
r r r r r r r r r r r r r
V0 V1N V2 N V0 V1P V2 P V0 V2 P ` V1P V0 V2 N V1N V0
I.
-1-1-1 0-1-1 00-1 000 100 110 111 110 100 000 00-1 0-1-1 -1-1-1
r r r r r r r r r r r r r
V0 V2 N V3 N V0 V2 P V3P V0 V3P V2 P V0 V3N V2 N V0
II.
-1-1-1 00-1 -10-1 000 110 010 111 010 110 000 -10-1 00-1 -1-1-1
r r r r r r r r r r r r r
V0 V3 N V4 N V0 V3P V4 P V0 V4 P V3P V0 V4 N V3 N V0
III.
-1-1-1 -10-1 -100 000 010 011 111 011 010 000 -100 -10-1 -1-1-1
r r r r r r r r r r r r r
V0 V4 N V5 N V0 V4 P V5 P V0 V5 P V4 P V0 V5 N V4 N V0
IV.
-1-1-1 -100 -1-10 000 011 001 111 001 011 000 -1-10 -100 -1-1-1
r r r r r r r r r r r r r
V0 V5 N V6 N V0 V5 P V6 P V0 V6 P V5 P V0 V6 N V5 N V0
V.
-1-1-1 -1-10 0-10 000 001 101 111 101 001 000 0-10 -1-10 -1-1-1
r r r r r r r r r r r r r
V0 V6 N V1N V0 V6 P V1P V0 V1P V6 P V0 V1N V6 P V0
VI.
-1-1-1 0-10 0-1-1 000 101 100 111 100 101 000 0-1-1 0-10 -1-1-1

Table 3.5 nine segments of region 2 for each sector

Switching Segments
Sector
1 2 3 4 5 6 7 8 9
r r r r r r r r r
V1N V2 N V7 V1P V2 P V1P V7 V2 N V1N
I.
0-1-1 00-1 10-1 100 110 100 10-1 00-1 0-1-1
r r r r r r r r r
V2 N V3 N V8 V2 P V3 P V2 P V8 V3 N V2 N
II.
00-1 -10-1 01-1 110 010 110 01-1 -10-1 00-1
r r r r r r r r r
V3 N V4 N V9 V3P V4 P V3P V9 V4 N V3 N
III.
-10-1 -100 -110 010 011 010 -110 -100 -10-1
r r r r r r r r r
V4 N V5 N V10 V4 P V5P V4 P V10 V5 N V4 N
IV.
-100 -1-10 -101 011 001 011 -101 -1-10 -100
r r r r r r r r r
V5 N V6 N V11 V5P V6 P V5 P V11 V6 N V5 N
V.
-1-10 0-10 0-11 001 101 001 0-11 0-10 -1-10
r r r r r r r r r
V6 N V1N V12 V6 P V1P V6 P V12 V1N V6 N
VI.
0-10 0-1-1 1-10 101 100 101 1-10 0-1-1 0-10

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 Table 3.6 seven segments of region 3 for each sector
Switching Segments
Sector 1 2 3 4 5 6 7
r r r r r r r
V1N V13 V7 V1P V7 V13 V1N
I.
0-1-1 1-1-1 10-1 100 10-1 1-1-1 0-1-1
r r r r r r r
V2 N V14 V8 V2 P V8 V14 V2 N
II.
00-1 11-1 01-1 110 01-1 11-1 00-1
r r r r r r r
V3N V15 V9 V3P V9 V15 V3N
III.
-10-1 -11-1 -110 010 -110 -11-1 -10-1
r r r r r r r
V4 N V16 V10 V4 P V10 V16 V4 N
IV.
-100 -111 -101 011 -101 -111 -100
r r r r r r r
V5 N V17 V11 V5P V11 V17 V5 N
V.
-1-10 -1-11 0-11 001 0-11 -1-11 -1-10
r r r r r r r
V6 N V18 V12 V6 P V12 V18 V6 N
VI.
0-10 1-11 1-10 101 1-10 1-11 0-10

Table 3.7 seven segments of region 4 for each sector

Switching Segments
Sector 1 2 3 4 5 6 7
r r r r r r r
V2 N V7 V14 V2 P V14 V7 V2 N
I.
00-1 10-1 11-1 110 11-1 10-1 00-1
r r r r r r r
V3 N V8 V15 V3P V15 V8 V3N
II.
-10-1 01-1 -11-1 010 -11-1 01-1 -10-1
r r r r r r r
V4 N V9 V16 V4 P V16 V9 V4 N
III.
-100 -110 -111 011 -111 -110 -100
r r r r r r r
V5 N V10 V17 V5P V17 V10 V5 N
IV.
-1-10 -101 -1-11 001 -1-11 -101 -1-10
r r r r r r r
V6 N V11 V18 V6 P V18 V11 V6 N
V.
0-10 0-11 1-11 101 1-11 0-11 0-10
r r r r r r r
V1N V12 V13 V1P V13 V12 V1N
VI.
0-1-1 1-10 1-1-1 100 1-1-1 1-10 0-1-1

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Figures 3.8 to 3.11 show switching sequence for Vref in sector I-1,2,3, and 4.

Figure 3.8 Switching sequence of thirteen segments for Vref in sector I region 1

Figure 3.9 Switching sequence of nine segments for Vref in sector I region 2
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Figure 3.10 Switching sequence of nine segments for Vref in sector I region 3

Figure 3.11 Switching sequence of nine segments for Vref in sector I region 4

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Figures 3.12 to 3.15 show switching sequence for Vref in sector II-1,2,3, and 4.

Figure 3.12 Switching sequence of thirteen segments for Vref in sector II region 1

Figure 3.13 Switching sequence of nine segments for Vref in sector II region 2

83
Figure 3.14 Switching sequence of nine segments for Vref in sector II region 3

Figure 3.15 Switching sequence of nine segments for Vref in sector II region 4
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Figures 3.16 to 3.19 show switching sequence for Vref in sector III-1,2,3, and 4.

Figure 3.16 Switching sequence of thirteen segments for Vref in sector III region 1

Figure 3.17 Switching sequence of nine segments for Vref in sector III region 2
85
Figure 3.18 Switching sequence of nine segments for Vref in sector III region 3

Figure 3.19 Switching sequence of nine segments for Vref in sector III region 4

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Figures 3.20 to 3.23 show switching sequence for Vref in sector IV-1,2,3, and 4.

Figure 3.20 Switching sequence of thirteen segments for Vref in sector IV region 1

Figure 3.21 Switching sequences of nine segments for Vref in sector IV region 2
87
Figure 3.22 Switching sequence of nine segments for Vref in sector IV region 3

Figure 3.23 Switching sequence of nine segments for Vref in sector IV region 4

88
Figures 3.24 to 3.27 show switching sequence for Vref in sector V-1,2,3, and 4.

Figure 3.24 Switching sequence of thirteen segments for Vref in sector V region 1

Figure 3.25 Switching sequence of nine segments for Vref in sector V region 2

89
Figure 3.26 Switching sequence of nine segments for Vref in sector V region 3

Figure 3.27 Switching sequence of nine segments for Vref in sector V region 4

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Figures 3.28 to 3.31 show switching sequence for Vref in sector VI-1,2,3, and 4.

Figure 3.28 Switching sequence of thirteen segments for Vref in sector VI region 1

Figure 3.29 Switching sequence of nine segments for Vref in sector VI region 2

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 Figure 3.30 Switching sequence of nine segments for Vref in sector VI region 3

Figure 3.31 Switching sequence of nine segments for Vref in sector VI region 4

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3.3 Conclusion

This chapter provides a comprehensive analysis on the three-level diode clamped

inverter, also known as neutral-point clamped (NPC) inverter. A number of issues were

investigated, including the inverter configuration, operating principle, space vector

modulation (SVM) techniques, and neutral point voltage control. The performance of the

three-phase three-level twelve switch inverter has been explained and improved by

employing SVPWM control scheme. The use of three-level inverters reduces the

harmonic components of the output voltage compared with the two-level inverter at the

same switching frequency. It needs no additional reactors or transformers to reduce the

harmonic components. Then, it is suitable for high voltage and high power systems.

Switching sequence for each region in each sector had been explained in details which

were utilized in the designed and implemented diode clamped three-level inverter to

realize the requirements, and fed R-L load by the required values of voltage and

frequency. Also, some derivations, such as thirteen segments of region 1 for each sector,

nine segments of region 2 in each sector, seven segments of region 3 for each sector for

three-level inverter, which have never been mentioned before, were derived and the

switching sequence for each region in each sector was drawn.

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