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Task Migration and Energy
Consumption in MPSoC
Systems
Fabiano Hessel
[fabiano.hessel@pucrs.br]
Catholic University of Rio Grande do Sul (PUCRS)

Informatics Faculty - Porto Alegre, Brazil
Task Migration and Energy Consumption in MPSoC Systems Fabiano Hessel PUCRS Porto Alegre, Brazil
Brazil....Porto Alegre....without beach

and cold?!?
2
Agenda
Introduction
Motivation
Task Migration
Energy Consumption
Conclusion
3
Introduction
Heterogeneous MPSoC is required by current
multimedia applications (TI OMAP, ST Nomadik,
Philips Nexperia)
MPSoCs issues
Parallel programming model
Energy consumption estimation tools
Performance evaluation tools
Load balancing methods
Real-time requirements (RTS management)
4
Energy Consumption and Performance

Evaluation
Estimates
Needed during the design time
Should estimate both performance and energy
consumption
Help taking decisions: # processors,
interconnection, mapping
Tools
Estimate projects requirements
Explore the solutions space in a high level of
abstraction 5
Load Balancing Methods

MPSoCs have some similarity with parallel
computing (cluster, grid)
parallel software model, mapping, task
migration, homogeneous/heterogeneous
processors,
Challenge: adapt/propose and employ
generic parallel techniques in MPSoCs
Parallel programming methods
Static and Dynamic Task migration: partial and
total cache coherence and cost
6
Motivation
Investigation of load balancing techniques
How to adapt existing techniques to MPSoC
systems ?
Helps avoiding execution overload
Typically, temperatures of the chip are higher in
overloaded points
Hot spots accelerate fail mechanisms
(electromigration, stress migration, dielectric
breakdown)
7
Motivation
Load balancing helps:
In situations where deadlines may not be
achieved (periodic/aperiodic, hard/soft RT)
Save energy (schedulability) : turn off a
processor, clock gating, low frequency
to minimize fail related issues which can occur
in a given processing element
8
Motivation
High level estimation tools
Software increasing importance
Short development time
Increasing number of processors
Estimation methods
Analytical-based
Simulation-based
Improvements in the simulation based methods
9
Task Migration
To be implemented in an MPSoC real-time
platform with a dynamic load balancing
mechanism (SMP and AMP)
The static task allocation (Task Graph Free
[Wolf] and CAFES Tool)
Group of Processors: Global AMP Local SMP
Load balancing mechanism should contain
both internal and external migration
10
Global AMP Local SMP

PE 1 PE 1 PE 2 PE 2
Router Router
PE 1 Mem + + PE 2 Mem
NI NI
Router Router
+ +
PE 3 PE 3
NI NI
Global
PE 3 Mem Mem
11
Platform N-MIPS
Exo-Kernel, EPOS and MIPS-RTOS
ISS tool for high level simulation (N-MIPS +
communication channel + OS)
N-Mips FPGA (FPGA VCV2VP30): ~94000 logic ports
12
Task migration
Shared memory (groups
Group of processors of processors - SMP)
T2 T2 Task is preempted
T2
PId Shared T5
T1 T4
T3 Memory T2
PE1 sends the T2 PId to
PE1 Get code
PE2
and data
PE2
Interconnection T2 Task continues its

execution in the new
processing element
13
Task migration
Non-shared memory
(AMP)
T2 Task is halted
T2
T2
Id T5
T1 T4 PE1 sends a message to
T3 T2 T2
Code PE2 telling that it should
PE1 PE2 Data
execute the T2 Task
Interconnection T2 Task restarts its

execution in the new
processing element
14
Task migration
Load monitor strategies:
Centralized, hardware
Centralized, software
Distributed
Load monitor activation can be based on: (when migrate
tasks ?)
Unbalanced load system measure: static and dynamic
Temperature measure
The decision of migrating a task takes into account the
associated cost of sending the needed information
through the communication channel
15
Task migration
Validation:
Benchmark applications
Use of applications in the ISS
Use of applications in the RTL level platform
16
Energy consumption
Same MPSoC platform:
N-MIPS
Bus interconnection
Modelling
Use of VHDL events to detect activity of logic
devices
Get the transitions of a circuit with such events
Cycle-level simulation
Energy consumption estimative with a pre-
implemented library (CMOS TSMC 0.35um)
17
Energy consumption - Methodology
Synthesized VHDL
Behavioural VHDL Synthesized VHDL
conversion to the
used as input in logic gate level
estimative library
Circuit simulation Test bench

with energy creation and use of
consumption the circuit with the
estimative library
*Leonardo Spectrum (synthesis) and ModelSim (simulation)

18
Energy consumption
Key component: estimative library
10 logic cells
Using events to detect activity and calculate
the power consumption of a circuit
Taking into account both static and dynamic
power, Power dissipated and Fanout (1 up to
10)
Electric simulation done by SPICE
19
Energy consumption
Architecture:
Processor core isolated from the memory
modules (internal and external) and UART
Both software performance and energy
consumption estimative verification
Use of the values reported by the VHDL
simulation in the instruction level
simulator (ISS)
20
Energy consumption
Initial platform for VHDL estimative
Synthesizes
CPU core
Internal
CPU internal bus
memory
(bootloader)
UART Estimative
library
External memory
(SRAM or BlockRAM)
Testbench
21
Energy consumption
Interconnection
Should be taken into account in the energy consumption
estimative
Use of the same estimative methodology previously employed
in the processors
Static consumption (1ms without package transmission)
Packet average consumption (256 packages)
Bus
Little area occupation when compared to other strategies
(8372 logic ports)
Satisfactory throughput (100Mb/s 8 data bits @ 25MHz) for
the current application (few cores)
50 clock cycles to send a package
22
Energy consumption
VHDL simulation is not feasible
Long simulation times for complex applications with
more than two PEs
ISS
Emulates the hardware
Detailed execution, in cycle level, of the same object
code used in the VHDL platform
Use of the estimative in VHDL
Speeds-up the simulation
Creates mechanisms to cycle counting and energy
consumption calculus
Implements interruptions
23
Energy consumption
Simulation tool
Communication among several ISSs
Synchronism
Cycle counting and separation of groups of
instructions
Energy consumption estimative of the whole system
24
Energy consumption
Classification of the instructions
Goal: increases the accuracy of the ISS estimative
6 classes: Arithmetic, Branch and Jump, Load / Store
and Memory Control, Logical, Move and Shift
Benchmark applications
Special applications which contains mostly instructions
of each class (executing for 1ms 25Mhz)
VHDL simulation and results annotation
Energy-per-cycle estimative for every instruction class
Incorporates the results in the ISS tool
25
Simulation Report 1
26
Simulation Report 2
27
Results Monoprocessor Architecture
Energy Energy Error Error

Energy
28
Results Multiprocessor Architecture
Energy Energy Error Error

Energy
Broadcast: 4 processors
MP ADPCM: 2 processors(< 34.62% execution time)
MP JPEG: 4 processors (< 58.14% execution time)
29
Results Interconnection
Energy Energy # packets Error Global

Energy
30
Concluding remarks and Future work

Load balancing techniques seem to be a
good approach for both energy and
performance MPSoC issues
Energy consumption high level estimative
quite accurate:
Allows the prediction of the system energy
based on core and interconnection information
Speeds-up development time of the system
Configurable and extensible processors
31
Open Positions
1 Pos-Doc
2 PhD
2 Master
32
Thank You
Fabiano Hessel
[fabiano.hessel@pucrs.br]
Catholic University of Rio Grande do Sul (PUCRS)

Informatics Faculty - Porto Alegre, Brazil

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Task Migration and Energy

Catholic University of Rio Grande do Sul (PUCRS)

Brazil....Porto Alegre....without beach

Energy consumption estimation tools

Performance evaluation tools

Load balancing methods

Real-time requirements (RTS management)

Energy Consumption and Performance

Load Balancing Methods

Global AMP Local SMP

Interconnection T2 Task continues its

Interconnection T2 Task restarts its

Energy consumption - Methodology

Circuit simulation Test bench

*Leonardo Spectrum (synthesis) and ModelSim (simulation)

Results Monoprocessor Architecture

Energy Energy Error Error

Results Multiprocessor Architecture

Energy Energy Error Error

Energy Energy # packets Error Global

Concluding remarks and Future work

Catholic University of Rio Grande do Sul (PUCRS)

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