1
Supplementary Problems
CHAPTER 2
Problem 1 Explain the operation of a MOS switch.
Solution: One advantage of MOS technology is
that it provides a good switch. Figure 2.48(a) shows a
MOS transistor that is to be used as a switch. Either
terminal, A or B, can be the drain or source of the
MOS transistor depending on the terminal voltages.
For an n-channel transistor, if terminal A is at a higher
potential than terminal B, then terminal A is the drain
and terminal B is the source. The ON resistance
consists of the series combination of r D , r S, and
whatever channel resistance exists. The contribution
from r D and r S is small such that the primary
consideration is the channel resistance.
C
A B
(a)
0VOFF
5VON G the resistor R D is regarded as the (variable) load
Circuit (0 to 2V) (0 to 2V) Circuit
1 S D 2
(b)
Fig. 2.48 (a) An n-channel MOS switch (b)
MOS switch with typical terminal voltages
In the ON state of the switch, the voltage across
the switch should be small and vGS should be large.
Therefore, the MOS device is assumed to be in the
non-saturation region.
In the OFF state of the switch, VGS VT and rOFF
is ideally infinite. Of course, it is never infinite, but
because it is so large, the performance in the OFF
state is dominated by the drain-bulk and source-bulk
leakage current as well as subthreshold leakage from
drain to source.
For the n channel MOS transistor the gate voltage
must be considerably larger than either the drain or
source voltage in order to ensure that the MOS
transistor in ON. The bulk is taken to the most negative
potential for the n channel switch. Typical terminal
voltages are given in Fig. 2.48(b).
Problem 2 How can a JFET be used to supply a
constant current to a variable load?
Solution: A JFET can be used to supply a constant
current to a variable load by connecting its gate
directly to its source, as illustrated in Fig. 2.49. Here,
resistance.
To be able to supply a current that is independent
of RD, the JFET must remain in its pinch off region.
The condition for pinch-off is | VDS | > |VP | | VGS |.
Because VGS = 0 in this case, the condition reduces
to | VDS | > | VP |.
 2 Linear Integrated Circuits

+VDD +VDD were horizontal: rd = D VDS /D ID with D ID = 0. The

IDSS JFET can be used to supply a constant current equal
RD
to some value less than I DSS by biasing it
=
RD appropriately.
Problem 3 Find the ideal value for IC2, IC3, and IC4
IDSS
for the current mirror shown in Fig. 2.51. Assume
that b1 = b2 = 100, b3 = 200, b4 = 150, IBias = 2 mA.
Solution:
(a) n-channel JFET current source
+12 V
+VDD VDD
5

RD IDSS

RD 2 mA IC2 1K IC3 1K IC4 1K

=
1 2 3 4
IDSS Q1 Q2 Q3 Q4
b = 100 b = 100 b = 200 b = 150

(b) p-channel JFET current source

Fig. 2.49 JFET constant current sources Fig. 2.51 For Problem 3

The constant current produced by the JFET is

Neglecting IB,
then ID = IDSS, because that is the drain current in the
IC2 = b2/b1 2 mA
pinch-off region when VGS = 0. So long as the JFET is
in its pinch-off region, the line corresponding to VGS = 100/100 2 mA = 2 mA
= 0 is essentially horizontal, meaning that the same IC3 = b3/b1 2 mA
current flows regardless of VDS (see Fig. 2.50). In = 200/100 2 mA = 4 mA
reality, the line rises slightly to the right, so the current IC4 = b4/b1 2 mA = 150/100 2 mA = 3 mA
source is not perfect. Of course no current source is
Problem 4 For the current mirror circuit shown
perfect. The JFET current source would be perfect if
in Fig. 2.52, PMOS transistors provide the mirror
rd were infinite, which would be the case if the line
current provided by M1. The W/L ratios are specified
ID for each transistor. NMOS transistor M5 is used to
Constant-current region
VGS = 0 bias the current mirror. A bias voltage of 1.2 V is
IDSS
DVDS
DID
applied to the gate of M1 transistor. KPn = 8.16 16
5
A/V2 and KPp = 2.83 105 A/V2. Determine the
DVDS bias current ID1, and the ideal currents for ID2, ID3
rd =
DID and ID4. VTN = 0.7 V, VTP = 0.82 V.
Solution: First, the bS for each transistor need to
|Vp| VDS be calculated.
W1 28
Fig. 2.50 A JFET current source maintains an b 1 = KPP = 2.83 105
L1 2
essentially constant current equal to IDSS in the
pinch-off region. If the characteristic were = 3.96 104
perfectly flat, then D ID would be zero, and vd W2 28
would be infinite b 2 = KPP = 2.83 105
L2 2
 Supplementary Problems 3

6 = 5.974 104
W
b 5 = KPp 5 = 8.16 105 10
L5 2
M2 M3
= 4.08 104
W = 28 M M4 W = 42
1
L 2 W = 28 W = 56 L 2

2
L 2 L 2 Next, calculate the bias current.
IBIAS (ID1) 3 4 5 C5
IBias = ID1 = (VGSS VTS)2
VBIAS 1 2
M5 ID2 RL2 ID3 RL3 ID4 RL4
(1.2 V) 4.08 s 10 4
(1.2 0.7)2 = 50 mA
W 10
L
=
2 =
2
Next, calculate the reflected currents for ID2, ID3,
Fig. 2.52 A MOSFET current mirror with three and ID4
reflected currents
C2 3.96 s 10 4
= 3.96 10 4 I D2 = ID1 = 50 mA = 50 mA
C1 3.96 s 10 4
W
b 3 = KPP 3 = 2.83 105 56 C3 7.92 s 10 4
L3 2 I D3 = ID1 = 50 mA = 100 mA
= 7.92 10 4 C1 3.96 s 10 4
W C4 5.974 s 10 4
b 4 = KPP 4 = 2.83 105 42 I D4 = ID1 = 50 mA = 150 mA
L4 2 C1 3.96 s 10 4
 4 Linear Integrated Circuits

CHAPTER 3 +12 V

Problem 1 What are the currents and voltages in

the single-ended output circuit of Fig. 1?

+12 V +12 V +8.61 V

0.7 V
3 kW

12 V
(a)

+12 V
5 kW

12 V
1.13 mA 1.13 mA
Fig. 1 Problem 1

Solution: Ideally, the tail current IT is

12 V
IT = = 2.4 mA
5 k8 1.13 mA 1.13 mA
Each emitter current IE is 2.26 mA

2.4 mA
IE = = 1.2 mA 12 V
2 (b)
The collector on the right has a quiescent voltage
of Fig. 2 Solution for Problem 1

VC = 12 V (1.2 mA) (3 k W) = 8.4 V Solution:

The collector on the left has 12 V. 15 V
IT = = 2 mA, IE = 1 mA
Including VBE drop across each emitter diode 7.5 k8
12 V  0.7 V 25 mV
IT = = 2.26 mA The ac emitter resistance r e = = 25 W
5 k8 1 mA
2.26 The voltage gain is
IE = = 1.13 mA
2 5 k8
A = = 200
VC = 12 V (1.13 mA) (3 kW) = 8.61 V 25 8
Fig. 4 (a) shows the dc voltages and Fig. 4 (b) The ac output voltage is
shows the dc currents. Vout = 200 (1 mV) = 200 mV
Problem 2 In Fig. 2 what is the ac output voltage? The input impedance of the differential amplifier
If b = 300, what is the input impedance of the is
differential amplifier?
Zin (base) = 2 (300) (25 W) =15 k W
 Supplementary Problems 5

Problem 3 Repeat Example 2 by including VBE The voltage gain for the single-ended output is
voltage drop across each emitter diode. 1 M8
A = = 150
IE = 0.995 mA, re = 26.2 W, A = 191 2 (3.33 k8)

Solution: The ac output voltage is The ac output voltage is

Vout = 191 (1 mV) = 191 mV Vout = 150 (7 mV) = 1.05 V

The input impedance of the differential amplifier The input impedance of the base is
is Z in = 2 (300) (3.33 kW) = 2 MW
Z in = 2 (300) (26.2 W) = 15.7 kW Problem 6 For the ideal differential amplifier
shown in Fig. 5, find (a) the dc output voltages VO1
+15 V
and VO2. (b) the single-ended output gain vO1/(vi1
vi2), (c) the double-ended gain (vO1 vO2)/(vi1 vi2).

5 kW 5 kW +15 V
vout +

6 kW 6 kW

1 mV vo1 vo2

vi1 vi2
7.5 kW

15 V
2 mA
Fig. 3 For Problem 2

Problem 4 Repeat Problem 2 for v2 = 1 mV and 15 V

v1 = 0. Fig. 5 For Problem 6

Solution: Instead of driving the non inverting input
we are driving the inverting input. Ideally, the output Solution:
voltage has the same magnitude of 200 mV, but it is (a) The emitter current in each transistor is
inverted. The input impedance is approximately
I E = I/2 = (2 mA)/2 = 1 mA IC
15 kW.
Therefore,
Problem 5 Find the ac output voltage in Fig. 4.
V O1 = VO2 = VCC ICRC
If b = 300, what is the input impedance of the
= 15 (1 mA)(6 kW) = 9 V
differential amplifier?
(b) The emitter resistance of each transistor is
Solution: Ideally,
re = 0.026 = 0.026 = 26 W
15 V IE 1 mA
IT = = 15 mA
1 M8
vo1  RC  6 k8
= = = 115.4
Since the emitter current in each transistor is half vi1  vi 2 2re 52 8
of the tail current,
25 mV vo1  vo 2  RC  6 k8
(c) = = = 230.8
re =
7.5 NA
= 3.33 kW vi1  vi 2 rea 26 8
 6 Linear Integrated Circuits

Problem 7 Calculate the common-mode gain for +9 V

the differential amplifier in Fig. 6.

Solution: Using RE = ro = 200 kW gives 10 kW 10 kW

C Rc
AC =
ri  2 ( C  1) RE Q1 Q2

75 (10 k8)
=
11 k8  2 (76) ( 200 k8)
Vi
Vi1
Q3
= 24.7 103
R2
R1
8.2 kW 5.1 kW
1 kW

9 V

b1 = b2 = b = 75 Q3
ri1 = ri2 = ri = 11 kW ro = 200 kW
b3 = 75

Fig. 6 For Example 7

 Supplementary Problems 7

CHAPTER 4 100
90
80
Problem 1 Calculate the differential gain in each 70
of the following cases.

CMRR, dB
60
50
Solution: See Fig. 1. 40
Problem 2 A certain op-amp has an open loop 30
20
voltage gain of 100,000 and a common-mode voltage
10
gain of 0.2. Determine the CMRR and express it in 0
decibels. 1 10 100 1 10 100 1 10 100

Hz kHz MHz
Solution: Frequency
A OL = 100,000 and ACM = 0.2
Fig. 2 For Problem 2
AOL 100,000
CMRR = = = 500,000
Acm 0.2
Problem 3 Discuss the CMRR of the 741 at
Expressed in decibels different frequencies with the help of Fig. 2.
CMRR = 20 log (500,000) = 114 dB
Solution: For the 741, CMRR is 90 dB at low
frequencies (see Fig. 4.32). Given equal signals, one a
desired signal, and the other a common mode signal,

+VCC +15 V

V1 V1
+ +

Vid = V1 V2 AVOL = 200,000 Vid = 50 mV AVOL = 200,000

V2 Vout = Vid . AVOL V2 Vout = 10 V

Vout = AVOL Vid

= 200,000 50 mV
VCC Vout = +10 V 15 V
(a) (b)

+15 V +15 V

V1 = 1 V V1 = 999.95 mV
+ + +

Vid = 50 mV AVOL = 200,000 Vid = 50 mV AVOL = 200,000

V2 = 999.95 mV Vout = +10 V V2 = 1 V Vout = 10 V
+

Vid = V1 V2 Vout = AVOL Vid

= 999.95 mV 1 V = 200,000 50 mV
15 V Vout = 10 V 15 V
Vid = 50 mV
(c) (d)

Fig. 1 For Problem 1

 8 Linear Integrated Circuits

the desired signal will be 90 dB larger at the output 30

28
than the common-mode signal. In ordinary numbers, 26
this means that the desired signal will be 24
approximately 30,000 times larger than the common- 22

MPP in volts
20
mode signal. 18
At higher frequencies, reactive effects degrade 16
14
CMRR. It is approximately 75 dB at 1 kHz 56 dB at 12
10 kHz and 20 dB at 1 MHz. 10
8
Problem 4 What is the CMRR of a 741C when the 6
0.1 0.2 0.5 1.0 2.0 5.0 10
input frequency is 100 kHz? Load resistance, kW

Solution: The CMRR of a 741C is approximately Fig. 3 For Problem 5

40 dB at 100 kHz (Fig. 2). This is equivalent to 100,
which means that the desired signal receives 100 times
Solution: The voltage gain at
more amplification than a common-mode signal when
the input frequency is 100 kHz. 1 kHz = 1000
10 kHz = 100
Problem 5 Discuss with the help of an illustration 100 kHz = 10
maximum peak-to-peak (MPP) output of an op-amp. The voltage gain decreases by a factor of 10 each
Solution: The MPP value of an amplifier is the time the frequency increases by a factor of 10.
maximum peak-to-peak output that the amplifier can
produce. Since the quiescent output of an op-amp is fc
100,000
ideally zero, the ac output voltage can swing 70,700
positively or negatively. For load resistances that 10,000
Voltage gain

are much larger than R out, the output voltage can

1000
swing almost to the supply voltages.
With a nonideal op-amp, the output cannot swing 100
all the way to the value of the supply voltages because
10
there are small voltage drops in the final stage of the funity

op-amp. When the load resistance is not large 0

1 10 100 1 10 100 1
compared to Rout, some of the amplified voltage is
Hz kHz MHz
dropped across R out , which means that the final Frequency
output voltage is smaller.
Fig. 4 For Problem 6
Figure 3 shows MPP versus load resistance for a
741C with supply voltages of 15 V. MPP value is
approximately 27 V for an RL of 10 k W. This means Problem 7
that the output saturates positively at +13.5 V and (a) Determine the value of R1 required to give Av
negatively at 13.5 V. When the load resistance = 25 given RF = 55 k W
decreases, MPP also decreases. For a load resistance (b) If Vin = 50 mV, determine I1, IF and V0.
of 275 W, MPP decreases to 16 V, which means that
the output saturates positively at + 8 V and negatively Solution:
at 8 V. RF 55
(a) R1 = = kW = 2.2 k W
25 25
Problem 6 What is the open-loop voltage gain of
the 741C when the input frequency is 1 kHz, Vin 50 mV
(b) I1 = = = 22.73 mA
10 kHz, 100 kHz? R1 2.2 k8
 Supplementary Problems 9

IF = I1 = 22.73 mA The error voltage is

Vo = Av Vin = (25 50 mV) = 1.25 V
Vout 50 mV
Verror = = = 0.5 mV
RF A 100,000

IF Note: The error voltage is very small. This is typical of

R1 IB()
A op-amps with feedback because the open-loop voltage is

+ quite high.
I1 Vid
Vin
+ vo Problem 9 Suppose the 741C of the preceding
IB(+) example is replaced by another 741C that has a voltage
gain of only 20,000 (worst case value on data sheet).
Recalculate the values of A CL, V out, and V error.
Fig. 5 For Problem 7
Comment upon the results.
Problem 8 If the 741C of Fig. 6 has an open loop Solution:
gain of 100,000, what is the closed loop gain? What
are the output and error voltages equal to? ACL = A = 1 = 49.875
1  AC 1  ( 20,000) ( 0.02)
+15 V
Without negative feedback the overall voltage gain
+ has dropped from 100,000 to 20,000, a decrease of 80
+
741C
per cent. With negative feedback, we have less overall
Vin
R1
+
vout
voltage gain, but in return we get a fabulously stable
98 kW 10 kW
15 V
closed-loop voltage gain. In this example, the closed-
loop voltage gain decreases from 49.975 to 49.875, a
decrease of only 0.2 per cent. Therefore, the closed-
R2 2 kW loop gain is nearly independent of the op-amp
voltage gain.
Since ACL is nearly 50
Vout = 50 (1 mV) = 50 mV
Fig. 6 For Problem 8
50 mV
Verror = = 2.5 mV
Solution: The voltage divider has a feedback 20,000
fraction of Compared with the preceding example, the error
voltage has increased by a factor of 5. When the open-
R2 2 k8 loop voltage gain drops by a factor of 5, the error
b= = = 0.02
R1  R2 100 k8 voltage increases by a factor of 5. Therefore, the
The closed loop gain output voltage still remains at approximately 50 mV.
Attempted changes in output voltage are fed back to
A 100,000
ACL = = the input producing an error voltage that
1  AC 1  (100,000) (0.02)
automatically compensates for the output change.
= 49.975
Problem 10 Show examples of typical op-amp device
An approximate value of ACL is given by
pinouts. Explain.
1
ACL = 1 = = 50 Solution: Most op-amps are in the form of
C 0.02
integrated circuits which typically contain one, two
This is an accurate approximation for the gain of
or four amplifiers. Figure 7 shows examples of device
amplifiers that use non-inverting feedback.
pinouts. The pins of the integrated circuits are
If Vin = 1 mV, the output voltage is
numbered anticlockwise when viewed from above
Vout = ACL Vin = 50 (1 mV) = 50 mV (the side away from the pins), as shown in Fig. 7. The
 10 Linear Integrated Circuits

Output 1 14 Output

Inv inp 2 13 Inv inp

+ +
Non-inv inp 3 12 Non-inv inp
Offse
1 8 NC Output 1 8 V+ V+ 4 11 V
null
Inv inp 2 7 V+ Inv inp 2 7 Output Non-inv inp 5 10 Non-inv inp
+ + +
Non-inv Non-inv +
+ 6 Output 6 Inv inp Inv inp 6 9 Inv inp
inp 3 inp 3
Offset Output 7 8 Output
V 4 5 V 4 5 Non-inv inp
null
(a) Single op-amp (b) Dual op-amp (c) Quad op-amp

Fig. 7 Single op-amp, dual op-amp and quad op-amp device pinouts

orientation of the device is indicated by a notch at This input of each MOSFET pair is internally
one end of the package, or by a dot against pin connected to the standard CMOS protection network
number one or both. The label NC against a pin (Fig. 9) and all six MOSFETs are enhancement-mode
represents no connection, V indicates the negative devices, Q1, Q3, and Q5 are p-channel types and Q2,
supply connection, and V +, the positive supply. Some Q4 and Q6 are n-channel types. Figure 9 also shows
devices have 'offset null' inputs which may be used the terminal notations of the two MOSFET types, the
to remove the effects of an offset voltage. The circuity B terminal represents the bulk substrate.
required for this null function differs from one device
S
to another. 14
G
B
Problem 11 Illustrate and explain the 4007 mB D
MOSFET array. (p) p-channel MOSFET
R1
IN
Solution: The 4007 mB is the cheapest (and possibly 1-5k0
D
(n)
the most useful) of all transistor array ICs and is G
B

actually a member of the CMOS digital IC family. S

n-channel MOSFET
Figure 8 shows the functional diagram and pin 7
numbering of the IC, which houses two
Fig. 9 Internal input-protection network (within
complementary pairs of independently accessible
dotted lines) on each input of the 4007 mB and
MOSFETs plus a complementary pair that is MOSFET terminal notations G = Gate, D = Drain,
connected as a simple CMOS inverter. S = Source, B = Bulk substrate

14 (VDD) 2 11
In use, the input terminals must not be allowed to
rise above VDD (the supply voltage) or fall below VSS
Q1 Q3 Q5 (zero volts).
(p) (p) (p)
6
13
3
1
10 12 Problem 12 How will you disable 4007 mB
8 5 complementary MOSFET pairs?
Q2 Q4 Q6 Solution: Each MOSFET element of the 4007 mB
(n) (n) (n)
can be used as either digital or analog (linear)
7 (GND) 4 9 amplifier and all unused elements must be suitably
disabled, by connecting them as standard CMOS
Fig. 8 Function diagram of the 4007 mB dual
CMOS pair plus inverter inverters and tying their inputs to ground, as shown
in Fig. 10.
 Supplementary Problems 11

VDD (+ve) VDD (+ve) VDD (+ve) Individual MOSFET pairs can be disabled by tying
14 14 their source to their substrate (B) and leaving the
6
14
13 10
11
12 3
2
1
drain open circuit.
Q1 Q 2 Q5 Q 6 Q3 Q 4
8 5
7 7 7
9 4
0V 0V 0V

Fig. 10 Individual 4007 mB complementary

MOSFET pairs can be disabled by connecting
them as CMOS inverters and grounding their
inputs
 12 Linear Integrated Circuits

CHAPTER 5 Problem 3 How can the tendency of an op-amp

differentiator to oscillate be avoided?
Problem 1 Calculate the output voltage of an op-
Solution: To avoid oscillations, a practical op-amp
amp summing amp for the following sets of voltages
differentiator usually includes some resistance in
and resistors. Use Rf = 1 MW in all cases.
series with the capacitor as shown in Fig. 3. A typical
(a) V1 = +1 V, V2 = +2 V, V3 = +3 V, R1 = 500 kW, value for this added resistance is between 0.01 R to
R2 = 1 M W , R3 = 1 M W 0.1 R. With this resistance, the closed-loop voltage
(b) V1 = 2 V, V2 = +3 V, V3 = +1 V, R1 = 200 kW, gain is between 10 and 100. The aim is to limit the
R2 = 500 kW, R3 = 1 MW closed-loop voltage gain at higher frequencies,
Rf
where the oscillation problem arises.
R1 R
V1
R2 +VCC
V2
R3 C
V0 vin
V3
+ 0.01R to 0.1R vout
+

VEE

Fig. 1 For Problem 1 Fig. 3 For Problem 3

Solution: Problem 4 Illustrate and briefly explain a 4-input

8
 1000 k 1000 k8 1000 k8 audio mixer.
(a) V O =  500 k
 8 ( 1 V)  1000 k8 ( 2 V)  1000 k8 ( 3 V)!"
= [2(1 V) + 1(2 V) + 1(3 V)] = 7 V Solution: Figure 4 illustrates the circuit of a 4-input
 1000 k 8 1000 k8 1000 k8 audio mixer by ac coupling the input signals and
(b) V O =  200 k
 8 (  2 V)  500 k8 (  3 V)  1000 k8 ( 1 V)!" giving R5 the same value as the feedback resistor.
= [5(2 V) + 2(3 V) + 1(1 V)] = +3 V R1 R6
C1
100 k 100 k
Problem 2 Illustrate the output of (a) an integrator Input 1
220 n

and (b) a differentiator, when the input is a train of C2 R2

220 n 100 k +9 V
rectangular pulses. Input 2
C3 R3 2 7
100 k
Solution: Figure 2. Input 3
220 n
741
6
C4 R4 3
+ 4
220 n 100 k
Input 4 R5 Out
Vin 9 V
100 k

0V

0 Fig. 4 4-input audio mixer

T

0 Problem 5 Illustrate a summing amplifier using

vin
both sides of the op-amp. Also give the relevant
formulas.
V vout
T Solution:
(a) (b) Vout = A1v1 + A2v2 + A3v3 + A4v4
Fig. 2 For Problem 5.87  RF
A1 =
R1
 Supplementary Problems 13

 RF Problem 7 Determine the output voltage of the DAC

A2 = in Fig. 5.91 (a).
R2
 RF  R4 || R5  Solution: The sequence of four-digit binary codes
A3 =   1   represented by the waveforms in Fig. 7 are applied to
 R1|| R2   R3  R4 || R5 
the input. A HIGH level is a binary 1 and a LOW level
 RF  R3|| R5  is a binary 0. The least significant digit is DO.
A4 =   1  
 R1|| R2   R4  R3|| R5 
200 kW
D0
R1
v1
10 kW
100 kW
D1
RF
v2
50 kW
R2 D2 Vout

25 kW +
vout D3
+
R3 (a)
v3
R5
0 1 2 3 4 5 6 7 8 9 10 11 12 1314 15
v4 +5 V
D0 0
R4 +5 V
D1 0
Fig. 5 Summing amplifier using both sides of +5 V
D2 0
the op-amp +5 V
D3 0
(b)
Problem 6 Describe the operation of a scaling adder.
Solution: One method of D/A conversion uses a Fig. 7 For Problem 7
scaling adder with input resistor values that represent
the binary weights of the input digital code. Figure 6 First, determine the current for each of the
shows a four-digit digital to analog converter (DAC) weighted inputs. Since the inverting input of the op-
of this type called a binary-weighted resistor DAC. amp is at 0 V (virtual ground) and a binary 1
The switch symbols represent transistor switches for corresponds to a HIGH level (+5 V), the current
applying each of the four binary digits to the inputs. through any of the input resistors equals 5 V divided
The inverting () input is at virtual ground, and so by resistance value.
the output voltage is proportional to the current
through feedback resistor (sum of input currents). The 5V 5V
IO = = 0.025 mA, I1 = = 0.05 mA,
lowest-value resistor R corresponds to the highest 200 k8 100 k8
weighted binary input (23). All of the other resistors
are multiples of R and corresponds to binary weights 5V 5V
I2 = = 0.1 mA, I3 = = 0.2 mA
22, 21 and 20. 50 k8 25 k8
+V 8R There is no current at the inverting op-amp input
20 Rf because of its extremely high impedance. Therefore,
4R all of the input current flows through Rf. Since one
21 end of Rf is at 0 V (virtual ground), the drop across Rf
2R

equals the output voltage, which is negative with
Vout
22
respect to virtual ground.
+
R V out(D ) = (10 kW) (0.02 mA) = 0.25 V; Vout(D )
0 1
23
= (10 kW)(0.05 mA)
= 0.5 V
Fig. 6 A scaling adder as a four-digit digital to
analog converter (DAC)
 14 Linear Integrated Circuits

Vout(D = (10 kW)(0.1 mA) = 1 V; Vout(D )

0000
0001
0010

0100
0101

1000
1001
1010

0000
0011

0110

0011
1100
1101
0111

1110
1111
2) 3
= (10 kW) (0.2 mA)
0 Binary input
0.25
= 2 V 0.50

The first binary input code is 0000, which produces

0.75
1.00
an output voltage of 0 V. 1.25

The next input code is 0001 (decimal 1), which 1.50

1.75
produces an output voltage of 0.25 V. 2.00
The next input code is 0010 (decimal 2), which 2.25
2.50
produces an output voltage of 0.5 V. 2.75
The next input code is 0011 (decimal 3), which 3.00

produces an output voltage of 0.75 V. 3.25

3.50
Each successive binary code increases the output 3.75

voltage by 0.25 V. So, for this particular straight VOUT

binary sequences on the input, the output is a stair

Fig. 5.92 Solution for Problem 7
step waveform going from 0 V to 3.75 in 0.25 V
steps as shown in Fig. 5.79. If the steps are very small
the output approximates a straight line.
 Supplementary Problems 15

CHAPTER 6 +V

8.82 V = Vref
Example 6.50 Design the circuit for Fig. 6.63(a) to Vo
have VUT = 12 V and VLT = 8 V. Assume that Vsat = +

15 V. V
10 kW 75 kW
Solution: Ei
R nR
V  ( Vsat )
(i) VH = VUT VLT = sat and Vctr = (a) The ratio of nR to R or n and Vref
n determines VUT, VLT, VH, and Vctr

VUT  VLT
= Vref  1  1 
+Vo and Ei

2  n Vo
+Vsat
12 V  8 V
VH = 12 V 8 V = 4 V and Vctr = VUT = 12 V
2 VH = 4 V
Vctr = 10 V

= 10 V VLT = 8 V
Ei
Vsat  ( Vsat )  15 V  (  15 V)
Vref = 8.82 V
(ii) n = = = 7.5
VH 4 0 t

Vctr 10 V
(iii) Vref = = = 8.82 V
1  1/ n 1  1/ 7.15
(iv) Select R = 10 k W and nR = 75 k W.
The relationship between Ei and V O shown in Vsat
Figs 6.63 (b) and (c).
Vo

Example 6.51 Design the circuit for Fig. 64(a) to (b) Vo and Ei vs. time

have VUT = 12 and VLT = 8 V. Assume that Vsat = +Vo

15 V. What are the requirements of voltage level +Vsat

Vo vs. Ei
detector with hysteresis?
Solution:
(i) VH = 12 V 8 V = 4 V
Vref Vctr
12 V  8 V
Vctr = = 10 V 8.82 V 10 V
2 0
VLT VUT
Ei

( Vsat )  ( Vsat ) 8V 12 V
(ii) n = 1
VH
15 V  (  15 V)
= 1 = 6.5
4V Vsat
VH = 4 V
n 1 6.5  1 Vo
(iii) Vref = (Vctr) = (10) = 11.53 V (c) Vo vs. Ei
n 6.5
(iv) Choose R = 10 k W; therefore, resistor nR = Fig. 6.63 Non-inverting voltage-level detec-
6.5 10 = 65 k W tor with hysteresis. Center voltage Vctr and
hysteresis voltage V H cannot be adjusted inde-
The relationship between Ei and VO are shown in pendently since both depend on the ratio n
Fig. 6.64 (b) and (c).
 16 Linear Integrated Circuits

The requirements of a voltage level detector are (3) the setting of VH and Vctr should not interact.
(1) an adjustable resistor to set the value of VH (4) The centre voltage Vctr should equal or be
(2) a separate adjustable resistor to set the value simply be related to an external reference
of Vctr. voltage Vref.

+V

Ei
Vo
+

V
10 kW 65 kW
11.53 V = Vref
R nR
(a) The ratio of nR to R or n and Vref
determines VUT, VLT, VH, and Vctr

+Vo

Ei Vo Vo vs. Ei
+Vsat +Vsat
VUT = 12 V
VH = 4 V
VLT = 8 V
5 Ei VctrVref
Vctr = Vref =
10 V V 11.53 V
0 t 0 Ei
VLT = VUT =
8V 12 V

Vsat Vsat
VH = 4 V
Vo
(b) Vo and Ei vs. time (c) Vo vs. Ei

Fig. 6.64 Inverting voltage-level detector with hysteresis. Center voltage V ctr and hysteresis
voltage VH cannot be adjusted independently since both depend on n
 Supplementary Problems 17

CHAPTER 8 sink that can accommodate a TO-3 package (d)

Diagram showing the mounting of a TO-3 or
Problem 1 Illustrate typical power amplifier TO-66 transistor package on a heat sink with an
heatsinks. insulating washer

Solution: Problem 2 A transistor with VCE = 25 V and IC 1 A

(a) Silicone Case has a junction-to-case thermal impedance of
greese
Be 0 washer 1C/W. Select a heatsink which will keep the junction
temperature from exceeding 90C when the ambient
Chassis
temperature is 25C. (The NC-421, NC = 423 and
(b) Fin-type NC-441 all have qC < 1.6C/W).
heat sink
Solution: P D = VCE IC = 25 V 1A = 25 W
Tj  TA
q CA = qCS + qSA = q jc
PD

90o C  25o C
= 1C/W
25 W
= 1.6C/W
As all three transistors have qC < 1.6C/W , choose
(c) the smallest and least expensive of the three, NC-
421s.
Problem 3 Draw the pin configuration and a
practical application of the TDA2822.
Solution:

6 sheet
Output 1 1 8 +In (1)
metal screws
V+ 2 7 In (1)
Power TDA 2522
transistor Output 2 3 6 +In (2)

GND 4 5 In (2)
Insulator
Clearance
holes Top view
Chassis or
+6 V
heat sink 10 m
Clearance +
holes 2
Insulating
bushing 47 k 7 L/H SPKR
L/H + 470 m
input 1 4R0 to 32R
Socket Volume
+ 8 + 100 n 4R7
Screws or rivets 0V
0V 100 m
(not in TDA
mounting kit)
2822
47 k 6 R/H SPKR
R/H + 470 m
(d) input 3 4R0 to 32R
Volume
+ 5 + 100 n 4R7
Fig. 8.40 (a) Method of mounting transistors 0V
0V
that are encased in a metal TO-5 package. 10 m
Mounting the transistors case close to the chas- 4
0V
sis using a beryllium oxide insulating washer
(b) Using a separate heat sink pressed on to Fig. 8.41 Pin configuration of the TDA2822
the transistor (c)Typical power transistor heat dual amplifier IC
 18 Linear Integrated Circuits

Problem 4 Draw the pin configuration of low power 5 10

IC-TBA820M. Give one application. Input 1 6 9 Input 2

Feedback 1 7 8 Feedback 2

Solution: See Fig. 8.45. Top view

2k0 100 k
V+ (see text)
V+
C1 R1 + C2 14 100 n
100 n 56 R 100 n
8 7

Vin 7 + C7 100 n 2
RV1 3 5 100 n 8
TBA820M + 2R7
k
100 k 1 + V
Volume 6 C5 CS 100
1 3,4,5
4 470 p LM1877
2 10,11,12
C3 + 220 p R3
+ 1R0 SPKR k 0
100 m C4 (see +
13
R2 C6 text)
47 m 100 n 8
120 R 220 n 2R7
510R
0V 100

Comp 1 8 Reflection 100 k

Gain
Input
GND
Fig. 8.42 Pin configuration of IC-TBA829M
and a low power audio amplifier circuit
Problem 5 Draw the pin configuration and one
application each of LM1877 dual 2 W amplifier IC
using a single-ended and a dual power supply.
TBA Bootsloep
820M V+ Fig. 8.43 Pin configuration of IC-LM1877 and
4 5 Out one application each of the IC using a single-
ended and a dual power supply
Problem 6 Draw the pin configuration of the
National Semiconductor LM2879T dual 8 W audio
power amplifier IC and give one application each of
the IC using a single ended and a dual power supply.

Solution: See Fig. 8.46. Solution: See Fig. 8.47.

510 R 100 k 11 V+
10 OUTPUT 2
+ V+
50 m 9 GND
14 100 n
8 INPUT 2
7 7 FEEDBACK 2
470 m
2 + 6 NC
100 n 8 5 FEEDBACK 1
Input + 2R7 4 INPUT 1
8R0
50 m 1M0 3 GND
1 100 n GND
+ 3,4,5 2 OUTPUT 1
LM1877
10,11,12 0V 1 BIAS
1M0 Top view
0
Input + 470 m
100 n 13 + 510 R 100 k
8
2R7 +
+ 8R0 50 m +28 V
510R
50 m 11 100 n
100 n
5
100 k 470 m
2 +
100 n 4
Input 1 + 2R7
Bios 1 14 V+ 8R0
50 m 1M0 100 n
OUT 1 2 13 OUT 2 + 1 3,0
LM2879T
TAB 0V
3 12
1M0
GND 4 LM1877 11 GND 8
Input 2 + 470 m
100 n 10 +
5 10
7
Input 1 6 2R7
9 Input 2 + 510R 8R0
50 m
Feedback 1 7 8 Feedback 2 100 n

Top view 100 k

 Supplementary Problems 19

V+ +21 V
11 470 n 82 R
5 +
Feedback 47m
2 6 150 R
1 OUT 1m0
4 1 +
Input + + 7
5 220m
TDA1514A

Signal input
1
Bias
BIAS 0 3 2 3R3
generator 8 22 k
4 SPKR
4R0
8
Input + 22 k 220 p 22 n
10 880 R
2 OUT
7
Feedback 0V
470 n 470 k

3, 9 +
3m3
GND 21 V

1. INPUT
2k0 100 k 2. SOAR
+ +14 V 3. MUTE
4m7 Metal
11 100 n 4. V
mounting
basis 5. OUTPUT
5 (V) 6. V+

100 n 2 7. BOOTSTRAP
Input 1
4 8. 0 V
+ 2R7 9. +INPUT
100 k 8R0
14 V
100 n Bottom view
1 3,9
LM1877
TAB 0V Fig. 8.45 Pin configuration of the super-fi
8
audio amplifier IC-TDA1514A. An application of
100 k the IC using split supplies
+
13
Input 2
100 n 7
2R7 Solution: The very thin layer of S i O 2, silicon
4m7
+ 510R 8R0 dioxide, between gate and channel is very susceptible
100 n
to high voltages and is very easily punctured, even
100 k by static electricity resulting from the transistor
Fig. 8.44 Pin configuration and simple equiva-
sliding around in a plastic bag. A large electrostatic
lent circuit of the dual 8 W audio power discharge may also result from a person who picks
amplifier IC-2879T. The IC usage with a single up the transistor from its case and brushes the gate
ended and a dual power supply lead against some grounded object. In a relatively
dry atmosphere, a static potential of 300 V is not
Problem 7 Give the pin configuration of the super-
uncommon on a person who has high resistance soles
fi audio amplifier IC-TDA1514A designed for use
on his shoes.
with split supplies. Also give one practical application.
As a result MOSFETs are protected by a shorting
Solution: See Fig. 8.48. ring, Fig. 8.50 (a), that is wrapped around all four
Problem 8 Give the pin configuration of the 9.5 W terminals during shipping and must remain in place
audio IC-TDA-1020 with one practical application. until after the device is soldered into position. The
MOSFET should never be inserted into or removed
Solution: See Fig. 8.49. from a circuit with the power on. The JFET is not
Problem 9 What type of protectionis provided to subject to these restrictions.
MOSFETs and why?
 20 Linear Integrated Circuits

GND 1 Solution: The PAO4 is an example of a high-

P.A. OUTPUT 2 voltage, high-current hybrid IC power operational
V+ 3 amplifier. It can operate with supply voltages up to
BOOTSTRAP 4 200 V and is capable of a peak current swing of 20 A.
RIPPLE REJECT 5 It has a dc open-loop gain of 102 dB (typ) and 94 dB
P.A. INPUT 6 (min). It offers a gain bandwidth product of 2 MHz
PREAMP OUTPUT 7 and a full power bandwidth of 90 kHz when producing
PREAMP INPUT 8 an output voltage swing of 180 V peak-to-peak. This
GND 9
is an FET input operational amplifier, so along with
Top view
these very impressive power output characteristics
is an input bias current of 10 pA (typ), 50 pA (max)
+14.4 V
100 n 330 k 100 n and an input impedance of 1011 W (typ) in parallel
Signal
input 5 C3 with 13 pF (typ).
+ 8 3
RV1 4 + 100 m C4 A simplified schematic of the PAO4 is given in
10 k 2000 m
1m0
TDA1020
2 + Fig. 8.51. The input stage consists of the Q1 Q2
6
9
1
100 n
PMOS differential amplifier stage that is biased by a
7 SPKR current source comprised of Q 5, R 5 and D 1. The
2R0
C2
C1 4R7 differential amplifier drives an npn current mirror
3n3
150 n
active load that is comprised of Q3 and Q4. The second
0V
stage uses Q6 as a common-source amplifier stage
with a current source active load. The last stage uses
Fig. 8.46 Pin configuration of the IC-TDA1020 Q8 and Q9 in the form of a complementary NMOS-
and on practical application, for use in automo-
biles
PMOS class AB source-follower push-pull output
stage. Transistor Q7, in conjunction with resistors R7
Some MOSFETs have a built-in gate protection, and R8, generates a voltage drop that is used to bias
a system built into the device to get around the the Q 8 , Q 9 push-pull output stage for class AB
problem of a high voltage on the gate causing a operation to minimize crossover distortion.
puncturing of the oxide layer, thus removing the need There are two separate sets of positive and
for the listed precautions. negative supply voltage connections, VBOOST and
The symbol in Fig. 8.50 (c) shows that between VS. The operational amplifier can be operated with
each gate and the source is placed a back-to-back or +V BOOST = V S and V BOOST = V S. Under these
front-to-front pair of diodes, which are built right into conditions, the peak output voltage swing is about
the p-type substrate (one pair on each side of the 5 V less than supply voltage under no load conditions,
MOSFET proper). and about 10 V less that the supply voltage for a
These diodes are designed so that if either gate load current of 20 A. For a larger output voltage swing
exceeds +10 V typically with respect to the source, and a greater power conversion efficiency, the boost
the upper diode will conduct and the lower diode will voltage can be raised by as much 20 V above the
break down (Zener effect) providing a shunt path for supply voltage.
excessive charge from gate to source. Likewise, if the A boost voltage that is 5 V above the supply
gate voltage exceeds 10 V, the lower diode conducts voltage is enough to cause the output transistor to
and the upper diode breaks down. The normal be driven into saturation and results in a substantial
application of signal voltages will not be affected. improvement in the output voltage swing and in
These diodes also guard against in-circuit transients. power conversion efficiency. With this value of boost
voltage, the peak output voltage swing is only 2 V
Problem 10 With the help of a simplified digram
less than the supply voltage under no load
describe the operation of the IC-PAO4 (Apex
conditions, and 5 V less for a 20 A load current.
Microtechnology) power operational amplifier.
 Supplementary Problems 21

Oxide
Gate 1 insulation Gate 2
internal internal

P P Drain 1 P P
Source 1 Drain 2
source 2
N N
N N N
Channel 1 Channel 2
Source Drain
(N) (N)
terminal terminal
P
Unit No. 1 Unit No. 2

Gate-protection Gate-protection
diodes diodes

(a) (b)

2 3 2 3

1. Drain
2. Gate
3. Gate 1
4. Source
(substrate and case)

1 4 1 4
(c) (d)

Fig. 8.47 (a) Shorting spring for MOSFETs that do not contain the integrated protection (b) Dual
gate protected n-channel depletion type MOSFET, cross-sectional view (c) Symbol of the dual gate
protected MOSFET (d) Showing how a dual gate may be operated as a single gate protected MOSFET
by joining gates 1 and 2

Problem 11 Determine the ideal maximum peak VCC 20 V

output voltage and current for the circuit shown in V O(peak) VCEQ =
= = 10 V
2 2
Fig. 8.52.
The maximum peak output current is
Solution: The ideal maximum peak output voltage
VCEQ 10 V
is IO(peak) IC(sat) = = = 1.25 A
V O(peak) VCEQ VCC = 20 V
RL 8 8
The ac output power is
The ideal maximum peak current is
P O = 0.25 IC(sat) VCC
VCC 20 V = 0.25 (1.25 A) (20 V) = 6.25 W
IO(peak) IC(sat) = = 1.25 A
RL 16 8
The dc input power is
The actual maximum values of peak voltage and
current are slightly smaller. I C ( sat )VCC (1.25 A) (20 V)
P DC = =
Problem 12 Find the maximum ac output power and
8 8
= 7.96 W
the dc input power of the amplifier in Fig. 8.53. Also
determine the input resistance assuming bac = 50 The input resistance is
and r e = 6 W. R in = bac (re + RL ) = 50 (6 W + 8 W)
Solution: The maximum peak output voltage is = 700 W
 22 Linear Integrated Circuits
+VBOOST

+V6

R5
D1
IB

Q8

Q5
IA

R7 Q7
R1 R2
Output
Noninverting
Inverting input R8
input

Q1 Q2
Q6
Q9

Q3 Q4 RCOMP

CCOMP

R3 R4 R6

VBOOST V5

Fig. 8.48 Simplified schematic of the PAO4 power operational amplifier

+20 V VCC
+20 V

R1
R1
470 W
C1 100 W
Q1
Q1
D1 10 mF
Vout
D1 C3 V
out
D2
D2 10 mF
Vs Q2 R6 RL
C2
16 W Q2 8W
R2 Vin
470 W 10 mF
R2
100 W

20 V
Fig. 8.50 For Example 8.58
Fig. 8.49 For Example 8.57
 Supplementary Problems 23

CHAPTER 9 Problem 2 In Fig. 9.5, R = 1 kW and mR = 99 kW.

Problem 1 Discuss a current amplifier.
Solution: There is no point in converting a current
to an equal current but a circuit that converts a small
current to a large current can be very useful. The
circuit of Fig. 9.67 is a current multiplier or current
amplifier (technically a current-to-current converter).
The signal current source Isc is effectively short-
circuited by the input terminals of the op-amp. All of
Isc flows through mR, and the voltage across it is
mR I sc . Resistor mR is known as a multiplying
resistor and m is a multiplier. Since R and mR are in
parallel, the voltage across R is also mRIsc. Therefore,
the current through R must be Isc. Both currents add
to form the load current IL. IL is an amplified version
of Isc and is found from
IL = (1 + m) Isc (9.36)
The load does not determine load current. Only
the multiplier m and Isc determine the load current.
For variable current gain, the mR and R can be
replaced by a single 100 kW potentiometer. The wiper
goes to the emitting diode, one end to the ground
and the other end to the () input. The optical coupler
isolates the op-amp circuit from any high voltage
load. DP is an ordinary silicon diode that protects
the emitting diode against a reverse bias voltage.
Find the current IL through the emitter diode of the
opto-coupler.
Solution:
m = 99 kW/1 kW = 99
IL = (1+99) (10 mA) = 1.0 mA
Problem 3 Explain the working of a light-column
voltmeter.
Solution: A light-column voltmeter displays a
column of light whose height is proportional to
voltage. Manufacturers of audio and medical
equipment may replace analog meter panels with light-
column voltmeters because they are easier to read
at a distance.
A light-column voltmeter is shown in Fig. 9.68.
Rcal is adjusted so that 1 mA flows through the equal
resistor divider network R 1 to R 10. Ten separate
reference voltages are established in 1-V steps from
1 V to 10 V.
When Ei = 0 V or less than 1 V, the outputs of all
op-amps are at Vsat. The silicon diodes protect the
light-emitting diodes against excessive reverse bias
voltage. When Ei is increased to a value between 1
and 2 V, only the output of op-amp 1 goes positive to
light LED 1. The op-amps output current is
automatically limited by the op-amp to its short-circuit

R = 1 kW
321

mISC
IL = (1 + m)ISC
0V

99 kW

mR ISC
To
Signal +V DP high
current voltage
source ISC
7
100 mA
321

2
0V 741
3 6 Optical
+
4 coupler
load

Fig. 9.51 Current amplifier with optical coupler load

 24 Linear Integrated Circuits

+15 V = +V

Rcal 0 10 kW
+V

220 W
Vref10 = 10 V #10
+ LED 10
R10 = 1 kW
V

+V

220 W
Vref9 = 9 V #9
+ LED 9
R9 = 1 kW
V

+V
321

R3 to R8
all 1 kW
220 W
Vref2 = 2 V #2
+ LED 2

R2 = 1 kW V
+V

2 7
220 W
Vref1 = 1 V #1
3 6
R1 = 1 kW + LED 1
+ 4
Ei
V

Fig. 9.52 Light-column voltmeter. Reference voltages to each op-amp are in steps of 1 V. As Ei
is increased from 1 V to 10 V, LED 1 through LED 10 light in sequence. R1 to R10 are 1% resistors.
The op-amps are 741 8-pin mini-DIPs

value, approximately 20 to 25 mA. The 220 W output one-half LM324 quad op-amps. Some manufacturers
resistances divert heat away from the op-amp. have designed IC packages for this particular
As Ei is increased, the LEDs light in numerical applications, such as National Semiconductors
order. This circuit can also be built using two and LM3914.
 Supplementary Problems 25

CHAPTER 10
Ground 1 8 V+
Problem 1 Give a typical application of the LM386.
NC C
Solution: A typical application of the LM386 as a Square
NE566
R
power amplifier in a radio receiver is shown in wave out
Fig. 10.29. The detected AM signal is fed to the Triangle
4 5
Modulation
wave out input
inverting input through the volume control
potentiometer R 1 and resistor R 2, C1 is the input
Fig. 10.30 Outline and pin configuration of
coupling capacitor and C 2 is the power supply the NE566
decoupling capacitor. R2 and C3 filter out any residual
RF or IF signal that may be on the output of the Solution: The NE566 is a general purpose generator
detector. R 3 and C 5 provide additional filtering that produces excellent simultaneous square and
before the audio signal is applied to the speaker triangle output (up to 1 MHz) that can be frequency
through the coupling capacitor C7.

+9 V
C1 C4

C2 10 mF
1 mF
0.1 mF
R2 6
R1 2 1
C7
10 W 8 R3
1.0 W C3 5
LM386
0.0022 mF 47 W
Volume 3 7 220 mF
+
control 4 C5 C6
10 mF 0.047 mF

Fig. 10.29 The LM386 as an audio power amplifier

Problem 2 Give the pin configuration and functional modulated (FM) or frequency shift keyed (FSK) via a
block diagram of the IC-NE 566. Explain briefly. voltage control input terminal. Figure 10.30 shows
the ICs outline and pin configuration. Figure 10.31
V+

R
6 8
vc Out
Modulation Current Schmitt Buffer
input 5 source trigger amplifier 3

Out
Buffer
amplifier 4
NE566

7 1
C

0V

Fig. 10.31 Functional block diagram of the NE566

 26 Linear Integrated Circuits

shows its functional block diagram plus a few R, and can be varied or modulated over a similar range
essential external components. via Vc. Thus the Fig. 10.46 circuit acts as a fixed-
In essence, the NE566 is a VCO with buffered frequency FM waveform generator; it operates at
output; the VCO section is made up of a pair of about 5 kHz with R and C values of 4 k and 10 nF. The
voltage-controlled current sources that linearly 1 nF capacitor between pins 5 and 6 enhances circuit
charge or discharge an external timing capacitor, and stability.
a Schmitt trigger that flips the current sources when
V+ (10 to 24 V)
the capacitor voltage reaches preset levels. A linear
triangle wave is generated across the capacitor, and R1
R
(2 k0 to
a high-quality square wave is generated at the 1 k5 20 k) Out
Schmitt output; these waveforms are fed to the 6 8
1n0
outside world via simple buffer amplifiers.
C1 VC 3
Problem 3 Discuss a simple fixed frequency 5
NE566
Out
application of the NE566.
Mod 4
Solution: The NE566's operating frequency is set input 7 1
R2
by an external resistor R and capacitor C, and by the 10 k
C
voltage Vc, applied to its control terminal and is
roughly equal to 2 (V+ V)/RC.V+. R must be in the
range 220 kW; C can have any value, and Vc must be 0V
between 75 and 100 per cent of the supply voltage
Fig. 10.32 Simple fixed-frequency applica-
value. Frequency can be varied over a 10 :1 range via tion circuit
 Supplementary Problems 27

CHAPTER 11 +V = +10 V

Problem 1. Explain the false lock in phase locked R1 + C2

loops. How can it be alleviated? 12 kW 10 mF
C3
Solution: The PLL could lock to twice the
0.001 mF
frequency of the input signal, three times the 10 8
frequency of the input signal or any other multiple.
7 Demodulated
Alternatively, it could lock to a submultiple of the Input
2
output
frequency of the input signal (i.e., one-half, one-third, 6 Reference
output
or some other submultiple). This false lock will occur NE565
4
whenever the free-running frequency of the VCO is VCO output
3
closer to a multiple or submultiple of the input 5

signals frequency rather than to its actual frequency.

False lock can only be alleviated by somehow 9 1
guaranteeing that the free-running frequency of the C1 0.01 mF
oscillator is closer to the actual input frequency than
it is to some multiple or submultiple thereof. This
requires a prior knowledge of the input signal and is
a limitation on how much the input signals frequency V = 10 V
can vary. Fig. 11.42 For Problem 3
Problem 2. A PLL is locked onto an incoming
signal with a frequency of 1 MHz at a phase angle of Solution:
50. The VCO signal is at a phase angle of 20. The 1.2 Hz
f out (11.47)
peak amplitude of the incoming signal is 0.5 V and 4 R1C1
that of the VCO output signal is 0.7 V. 12.
= Hz
(a) What is the VCO frequency? 4 (12 s 103) ( 0.01 s 106)
(b) What is the value of the control voltage = 2.5 kHz
being fed back to the VCO at this point?
8 f out
fL = Hz (11.48)
Solution: V
(a) Since the PLL is in lock 8 ( 2.5 s 103)
fi = fo = 1 MHz = = 1 kHz
20
(b) qe = qi qo = 50 20 = 30 1/ 2
 fL
VV fC =  3 !
Hz (11.49)
Vc = i o cos qe  (2Q ) (3.6) (10 ) ( C2 ) "
2
where C2 is in farads.
(0.5 V s 0.7 V )
= cos 30 1/ 2
2  (10) 3
= (0.175 V) cos 30 = 0.152 V fC =  3 6 !
 ( 2Q ) ( 3.6 s 10 ) (10 s 10 ) !
 "
Problem 3. In the circuit in Fig. 11.42, determine = 66.49 Hz
the free-running frequency fout, the lock range fL,
and the capture range fC.
 28 Linear Integrated Circuits

fout, fL and fC are illustrated in Fig. 11.43. Lock range

Capture
Lock range fL range
Capture range
fC fC
fOUT 1.0 2.894 3.106 kHz 5.0 kHz
1.5 k 2.433 k 2.5 k 2.566 k 3.5 k kHz kHz 3 kHz
Frequency, Hz
Frequency (Hz)

Fig. 11.45 Solution for Problem 4

Fig. 11.43 Solution for Problem 3
Problem 5. The log amplifier shown in Fig. 11.46
Problem 4. In the circuit in Fig. 11.43, determine has the following circuit parameters.
the free running frequency fout, the lock range fL
R1 = 5 k W, VT = 26 mV, ISO = 1010 A
and the capture range fC.
Find the output voltage vo corresponding to the
Solution: input voltage vS = (i) 1 mV, (ii) 10 mV ; (iii) 100 mV
1.2 and (iv) 1 V.
f out
4 R1C1
C T E
12
.
= + +
(4) (10 s 103) (.01 s 106) iC
VCB B VBE
+
= 3 kHz R1 Vj1
+
vs > 0 =0
8 f out + vo
fL = Hz
V
8 s 3 s 103
= = 2 kHz
12 Fig. 11.46 For Problem 5
1/ 2
 (2) (10) 3 Solution:
fC =  !
 ( 2Q )
 ( 3.6) (103) (5) (106) !"
vs
= 106 Hz v o = VT ln (11.50)
I so R1
fout, fL and fC are illustrated in Fig. 11.44.
vs
+6 V = (26 103) ln
C2 1010 s 5 s 103
+

103
R1 5 mF
10 k C3 0.001 (i) vo = (26 103) ln 10
= 0.197 V
10 s 5 s 103
10 0.001 mF

103
2 Demad
(ii) vo = (26 103) ln
Input 7 o/p
10
= 0.2575 V
LM 565 6
Ref o/p 10 s 5 s 103
4
3
VCO
(iii) vo = (26 103) ln 102 = 0.3174 V
output 10
9 1
5 10 s 5 s 103

1
(iv) vo = (26 103) ln
C1 0.01 mF
= 0.377 V
6 V
1010 s 5 s 103
Thus, the output voltage is a compressed version
Fig. 11.44 For Problem 4
of the wide input voltage.
 Supplementary Problems 29

Problem 6. If you have at your disposal a Problem 8. Show that the op-amp circuit of Fig. 11.49
logarithmic amplifier and an exponential amplifier, uses the analog multiplier to perform division.
devise a circuit that will produce the quotient of two
Solution:
members.
Since i S = iP and vd = 0
Solution: x/y = eIn xIn y. Thus, if the divisor and the vs v  vovss
dividend are each fed to a logarithmic amplifier, the = P =
vR vR R
two resulting signals are fed to a difference amplifier,
and the difference is fed to an exponential amplifier, vs
vo = (11.52)
the result is identical to division. This is shown in vss
Fig. 11.47.

Logarithmic amplifier

V1 k(ln V1) R R

V1
V2
C(ln V1 ln V2)

+
V2 k(ln V2)
Exponential amplifier
R
R1
Logarithmic amplifier

Fig. 11.47 For Problem 6

Problem 7. The analog multiplier of Fig. 11.48 has This is shown in Fig. 11.49
the characteristic vP = v1 v2. Determine the output vo
vSS
for the op-amp circuit.
Solution: iP R vP
Since i S = iP and vd = 0 X
iS R
vs vp  v1v2 v2
= = = 0 vs
R R R R + vo

\ vo =  vs (11.51)
This is shown in Fig. 11.77
Fig. 11.49 For Problem 8
R vP
X
iP v2
iS R v1

+
+ +
vs
vo

Fig. 11.48 For Problem 7

 30 Linear Integrated Circuits

CHAPTER 13 Solution:
R = 1
Problem 1. For the Wien bridge oscillator circuit 2 Q f 0C
of Fig. 13.51, determine (a) the oscillation frequency, The largest value of f0 requires the smallest value
and (b) the value of Rf required. of R and the smallest value of f0 requires the largest
R = 15 kW, C = 0.02 mF, and Ri = 10 kW value of R.
Solution: 1
Rmin = = 15.915 kW
1 1 2Q (1 kHz) ( 0.01 NF)
(a) f0 = = Hz
2Q RC 2Q (15 k8) ( 0.02 NF) 1
Rmax = = 159.15 kW
= 530.5 Hz 2Q (100 Hz) (0.01 NF)
(b) To sachieve a gain of 3, the value of Rf must Thus, the resistances must be adjustable from
be 15.915 kW to 159.15 kW in order to tune the oscillator
R f = 2Ri = 2(10 kW) = 20 kW over the required range. It is assumed that the
resistances are aligned so that their values are equal.
10 kW Rf
Problem 3. Design a phase-shift oscillator to
produce oscillations at 1 kHz. The capacitor values

vo
are selected as C = 0.01 mF.
+
15 kW Rf
0.02 mF
0.01 mF 0.01 mF 0.01 mF 12 kW

15 kW 0.02 mF vo
+
R R
Rc
Fig. 13.51 For Problem 2

Problem 2. A variable Wien bridge oscillator of a Fig. 13.53 For Problem 4

form similar to that of Fig. 13.52 is to be designed to
produce an output sinusoid that can be adjusted from Solution:
100 Hz to 1 kHz. The two capacitor values are
R = 1 = 1 = 6497 W
selected as C = 0.0 mF. Determine the required range
2 Q 6 f 0C 2Q 6 (1 kHz) (0.01 NF)
in the resistances.
The value of R f is then determined as
R R2 R f = 29R = 29 6497 = 188.4 kW
C + None of the resistance values are standard so
some adjustments will be required.
Problem 4. What is the frequency of the output
signal in Fig. 13.54?

C R Solution: The feedback fraction is

C R1
18 k8
b= = 0.9
20 k8
Fig. 13.52 For Problem 3
 Supplementary Problems 31

1 kW = 0.693(1 kW + 3 kW)(0.02 mF)

= 55.44 ms
+15 V
(b) The low-state time interval is
2
7
6 TL = 0.693 RB C = 0.693 (3 kW)(0.02 mF)
vout
= 41.58 ms
3 318
0.1 mF + 4
(c) The period is
15 V
T = TH + TL = 55.44 mS + 41.58 ms
2 kW = 97.02 ms
18 kW
(d) The frequency is
1 1
f= = = 10.31 kHz
Fig. 13.54 For Problem 5 T 97.02 s 10 6
(e) The duty cycle is
1 C
T = 2RC ln = 2 (1 kW)(0.1 mF) TH 54.44 Ns
1 C D = 100% = 100% = 57.14%
T 97.02 Ns
1  0.9
ln = 589 ms Problem 6. In a Wien bridge oscillator C1 = C2 =
1  0.9
C. The minimum and maximum values of C1 are 90 pF
The frequency is
and 900 pF respectively. R1 = R2 = R = 100 kW.
f= 1 = 1.7 kHz
589 Ns (a) Determine the range of the operating
frequency of the oscillator.
Problem 5. Consider the 555 astable circuit of (b) Determine the value of R3, if R4 = 10 kW, so
Fig. 13.55. Determine (a) high state time interval, that oscillations can be maintained.
(b) low-state time interval (c) period (d) frequency,
Solution:
and (e) duty cycle.
R A = 1 kW, RB = 3 kW, and C = 0.02 mF (a) f0 = 1
2Q RC
Solution:
(a) The high-state time interval is f0(max) = 1
T H = 0.693 (RA + RB)C 2Q RC min
+5 V
1
= = 17.68 kHz
2Q s 100 k8 s 90 s 1012
1 kW RA
8 4 f0(min) = 1
7 2Q RC max

3 kW RB 555 3 Output
= 1 = 1.768 kHz
6
2
2Q 100 k8 s 900 s 1012
1 5
The range of f0 is from 1.768 kHz to 17.68 kHz.
0.02 mF C
R3
0.01 mF (b) 1 , R3 = 2R4 = 2 10 kW = 20 kW
R 3  R4 3
Fig. 13.55 For Problem 6
 32 Linear Integrated Circuits

Wien bridge
f0 = 1
2Q RC 6
R1
R2 = 1
C1 2Q s 200 s 103 100 s 10 12 6
A
= 3.248 kHz
R3
R4
Problem 9. Design a phase-shift oscillator to
oscillate at 100 Hz.
C2
Solution: Let
C = 0.1 mF

f0 = 1
Fig. 13.56 For Problem 6 2Q RC 6

Problem 7. In a Wien bridge oscillator, if the value R = 1

of R is 100 kW, and the frequency of oscillation is 2Q f 0 C 6
10 kHz, find value of capacitor C. 1
= = 6.49 kW
Solution: 2Q (100) (107) 6

f0 = 1 Use R = 6.5 kW
2Q RC To prevent loading of the amplifier by the RC
1 network, R1 10 R
C =
2Q R f 0 \ R 1 = 65 kW
1 Since R f = 29 R1
C =
2Q s 100 k8 s 10 kHz R f = 29 65 kW = 1885 kW
= 159 pF Problem 10. For the 555 monostable circuit of
Problem 8. In an RC phase-shift oscillator if R1 = Fig. 13.60, determine the pulse width.
R2 = R3 = R = 20 kW, and C1 = C2 = C3 = 100 pF, find +5 V
the frequency of the oscillator.
Solution:
2 kW
Amplifier Input 8 4 R 15 kW
Rf 2 7
1885 kW 0.01 mF
R1

65 kW vo C 0.22 mF
+ 5 6
3
Rcomp
0.01 mF
Output
0.1 0.1 0.1
C C C
vf R R R Fig. 13.60 For Problem 12
6.5 kW 6.5 kW 6.5 kW Feedback
network
Solution: In the given circuit
Fig. 13.57 RC phase-shift oscillator R = 15 kW and C = 0.22 mF
 Supplementary Problems 33

+VCC +5.5 V

Ri
Ci 8 4
R
R1
2 7
Trigger 2.2 kW RESET VCC
input 555 vC(t)
DISCH
R2
6 555
5 4.7 kW
1 3 THRESH OUT
0.01 mF C
TRIG CONT

Output
Cext GND C1
vo(t)
0.022 mF 0.01 mF

Fig. 13.61 For Problem 13

T P = 1.1RC Fig. 13.63 For Problem 15

= 1.1(15 103) (0.22 106)
= 0.003635
Solution:
= 3.63 ms
fr = 1.44
Problem 11. Design a monostable 555 timer circuit ( R1  2 R2) Cext
of the form shown in Fig. 13.61 to produce an output
pulse 1ms wide. = 144
.
(2.2 k8  9.4 k8 ( 0.022 NF)
Solution:
= 5.64 kHz
T P = 1ms = 1.1RC
RC = 9.1 104  R1  R2 
Duty cycle =   100%
 R1  2 R2 
There are many choices of R and C that would
satisfy the constraint. In the range of reasonable
 2.2 k8  4.7 k8 
choices select: =  100% = 59.5%
C = 0.01 mF, R = 91 kW
If the trigger circuit shown on the left-hand side
of Fig. 13.61 is used, the values of Ci and Ri should
selected. These values are not critical, but the product
R iC i should typically be much smaller than T P .
Reasonable choices might be
C i = 0.001 mF and Ri = 10 kW.
Problem 12. A 555 timer configured to run in the
astable mode is shown in Fig. 13.64. Determine the
frequency of the output and the duty cycle.
k8  9.4 k8 

 2.2
Problem 13. Give the pin configuration of CD 4046
phase-locked loop IC. Explain briefly.
Solution: The tendency to lose lock is a major
weakness of the exclusive OR type phase detector.
Within the CD 4046 is a second phase detector. It
shares the input and feedback signals with the f1
(exclusive OR) detector, but has its own fII, output
(Pin 13). It consists of digital logic with flip-flops for
memory and a three-state output driver.
 34 Linear Integrated Circuits
CHAPTER 14
Problem 1. Illustrate the frequency response of a
(a) practical low-pass filter (b) practical high-pass
filter.
Solution: See Fig. 14.58
Gain
Pass band Stop band
3 dB
f3 dB
Gain
Stop band Pass band
f3 dB
Fig. 14.58 Frequency response (a) low-pass
filter and (b) high-pass filter
Problem 2. A low-pass filter is desired for a given
application. The specifications are as follows:
(1) Relative attenuation 3 dB for f 800 Hz
(2) Relative attenuation 23 dB for f 2 kHz
Specify the minimum number of poles for a
Butterworth filter that will satisfy the requirements.
Solution: Requirement (1) specifies passband in
which the response drops no more than 3 dB.
Requirement (2) specifics a stopband in which the
response is required to be at or below a certain level.
The region between (1) and (2) can be interpreted as a
transition band. The specifications are not very
demanding since a very wide transition band is
provided.
The curves of Fig. 14.59 may be readily used. We
interpret the cut-off frequency to be fc = 800 Hz. The
actual frequency f = 2 kHz corresponds to a normal-
ized frequency f/fc = 2000/800 = 2.5. At an abscissa of
2.5 on the normalized frequency scale, we drop down
to determine the response curves that will achieve
the required attenuation. The response of a two-pole
function is down by only about 16 dB at this fre-
quency, so it is inadequate. However, a three-pole
response is down by about 23 dB, so it more than
meets the specifications. Hence the minimum num-
ber of poles required in the Butterworth filter is three.
Note:
(1) The relative amplitude response curve for any
three-pole Butterworth filter will meet the
f specifications as given for any frequencies having
the same ratios as those given. For example, if the
frequency of specification (1) had been 5 kHz and
the frequency of specification (2) had been
3 dB
12.5 kHz, a three-pole Butterworth filter would
again be the correct solution, since 12.5 kHz/5 kHz
= 2.5 is the same normalized frequency as
determined in the problem.
(2) The utility of the normalized frequency concept is
that the various results apply to any frequency
f combination having the same relative ratios.
Problem 3. A high-pass filter is required for a given
application. The specifications are as follows:
(1) Relative attenuation 3 dB for f 500 Hz
(2) Relative attenuation 46 dB for f 12.5 Hz
Specify the minimum number of poles for a
Butterworth filter that will satisfy the requirements.
Solution: The manner in which the specifications
are given suggests that the 3 dB cut-off frequency
can be established at 500 Hz. For a high-pass filter
the frequency of 125 Hz corresponds to 500 Hz
inverted normalized frequency of fc/f = 500/125 = 4.
At a normalized frequency of 4, the smallest number
of poles satisfying the specification is four. The
attenuation at this point is slightly greater than
48 dB, so the specification is met with reserve.
 Supplementary Problems 35

0
10 1
20 dB/decade
20
23 2
30
3
4
40
40
Gain (dB)

5
50
6 60
60
70
80
80
100
90
120
100
110
120
1 1 2 2.5 3 4 5 6 7 8 910 20 30 40 60 80100
50 70
f/f0

Fig. 14.59 Roll off rate comparison

 36 Linear Integrated Circuits

CHAPTER 15 from 1 to 40 V. The mA 78S40 draws a maximum

quiescent current of 2.5 mA at Vin = 5 V and 3.5 mA, at
Problem 1. Design a voltage regulator using LM723 Vin = 40 V, with typical values being 1.8 mA and
for 5 V, 100 mA power supply. Given Vin = 10 V. 2.3 mA respectively. The regulator is supplied in a 16-
Assume Vsense = 0.65 V. pin DIP that can dissipate 1.5 W in the plastic version
and 1 W in the hermetically sealed version. The device
Solution: The reference voltage V REF must be
is supplied in a commercial version with an operating
reduced to 5 V for the non-inverting input of the
temperature of 0 to 70C and a military version with a
error amplifier by means of a voltage divider.
temperature range of 55 to 125C. The device can
Assume I0 = 1 mA supply up to 1.5 A without external transistors.
VR  Vo 7.15 V  5 V The m A 78S40 consists of a temperature
R1 = =
Io 1 mA compensated voltage reference, a duty-cycle
= 2.15 kW (use 2.2 kW) controllable oscillator with an active current limit
circuit, high-gain comparator, high-current high-
Vo 5V voltage output switch, a power switching diode and
R2 = = = 5 kW (use 5.1 kW)
Io 1 mA an uncommitted op-amp. The block diagram and the
R 3 = R1 || R2 = 2.15 kW || 5 kW = 1.5 kW pin configuration of the IC are given in Fig. 15.50.
Rsense 0.65 V Ipk
= 6.5 W (use 6.8 W)
Noninv. Inv. Timing Driver Switch
R CL = = input input capacitor Vcc sense collector collector
Im 100 mA Gnd.
9 10 11 12 13 14 15 16
PD (max) = Vin (I0 + IQ) = 10 V (100 mA + 3 mA )
= 1.03 W
CT Ipk
Vin Oscillator S Q Q2

+ VC RCL
V Q1
VO
Comp. R
VREF Vo
170
CL
R1 723 1.25 V
CS reference Op D1
NI R3 Amp.
INV +
Cref R2 V Comp.

100 pF 8 7 6 5 4 3 2 1
Ref Inv. Noninv. Vcc Output Switch Diode Diode
C1 output input input Op Amp. emitter anode cathode

Fig. 15.49 for Problem 1

Diode cathode 1 16 Switch collector
Problem 2. Explain in detail the operation of Diode anode 2 15 Driver collector
switching voltage regulator IC-mA 78S40. Switch emitter 3 14 Ipk sense
Op amp output 4 13 Vcc
Solution: m A 78S40 is a universal switching Vcc Op Amp 5 12 Timing capacitor
regulator subsystem. It is a versatile pulse-width 11 Ground
Op Non-inv. 6
modulated switching regulator capable of line and Amp Inv. input 7 10
Comparator
Inv. input
load voltage regulation of 80 dB (0.01%). It has an Reference 8 9 Comparator
input voltage range from 2.5 to 40 V and can control Non-inv. input
(Top view)
output voltage limited by the external components
used. As a step-down or step-up regulator with no Fig. 15.50 mA 78S40 universal switching
external switching transistors, it can supply voltages regulator (a) block diagram, and (b) pin
configuration
 Supplementary Problems 37

The initial switching frequency is set by the timing
capacitor CT, connected between pins 12 and ground
pin 11. The initial duty cycle is 6 : 1. The switching
frequency and duty cycle can be modified by the
current limit circuitry, I pk sense pin 14, and the
comparator pins 9 and 10. The oscillator can be set
between 100 Hz and 100 kHz. Ipk, pin 14, is used to
vary the duty cycle and thus ton in the regulator. The
lower limit of tON or tOFF is 10 ms.
The output transistors can block 40 volts and
supply up to 1.5 A. Q2 is the driver for Q1 Q1 and Q2
can be connected as a darlington pair or Q2 can be

Vin
25 V RSC
100
470 0.33
CT
pF
9 10 11 12 13 14 15 16
VCC

CT Ipk
Oscillator S Q Q4

Q1
Comp. R
170

1.25 V
reference Op D1
Amp.
+

8 7 6 5 4 3 2 1
1N5822
R2 L
Vout
3.6 K 220 mH 5.0 V/500 mA
R1 1.2 K +
470 C0

Fig. 15.51 Step-down voltage regulator with mA 78S40

Line
rectification Transistor
220 V dc filtering an switching Load
isolation or array
battery

Transistor
drive

Reference Pulse width Negative feedback

voltage modulator

Fig. 15.52 Generalized block diagram of a buck converter

 38 Linear Integrated Circuits

Table 15.1 Datasheet of m A78S40 (Fairchild Semiconductors)

Calculation Step-Down Step-Up Inverting

ton Vout  VF Vout  VF Vin(min) Vout  VF

toff Vin(min)  Vsat  Vout Vin(min)  Vsat Vin(min)  Vsat

(ton + toff)max
1 1 1
tmin tmin tmin
CT 45 105 tON 45 105 tON 45 105 tON
t t  t t 
Ipk(switch) 2Iout(max) 2I out(max)  on off  2I out  on off 
 toff   toff 

0.33 0.33 0.33

RSC
I pk(switch) I pk (switch) I pk (switch)

 Vin(min)  Vsat   Vin(min)  Vsat 

L (V0 + V d)/I pk toff  I  t on(max)  I  t on(max)
 pk (switch)   pk (switch) 

I pk (switch) ( ton  toff ) I out ton I out ton

CO = =
8Vripple( pp ) Vripple Vripple

used with an external resistor to provide increased Vload

0V
base drive to Q1 as is necessary in the step-up supply.
I +
QCE (sat), of Q1 is 1.1 V typically and 1.3 V maximum On +

at IC = 1 A. The b of Q1 is 70 with IC = 1 A and VCE = Ein
+ +
5 V, so for VCE = 1 V at IC = 1 A, a value of b (Q1) = 20 PWM Off Load

may be used for calculations.
The AND gate output is connected to the flip-flop
input to turn Q1 off when V0 > VR. It is part of the (a) Charge cycle

regulator circuitry. The diode will block 40 V and drop Vload

1.5 V in the forward bias case with forward current IF 0V

= 1 A. The typical VD is 1.25 V at 1 A. The reference Off

+

voltage is temperature compensated and is equal to

+ +
1.25 V typically. PWM On Load

The comparator is a high-gain amplifier used as
an error amplifier for regulation. The uncommitted
op-amp is used in inverting configuration or used (b) Discharge cycle
as a driver for an auxiliary series-pass regulator.
Fig. 15.53 (a) Charge, and (b) discharge
Problem 3. Draw the generalized block diagram cycles of a buck converter
of a buck converter and illustrate the charge and 12 V dc ; Output voltage = 5 V ; Output current
discharge cycles. maximum 0.5 A. Maximum output ripple is 2%.
Solution: See Figs 15.51 through 15.53. Solution: From Table 15.1 for step-down mode: The
Problem 4. How will you read the data sheet voltage drop across the diode VD = 1.25 V.
(Table 15.1) of mA 78S40? Design a step-down voltage The output saturation voltage ; VS = 1.1 V, VREF =
regulator using mA 78S40 given that Input voltage = 1.245 V; IBias (comparator) = 35 mA and ID (divider
current) through R1 R2 = 0.1 mA.
 Supplementary Problems 39

Ipeak = 2 Iout(max) = 2 0.5 103 = 1 A I pk ( Ton  Toff ) 50 s 106

C0 = = = 125 mF
0.33 0.33 8 Vripple 8 Vripple
Short-circuit resistance, RSC = = =
I peak 1 Next, calculate the values of resistors used in the
0.33 W sampling network. The non inverting terminal is
Vo  VD 5  125
. connected to the reference voltage. Therefore,
Ton
= = = 1.06 1245
.
Toff Vin  Vout  VS 12  11
.  0.5 R2 = = 12.45 kW
The switching regulator has maximum efficiency . s 103
01
when operating at 20 kHz R2 1245
. s 103
V R2 = Vout; 1.2 =
TD =
1
= 50 ms R1  R2 R1  (12.45 s 103 )
20 s 103 R 1 = 36 kW
Ton + Toff , but Ton = 1.06 Toff The efficiency of the switching is given by
Toff = 24.2 ms and Ton = 25.8 ms
Vin  Vs  Vo Vout
C T = (45 103) Toff h = s
Vin Vin  Vout
= (45 105) (24.2 106) = 0.0109 mF
12  11
.  125
.
The load inductor, h % = s 5 100 = 81%
12 5  125
.
Vout  VD 5  1.25
L = Toff = 24.2 106
I peak 1 Problem 5. Illustrate the use of the CA723CT IC
= 151.25 mH as switching regulator:
The value of output capacitor, Solution: See Fig. 15.54

VIN = 25 V 20%

R9
3.3 k
Q1
R1 BEL 6109
R10 4 L = 4 mH
5.6 k 8
2.2 MW 7
3 +
R2
CA 723CT 6 D
4.7 k R5
2 2N 1482
10 10 W
1 R8
9
5 0.6 W, 1W

R6
Q2 0.75 W R7
BC 148 0.6 W
Vo
C2 C3 5 V, 1 A
22 KPF C4 250 mF R3
330 PF C1 12 V 1.8 k
47 KPF
100 W

R4
3.3 k

Fig. 15.54 Circuit of a switching regulator using CA723CT

 40 Linear Integrated Circuits
CHAPTER 16
Problem 1. Discuss the need for an isolation
transformer. How does it operate?
Solution: Isolation transformers provide dc iso-
lation between input and output for the protection
of human life of sensitive equipment in those appli-
cations where hazardous power-line leakage or
high-voltage transients are possible. The principal
areas of applications for isolation amplifiers are in
medical instrumentation, power plant instrumenta-
tion, industrial processing and automated testing.
In some ways, the isolation amplifier can be viewed
as an elaborate op-amp instrumentation amplifier.
The difference is that an isolation amplifier has an
input stage, an output stage and a power-supply
section that are all electrically isolated from each
other. The transformer-coupled device is the one most
commonly used. The circuit is in IC form, but the
miniature multiple-winding, toroid transformer is not
fully integrated.
As shown in Fig. 16.37, there are three isolated
independent grounds for the input signal ( ),
the output signal ( ) and the power supply (
An external dc supply voltage, VDC is applied to
the oscillator. The oscillator converts the dc power
to ac at a relatively high frequency. The ac output of
the oscillator is coupled by the transformer to the
input power supply (rectifiers and filters) and to the
output power supply (rectifiers and filters) where it
Input stage
Input
demodulator
A1 Modulator
+ +
Input
Rectifiers
Vin and filters
Power
Fig. 16.37 A transformer coupled isolation amplifier
is rectified and filtered to produce dual-polarity dc
voltages (+ ve and ve) for the input and output
stages.
The oscillator output is also coupled to the
modulator where it is combined with the input signal
from the input op-amp A1. The modulator varies the
amplitude of the relatively high oscillator frequency
with the lower-frequency input signal. To couple the
lower-frequency input signal without modulation
would require a prohibitively large transformer.
The modulated signal is coupled to the
demodulator in the output stage. The demodulator
recovers the original input signal from the higher
oscillator frequency. The demodulated input signal
is then applied to output op-amp, A2, which is part of
a feedback loop that forces the signal at the inverting
input of A1 to equal the original input signal at the
non-inverting input.
The isolation function is an unseen process. You
apply a dc voltage, put a signal in and you get an
amplified signal out. A representative device is the
BurrBrown 3656KG. It has a few more input and
output pins to provide for gain adjustments, offset
adjustments, isolated dc voltage outputs, and other
). functions.
Problem 2. Explain the operation of an ECG system
with the help of a block diagram.
Solution: The human heart produces an electrical
signal that can be picked up by electrodes in contact
with the skin. When the heart signal is displayed on
a chart recorder, or on a video monitor, it is called
Output stage
+
Oscillator VDC
Output
A2 Output
demodulator
Output
Rectifiers
and filters
Power
 Supplementary Problems 41

an electrocardiograph (ECG). Typically, the heart Solution: The voltage gain of the input stage is
signal picked up by the electrode is about 1 mV and RF1 22 k8
has significant frequency components, from less than A v1 = +1= + 1 = 10 + 1 = 11
Ri1 2.2 k8
1 Hz to about 100 Hz.
As indicated in the block diagram in Fig. 16.38, an The voltage gain of the output stage is
ECG system has at least three electrodesa right- RF2 47 k8
A v2 = +1= +1
arm electrode (RA), a left-arm electrode (LA), and a R i2 10 k8
right-leg electrode (RL) that is the common terminal.
= 4.7 + 1 = 5.7
The isolation amplifier provides for differential
inputs from the electrodes, provides a high CMR to The total voltage gain of the isolation amplifier is
eliminate the relatively high common-mode noise Av (tot) = Av1 Av2 = (11) (5.7)
voltages associated with heart signals and provides = 62.7
electrical isolation for protection of the patient. The
low-pass filter rejects frequencies above those Note: The triangle with a split down the middle is one way
contained in the heart signal. The post-amplifier of representing an isolation amplifier by indicating that the
input voltages are separated by transformer coupling.

Power supply

Video monitor
RA
Isolation Low-pass
LA Postamplifier
amplifier filter
RL
Electrodes Amplifier circuit board
Chart recorder

Fig. 16.38 Block diagram of an ECG system

provides most of the amplification in the system and

drives a video and/or a chart recorder. 10 kW Ri2
Vin 7 10 kW
The inputs from electrode sensors are connected Rf1 Rf2
to the amplifiers through a shielded cable to prevent 10
22 kW 47 kW
noise pick-up. The input differential signal is amplified 6 14
by the fixed gain of the 3656KG isolation amplifier. Ri1 Input Output 15 Vout
The low-pass filter is an active filter. The post- 2.2 kW
16
amplifier is an inverting amplifier with an adjustable 19
12
0.47 mF
voltage gain. The inverting input also serves as a 20
0.47
summing point for the signal voltage. A dc voltage is mF
used for adding an adjustable dc level to the output 0.47
for adjusting the vertical position of the display. mF

Problem 3. Determine the total voltage gain of the +15 V

3656 KG isolation amplifier in Fig. 16.39. Fig. 16.39 For Problem 3

 42 Linear Integrated Circuits

Problem 4. Calculate the differential voltage gain () +

R4 R6
of the instrumentation amplifier in Fig. 16.40 with A1
the following resistance values.
R2
Solution: R3 = 33 kW, R1 = 2.2 kW, R5 = 3.3 kW and
R7 = 15 kW.

Input
R1
Gain R3 A3
E0
 2 R 3   R 7 +
Av =   1 !  
 R 1  "  R 5
R5
 (2 ) (33 k 8)  (15 k8) A2
=  (2.2 k )
 8  1!"  (3.3 k8) !" (+) +
R7

= 141 LM 2 R3 + 1OP LM R6 OP CMR

AV =
N R1 Q N R4 Q ADJ

Provided that: R2 = R3
R4 = R5
R6 = R7

Fig. 16.40 For Example 4instrumentation

amplifier