Professional Documents
Culture Documents
QUESTIONBANK
UNIT I
CMOS TECHNOLOGY
A brief History-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non ideal IV
effects, DC transfer characteristics - CMOS technologies, Layout design Rules, CMOS process
enhancements, Technology related CAD issues, Manufacturing issues
PART-A (1 Mark)
1. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmer
interconnect that is used to connect internal logic modules is called a ________.
A.bed-of-nails B.boundary scan C.CLB D.CPLD
2. The ________ is the most popular standard logic device family today.
A.TTL B.CMOS C.ECLD .None of the above
3. Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions.
A.AND array B.Look-up table C.OR array D.AND and OR array
4. A macrocell is ________.
A.part of a PAL or GAL B.a type of one-time programmable SPLD
C.an example of intellectual property D.a logic array block
5. The final step in a design flow in which the logic design is implemented in the target device is called
________.
A.design entry B.simulation C.downloading D.compiling
6. Using a hardware solution for a digital system is always ________ than a software solution.
A.slower B.harder C.easier D.faster
7. The programming technologies that are used in FPGA devices include SRAM, flash, and antifuse, with
________ being the most common.
A.SRAM B.flash C.antifuse D.SRAM and flash
8. Full custom ICs can operate at ________ and require the ________.
A.lowest speed, largest die area B.lowest speed, smallest die area
C.highest speed, largest die area D.highest speed, smallest die area
9. complex programmable logic device that consists of multiple SPLD arrays with programmable
interconnections is called a ________.
Answers:
1 2 3 4 5 6 7 8 9 10
c b b a c d a d d d
11 12 13 14 15 16 17 18 19
c d a b a d b b d
PART-B (2 MARKS)
37. Derive the CMOS inverter DC characteristics and obtain the relationship for output voltage at
different region in the transfer characteristics. [ Nov-2004]
38. Explain with neat diagrams the various CMOS fabrication technology [APRIL-2009]
39. Explain the operation of PMOS Enhancement transistor [APRIL-2008]
40. Explain the threshold voltage equation [Nov-2006]
41. Explain the silicon semiconductor fabrication process. [APRIL-2006]
42. Derive and explain the. [APRIL-2007]
(i) Threshold voltage equation, (ii) MOS DC equation.
Delay estimation, Logical effort and Transistor sizing, Power dissipation, Interconnect, Design
margin, Reliability, Scaling- SPICE tutorial, Device models, Device characterization, Circuit
characterization, Interconnect simulation
PART-A (1 MARK)
43. Propagation delay is important because ________.
A. the logic gates must be given a short break during each clock cycle or else they will overheat
B. it limits the maximum operating frequency of a gate
C. it is a measure of how long the clock must be applied to the gate before it will make the required decision
D. all the gates in a system must have the same propagation times in order to be compatible
44. The output current for a LOW output is called a(n) ________.
A.sink current B.ground current C.exit current D.fan-out
45. The proliferation of small handheld consumer equipment such as digital video cameras, cellular
phones, handheld computers (________), portable audio systems, and other devices has created a need for
logic circuits in very small packages.
A. HDLs B. GDAs C. PDAs D. TTLs
46.The lower transistor of a totem-pole output is saturated when the gate output is ________.
A. overdriven B. HIGH C. LOW D. malfunctioning
47.The time it takes for an input signal to pass through internal circuitry and generate the appropriate
output effect is known as ________.
A. fan-out B. propagation delay C. rise time D. fall time
48.________ is about twice as fast as P-MOS.
A. CMOS B. DMOS C. MOD D. N-MOS
49.P-MOS and N-MOS ________.
A.represent MOSFET devices utilizing either P-channel or N-channel devices exclusively within a given gate
B.are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC
C.represent positive and negative MOS-type devices that can be operated from differential power supplies and are
compatible with operational amplifiers
D.None of the above are.
50.________ is ideally suited for applications using battery power or battery backup power.
A. MOS B. P-MOS C. N-MOS D. CMOS
51.A logic probe is placed on the input of a digital circuit and the probe lamp blinks slowly, indicating
________.
A. that an open or bad logic level exists B. a high level output
C. a high-frequency pulse train D. that the supply voltage is low
52.The HIGH logic level for a standard TTL output must be at least ________.
A. 2.4 V B. 2V C. 0.8 V D. 5 V
53. The term "hex inverter" refers to:
A. an inverter that has six inputs B. six inverters in a single package
C. a six-input symbolic logic device D. an inverter that has a history of failure
54. The basic logic gate whose output is the complement of the input is the:
A. OR gate B. AND gate C. inverter D. comparator
Answers:
49 50 51 52 53 54 55 56 57 58
a a c c a b d a d b
59 60 61 62 63 64 65 66 67 68
c c c d b b b a b d
90. Explain the Transmission gate and the tristate inverter briefly. [Nov-2005]
92. Explain about the various non ideal conditions in MOS device model. [APRIL-2008]
93. Explain with neat diagrams the Multiplexer and latches using transmission Gate.
94. Explain that how the MOS transistor is to be analysed by the small scale models.
95. Explain the complimentary CMOS inverter DC characteristics.[Nov-2004]
96. Write short notes on [APRIL-2009]
(i) Noise Margin, (ii) Rise Time, (iii) Fall Time.
Circuit families Low power logic design comparison of circuit families Sequencing static
circuits, circuit design of latches and flip flops, Static sequencing element methodology-
sequencing dynamic circuits synchronizers.
PART-A (1Mark)
97. What is meant by the rise time of a waveform?
a) The time taken for the waveform to increase from 10% to 90% of the height of a step.
b) The time taken for the waveform to increase from 0% to 90% of the height of a step.
c) The time delay from when the input step changes by 50% to when the output step changes by 50%.
d) The time taken for the waveform to decrease from 90% to 10% of the height of a step.
98. What is the cause of storage time in a bipolar transistor?
a) The inertia of the minority charge carriers.
b) The time taken to remove excess charge stored in the base region as a result of saturation.
c) The inertia of the majority charge carriers.
d) The 'memory effect' of the device.
99.What is meant by the fan-out of a logic gate?
a) The physical distance between the output pins on the device.
b) The number of other gates that can be connected to one of the gate's inputs.
c) The number of other gates that can be connected to the gate's output.
d) The amount of cooling required by the gate.
100.Which of the following statements is incorrect?
a) CMOS circuitry is more difficult to fabricate than NMOS or PMOS as it required devices of both polarities.
b) CMOS gates have very good noise immunity that is typically 10% of the supply voltage.
c) When a CMOS gate is static it has negligible power consumption.
d) CMOS gates have logic levels close to the supply rails.
101.Which of the following statements is incorrect?
a) TTL logic normally operates from a single 5 V supply.
b) TTL devices have logic levels of about 3.4 V and 0.2 V.
c) Standard TTL devices have a propagation delay that is dominated by the storage time of the bipolar transistors
used.
d) TTL logic has very low power consumption and is therefore widely used in highly integrated components.
102. Which of the following statements is incorrect?
a) ECL is widely used in high-speed applications.
b) ECL suffers from low noise immunity.
c) ECL is one of the fastest forms of electronic logic.
d) ECL has high power consumption.
103. What should be done with an unused TTL input that is required to be at logical 1?
a) It should be connected directly to the zero volt supply rail.
b) It should be connected directly to the positive supply rail.
c) It should be tied to the positive supply rail through an appropriate resistor.
d) It should be left disconnected.
PART-B (2 MARKS)
149. Derive the CMOS inverter DC characteristics and obtain the relationship for output voltage at
different region in the transfer characteristics.[ Nov-2004]
150. Explain with neat diagrams the various CMOS fabrication technology [APRIL-2009]
151. Explain the operation of PMOS Enhancement transistor [APRIL-2008]
152. Explain the threshold voltage equation [Nov-2006]
153. Explain the silicon semiconductor fabrication process. [APRIL-2006]
154. Derive and explain the. [APRIL-2007]
(i) Threshold voltage equation,
(ii) MOS DC equation.
UNIT IV
CMOS TESTING
Need for testing- Testers, Text fixtures and test programs- Logic verification- Silicon debug
principles- Manufacturing test Design for testability Boundary scan
PART-A (1 MARK)
155. How many data select lines are required for selecting eight inputs?
A.1 B.2 C.3 D.4
156. The implementation of simplified sum-of-products expressions may be easily implemented into actual
logic circuits using all universal ________ gates with little or no increase in circuit complexity. (Select the
response for the blank space that will BEST make the statement true.)
A.AND/OR B.NAND C.NOR D.OR/AND
157.As a technician you are confronted with a TTL circuit board containing dozens of IC chips. You have
taken several readings at numerous IC chips, but the readings are inconclusive because of their erratic
nature. Of the possible faults listed, select the one that most probably is causing the problem.
A.A defective IC chip that is drawing excessive current from the power supply
B.A solar bridge between the inputs on the first IC chip on the board
C.An open input on the first IC chip on the board
D.A defective output IC chip that has an internal open to Vcc
Answers:
171. Mention the levels at which testing of a chip can be done? [APRIL-2009]
a) At the wafer level, b) At the packaged-chip level c) At the board level
d) At the system level, e) In the field
172. What are the categories of testing? [Nov-2004]
a) Functionality tests b) Manufacturing tests
173. Write notes on functionality tests? [APRIL-2009]
Functionality tests verify that the chip performs its intended function. These tests assert that all the gates in the
chip, acting in concert, achieve a desired function. These tests are usually used early in the design cycle to verify
the functionality of the circuit.
174. Write notes on manufacturing tests [APRIL-2009]
Manufacturing tests verify that every gate and register in the chip functions correctly. These tests are used after
the chip is manufactured to verify that the silicon is intact.
175. Mention the defects that occur in a chip? [Nov-2004]
a) layer-to-layer shorts b) discontinous wires c) thin-oxide shorts to substrate or well
176. Give some circuit maladies to overcome the defects?
i)nodes shorted to power or ground ii)nodes shorted to each other iii)inputs floating/outputs disconnected
177. What are the tests for I/O integrity? [APRIL-2009]
i). I/O level test ii). Speed test iii). IDD test
178. What is meant by fault models?
Fault model is a model for how faults occur and their impact on circuits.
179. Give some examples of fault models?
i). Stuck-At Faults ii). Short-Circuit and Open-Circuit Faults
180. What is stuck at fault?
With this model, a faulty gate input is modeled as a stuck at zero or stuck at one. These faults most frequently
occur due to thin-oxide shorts or metal-to-metal shorts.
181. What is meant by observability? [APRIL-2009]
The observability of a particular internal circuit node is the degree to which one can observe that node at the
outputs of an integrated circuit.
182. What is meant by controllability?
The controllability of an internal circuit node within a chip is a measure of the ease of setting the node to a 1 or 0
state.
183. What is known as percentage-fault coverage?[APRIL-2009]
The total number of nodes that, when set to 1 or 0, do result in the detection of the fault, divided by the total
number of nodes in the circuit, is called the percentage-fault coverage.
184. What is fault grading?[ Nov-2004]
Fault grading consists of two steps. First, the node to be faulted is selected. A simulation is run with no faults
inserted, and the results of this simulation are saved. Each node or line to be faulted is set to 0 and then 1 and the
test vector set is applied. If and when a discrepancy is detected between the faulted circuit response and the good
circuit response, the fault is said to be detected and the simulation is stopped.
185. Mention the ideas to increase the speed of fault simulation?
a. parallel simulation b. concurrent simulation
186. What is fault sampling?
An approach to fault analysis is known as fault sampling. This is used in circuits where it is impossible to fault
every node in the circuit. Nodes are randomly selected and faulted. The resulting fault detection rate may be
UNIT V
SPECIFICATION USING VERILOG HDL
Basic concepts- identifiers- gate primitives, gate delays, operators, timing controls, procedural
assignments conditional statements, Data flow and RTL, structural gate level switch level
modeling, Design hierarchies, Behavioral and RTL modeling, Test benches, Structural gate
level description of decoder, equality detector, comparator, priority encoder, half adder, full
adder, Ripple carry adder, D latch and D flip flop.
PART-A (1MARKS)
205. After the final routing the violations in the design ___.
a. There can be no setup, no hold violations
b. There can be only setup violation but no hold
c. There can be only hold violation not Setup violation
d. There can be both violations.
206Utilisation of the chip after placement optimisation will be ___.
a. Constant b. Decrease c. Increase . None of the above
207. What is routing congestion in the design?
a. Ratio of required routing tracks to available routing tracks
b. Ratio of available routing tracks to required routing tracks
c. Depends on the routing layers available
d. None of the above
208. What are preroutes in your design?
a. Power routing b. Signal routing c. Power and Signal routing d. None of the above.
209. Clock tree doesn't contain following cell ___.
a. Clock buffer b. Clock Inverter c. AOI cell d. None of the above
210.In VHDL,V tnds for
A.Verilog B.VLSI C. VHSI D.Very Efficient
211.In VHDL always the ------------------- file should be included
a. Library B. Header C. assembly D.target
212.Todeclare the inputs and outputs of the circuit --------------------- statement is used
A.Architecture B.Component C.Process D.entity
213.IN bit is used to declare
A. 1 bit output B.1 bit input C. 2 bit output D. 2 bit input
214.For dont cases -------------symbol is used
A.1 B.0 C.X D.U
Answers:
205 206 207 208 209 210 211 212 213 214
d c a a c c a d b c
215 216 217 218 219 220 221 222 223 224
a c c d b b c d b c
PART-B (2 MARKS)
240. Explain the concept of gate delay in VERILOG with example [APRIL-2009]
241. Explain the concept involved in structural gate level modeling and also give the
description for Half adder and Full adder.