Multiplexers

Decoders
ROMs (LUTs)

ECEn 224 09 MUX © 2003-2008

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 A Problem Statement

Design a circuit which will

select
between two inputs (A and B) and
pass
the selected one to the output (Q).

The desired circuit is called a multiplexer or MUX for short

ECEn 224 09 MUX © 2003-2008

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 Multiplexer Symbols

Preferred symbol

A 0
A 0
Q Q
B 1 B 1

S
S

“Select” input

ECEn 224 09 MUX © 2003-2008

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 Data Steering

A 0 A 0 A 0
Q Q Q
B 1 B 1 B 1

S 0 1

Key idea: The select input wire selects one of the

inputs and passes it out to the output.

This is called a 2:1 MUX (pronounced “two-to-one”)

ECEn 224 09 MUX © 2003-2008

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 Multiplexers

S A B Q
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

ECEn 224 09 MUX © 2003-2008

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 Multiplexers

S A B Q AB

0 0 0 0 S 00 01 11 10
0 0 1 0 0
0 1 0 1 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

ECEn 224 09 MUX © 2003-2008

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 Multiplexers

S A B Q AB

0 0 0 0 S 00 01 11 10
0 0 1 0 0 1 1
0 1 0 1 1 1 1
0 1 1 1
1 0 0 0 Q = S’A + SB
1 0 1 1
1 1 0 0 A
1 1 1 1 S
Q

ECEn 224 09 MUX © 2003-2008

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 Multiplexers

{
I0
Data I1 4:1 Z
Inputs I2 MUX

I3

AB

{
Control Inputs

Z = A’B’I0 + A’BI1 + AB’I2 + ABI3

ECEn 224 09 MUX © 2003-2008

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 8 to 1 Multiplexer
I0
I1
I2
Data I3 8:1
Inputs MUX Z
I4
I5
I6
I7

ABC

Control Inputs

Z = A’B’C’I0 + A’B’CI1 + A’BC’I2 + …

ECEn 224 09 MUX © 2003-2008

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 A General MUX

I0
N Data I1 N:1 Z Output
Inputs … MUX
IN-1

…
sk-1…..s0

log2(N) Control Inputs

ECEn 224 09 MUX © 2003-2008

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 A 3:1 MUX?

I0
Q = A’B’I0 + A’BI1 + AB’I2 I1
3:1 Q
MUX
I2

AB

• What happens when AB = 11?

• Often we just use a 4:1 MUX and leave I3 unconnected.

ECEn 224 09 MUX © 2003-2008

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 Multiplexers In A Microprocessor

• Each signal here is a 16-bit wide bus

– A 16-bit wide MUX is simply
16 1-bit wide MUXes all with
common select inputs

ECEn 224 09 MUX © 2003-2008

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 16-bit 3:1 MUX Example

BusA

00
bit 0 01 bit 0
10

11

BusB
Select control
lines
bit 0

BusC

bit 0

ECEn 224 09 MUX © 2003-2008

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 16-bit 3:1 MUX Example

BusA

00

bit 1 01 bit 1
10

11

BusB
Select control
lines
bit 1

BusC

bit 1

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 16-bit 3:1 MUX Example

BusA 00 00 00 00
Output

bit 15
BusB

bit 2
bit 0

01 01 bit 1 01 01
BusC 10 10 10 … 10

11 11 11 11

s1
s0

They all use the same select control lines…

One bit from each bus goes to each MUX
The result is a 16-bit bus

ECEn 224 09 MUX © 2003-2008

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Implementing Logic with MUX Blocks

ECEn 224 09 MUX © 2003-2008

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 Example 1
Using A as the select input …

A B C F
0 0 0 0
0 0 1 0 A=0 part of the truth table
0 1 0 0 … when A=0, F=0 0 0
F
0 1 1 0 B+C 1
1 0 0 0
1 0 1 1 A=1 part of the truth table
1 1 0 1 … when A=1, F=B+C A
1 1 1 1

ECEn 224 09 MUX © 2003-2008

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 Example 2
Using B as the select input …

B A C F
0 0 0 0
0 0 1 0 B=0 part of the truth table
0 1 0 0 … when B=0, F=AC AC 0

0 1 1 1 F
A 1
1 0 0 0
1 0 1 0 B=1 part of the truth table
1 1 0 1 … when B=1, F=A B
1 1 1 1

ECEn 224 09 MUX © 2003-2008

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 Example 3
Using C as the select input …

C A B F
0 0 0 0
0 0 1 0 C=0 part of the truth table
0 1 0 0 … when C=0, F=AB AB 0

0 1 1 1 F
A 1
1 0 0 0
1 0 1 0 C=1 part of the truth table
1 1 0 1 … when C=1, F=A C
1 1 1 1

All 3 of these examples are the same truth table…

ECEn 224 09 MUX © 2003-2008

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 Using a Bigger MUX
Using AB as the select input …

A B C F
0 0 0 0 AB=00 part of the truth table
0 0 1 0 … when AB=00, F=0 00
0 1 0 1 AB=01 part of the truth table
0
C’ 01
F
0 1 1 0 … when AB=01, F=C’ 1 10
1 0 0 1 AB=10 part of the truth table C 11
1 0 1 1 … when AB=10, F=1
1 1 0 0 AB=11 part of the truth table
… when AB=11, F=C AB
1 1 1 1

Can easily re-order truth table to use different MUX control inputs

ECEn 224 09 MUX © 2003-2008

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 Another 4:1 MUX Example

A B F
0 0 1 1 00

0 1 1 1 01
F
0 10
1 0 0 1 11

1 1 1
AB

This shows that a large enough MUX can directly implement a truth table…

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Implement: Z = A’B + BC’

I0
AB
C 00 01 11 10 I1 4-to-1
MUX Z
0
I2

1
I3

A B

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 Implementing Logic Functions With
Muxes
Implement: Z = A’B + BC’

0 I0
AB
C 00 01 11 10 I1 4-to-1
MUX Z
0 0 1 1 0 I2

1 0 1 0 0
I3

for AB=00, Z=0

A B

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Implement: Z = A’B + BC’

0 I0
AB
C 00 01 11 10 1 I1 4-to-1
MUX Z
0 0 1 1 0 I2

1 0 1 0 0
I3

for AB=01, Z=1

A B

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Implement: Z = A’B + BC’

0 I0
AB
C 00 01 11 10 1 I1 4-to-1
MUX Z
0 0 1 1 0 0 I2

1 0 1 0 0
I3

for AB=10, Z=0

A B

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Implement: Z = A’B + BC’

0 I0
AB
C 00 01 11 10 1 I1 4-to-1
MUX Z
0 0 1 1 0 0 I2

1 0 1 0 0
C’ I3

for AB=11, Z=C’

A B

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
An alternate method
Z = A’B + BC’
A=0 B=0 Z = 1•0 + 0•C’ = 0 I0
0

A=0 B=1 Z = 1•1 + 1•C’ = 1 1 I1 4-to-1

MUX Z

0 I2
A=1 B=0 Z = 0•0 + 0•C’ = 0
C’ I3
A=1 B=1 Z = 0•1 + 1•C’ = C’

A B

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB
CD 00 01 11 10

00
0 4 12 8

01
1 5 13 9

11
3 7 15 11

10
2 6 14 10

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB
CD 00 01 11 10

00 X 1 X
0 4 12 8

01 1
1 5 13 9

11 13 7
115 111

10 X 1
2 6 14 10

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB I0
CD 00 01 11 10 I1
I2
00 X 1 X I3
8-to-1 Z
MUX
I4
01 1
I5
11 1 1 1 I6
I7
10 X 1

A B C

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB 0 I0
CD 00 01 11 10 I1
I2
00 X 1 X I3
8-to-1 Z
MUX
I4
01 1
I5
11 1 1 1 I6
I7
10 X 1

A B C

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB 0 I0
CD 00 01 11 10 D I1
I2
00 X 1 X I3
8-to-1 Z
MUX
I4
01 1
I5
11 1 1 1 I6
I7
10 X 1

A B C

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB 0 I0
CD 00 01 11 10 D I1
1 I2
00 X 1 X I3
8-to-1 Z
MUX
I4
01 1
I5
11 1 1 1 I6
I7
10 X 1

A B C

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB 0 I0
CD 00 01 11 10 D I1
1 I2
00 X 1 X 0 I3
8-to-1 Z
MUX
I4
01 1
I5
11 1 1 1 I6
I7
10 X 1

A B C

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB 0 I0
CD 00 01 11 10 D I1
1 I2
00 X 1 X 0 I3
8-to-1 Z
MUX
0 I4
01 1
I5
11 1 1 1 I6
I7
10 X 1

A B C

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB 0 I0
CD 00 01 11 10 D I1
1 I2
00 X 1 X 0 I3
8-to-1 Z
MUX
0 I4
01 1
1 I5
11 1 1 1 I6
I7
10 X 1

A B C

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB 0 I0
CD 00 01 11 10 D I1
1 I2
00 X 1 X 0 I3
8-to-1 Z
MUX
0 I4
01 1
1 I5
11 1 1 1 D’ I6
I7
10 X 1

A B C

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB 0 I0
CD 00 01 11 10 D I1
1 I2
00 X 1 X 0 I3
8-to-1 Z
MUX
0 I4
01 1
1 I5
11 1 1 1 D’ I6
1 I7
10 X 1

A B C

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB I0
CD 00 01 11 10 I1
I2
00 X 1 X I3
8-to-1 Z
MUX
I4
01 1
I5
11 1 1 1 I6
I7
10 X 1

A C D

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB 0 I0
CD 00 01 11 10 I1
I2
00 X 1 X I3
8-to-1 Z
MUX
I4
01 1
I5
11 1 1 1 I6
I7
10 X 1

A C D

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB 0 I0
CD 00 01 11 10 B I1
I2
00 X 1 X I3
8-to-1 Z
MUX
I4
01 1
I5
11 1 1 1 I6
I7
10 X 1

A C D

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB 0 I0
CD 00 01 11 10 B I1
0 I2
00 X 1 X I3
8-to-1 Z
MUX
I4
01 1
I5
11 1 1 1 I6
I7
10 X 1

A C D

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB 0 I0
CD 00 01 11 10 B I1
0 I2
00 X 1 X B’ I3
8-to-1 Z
MUX
I4
01 1
I5
11 1 1 1 I6
I7
10 X 1

A C D

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB 0 I0
CD 00 01 11 10 B I1
0 I2
00 X 1 X B’ I3
8-to-1 Z
MUX
1 I4
01 1
I5
11 1 1 1 I6
I7
10 X 1

A C D

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB 0 I0
CD 00 01 11 10 B I1
0 I2
00 X 1 X B’ I3
8-to-1 Z
MUX
1 I4
01 1
0 I5
11 1 1 1 I6
I7
10 X 1

A C D

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB 0 I0
CD 00 01 11 10 B I1
0 I2
00 X 1 X B’ I3
8-to-1 Z
MUX
1 I4
01 1
0 I5
11 1 1 1 1 I6
I7
10 X 1

A C D

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB 0 I0
CD 00 01 11 10 B I1
0 I2
00 X 1 X B’ I3
8-to-1 Z
MUX
1 I4
01 1
0 I5
11 1 1 1 1 I6
1 I7
10 X 1

A C D

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
An alternate method
AB
CD 00 01 11 10

00 X 1 X
I0
01 1 I1
I2
8-to-1 Z
11 1 1 1 I3 MUX
I4
10 X 1 I5
I6
Z = AC + AD’ + A’BC’ + B’CD I7

A C D

ECEn 224 09 MUX © 2003-2008

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Implementing Logic Functions With
Muxes
An alternate method

A C D Z = AC + AD’ + A’BC’ + B’CD

0 0 0 Z = (0)(0) + (0)(1) + (1)B(1) + B’(0)(0) = B

0 0 1 Z = (0)(0) + (0)(0) + (1)B(1) + B’(0)(1) = B

0 1 0 Z = (0)(1) + (0)(1) + (1)B(0) + B’(1)(0) = 0

0 1 1 Z = (0)(1) + (0)(0) + (1)B(0) + B’(1)(1) = B’

1 0 0 Z = (1)(0) + (1)(1) + (0)B(1) + B’(0)(0) = 1

1 0 1 Z = (1)(0) + (1)(0) + (0)B(1) + B’(0)(1) = 0

1 1 0 Z = (1)(1) + (1)(1) + (0)B(0) + B’(1)(0) = 1

1 1 1 Z = (1)(1) + (1)(0) + (0)B(1) + B’(1)(1) = 1

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
An alternate method
AB
CD 00 01 11 10

00 X 1 X
B I0
01 1 B I1
0 I2
8-to-1 Z
11 1 1 1 B’ I3 MUX
1 I4
10 X 1 0 I5
1 I6
Z = AC + AD’ + A’BC’ + B’CD 1 I7

A C D

ECEn 224 09 MUX © 2003-2008

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Implementing Logic Functions With
Muxes
An alternate method

A C D Alternate Method Original Method

0 0 0 Z = B Z = 0

0 0 1 Z = B Z = B Why
0 1 0 Z = 0 Z = 0 are
they
0 1 1 Z = B’ Z = B’
different?
1 0 0 Z = 1 Z = 1

1 0 1 Z = 0 Z = 0

1 1 0 Z = 1 Z = 1

1 1 1 Z = 1 Z = 1

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
AB
CD 00 01 11 10
The original method used this grouping.
00 X 1 X X was determined to be “0”.

01 1

11 1 1 1

10 X 1

Z = AC + AD’ + A’BC’ + B’CD

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
AB
CD 00 01 11 10
The alternate method used this grouping.
00 X 1 X X was determined to be “1”.

01 1

11 1 1 1

10 X 1

Z = AC + AD’ + A’BC’ + B’CD

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
An alternate method
AB
CD 00 01 11 10
The new method used this grouping.
00 X 1 X X was determined to be “1”.

01 1

11 1 1 1 Which is right??
10 X 1 They both are!!!!
Z = AC + AD’ + A’BC’ + B’CD

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic Functions With
Muxes
Z (A,B,C,D) = Σ m(3,5,10,11,12,15) + Σ d (4,8,14)
AB I0
B
CD 00 01 11 10
B'
I1 4-to-1
00 X 1 X D
MUX Z
D’ I2
01 1

11 1 1 1 1 I3

10 X 1

A C
F = A’B’CD = (0)’B’(1)D = B’D

ECEn 224 09 MUX © 2003-2008

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Implementing Logic Functions With
Muxes
An alternate method

A C Z = AC + AD’ + A’BC’ + B’CD

0 0 Z = (0)(0) + (0)D’ + (1)B(1) + B’(0)D = B

0 1 Z = (0)(1) + (0)D’ + (1)B(0) + B’(1)D = B’D

1 0 Z = (1)(0) + (1)D’ + (0)B(1) + B’(0)D = D’

1 1 Z = (1)(1) + (1)D’ + (0)B(0) + B’(1)D = 1

Same as before!

ECEn 224 09 MUX © 2003-2008

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Decoders

ECEn 224 09 MUX © 2003-2008

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Decoder Symbol

F0
I1 F1
I0 F2
F3

© 2003-2008
BYU
 Decoder Behavior
F0 1 F0 0
0 I1 F1 0 0 I1 F1 1
0 I0 F2 0 1 I0 F2 0
F3 0 F3 0

F0 0 F0 0
1 I1 F1 0 1 I1 F1 0
0 I0 F2 1 1 I0 F2 0
F3 0 F3 1

Key idea: The device decodes an input bus by

asserting the appropriate output.

This is called a 2:4 decoder (pronounced “two-to-four”)

© 2003-2008
BYU
 2:4 Decoder

A B Q0 Q1 Q2 Q3
Q0
A 2:4 Q1 0 0
B Decoder Q2 0 1
Q3 1 0
1 1

ECEn 224 09 MUX © 2003-2008

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 2:4 Decoder

A B Q0 Q1 Q2 Q3
Q0
A 2:4 Q1 0 0 1 0 0 0
B Decoder Q2 0 1 0 1 0 0
Q3 1 0 0 0 1 0
1 1 0 0 0 1

Q0 = A’B’ = m0
Q1 = A’B = m1
Q2 = AB’ = m2
Q3 = AB = m3

A decoder is a minterm generator…

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 3:8 Decoder
A B C Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0 3:8
0 1 1 0 0 0 1 0 0 0 0 Decoder
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Q0 = A’B’C’ = m0
Q1 = A’B’C = m1
Q2 = A’BC’ = m2
… …
Q7 = ABC = m7

ECEn 224 09 MUX © 2003-2008

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 Implementing Logic With Decoders
m0

2:4
m2 F = Σ m(0, 2)
Decode

m1
2:4
m2 F = Π M(1, 2)
Decode

M0

2:4
F = Σ m(0, 3)
Decode
M3

Historically, some decoders have come with inverted outputs…

ECEn 224 09 MUX © 2003-2008
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 Uses of Decoders

• Decode 3-bit op-code into a set of 8 signals

ADD
SUB
op2 AND
3:8 XOR
op1
Decoder NOT
op0 LOAD
STORE
JUMP

ECEn 224 09 MUX © 2003-2008

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ROM: Read Only Memory

ECEn 224 09 MUX © 2003-2008

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 ROM: Read-Only Memory

• Can read values from it

• Cannot write to it
• Often used as lookup tables and called LUTs

ECEn 224 09 MUX © 2003-2008

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 ROM: Read-Only Memory

• Example: 8-entry ROM with 1-bit output
8x1

Each entry is 1 bit

Address Data
0 1
1 0
2 1
3 0 Addr 8x1 Data
4 0 In ROM Out
5 1
6 1
7 0

ECEn 224 09 MUX © 2003-2008

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 ROM: Read-Only Memory

• Example: 8-entry ROM with 5-bit output
8x5

Each entry is a 5-bit word

Address Data
0 0
1 7
2 2
Addr 8x5 Data
3 14
In ROM Out
4 26
5 0
6 18
7 22

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 Read Only Memory (ROM)
Each minterm of each function can be specified
A B C F4 F3 F2 F1 F0
0 0 0 0 0 0 0 1
3 Inputs A ROM
0 0 1 0 0 1 1 0
Lines B 8 words 0 1 0 0 0 1 1 0
C x 5 bits 0 1 1 1 0 1 0 1
1 0 0 0 0 1 1 0
1 0 1 0 0 1 0 1
F4 F3 F2 F1 F0 1 1 0 1 0 1 0 1
5 Outputs Lines 1 1 1 1 1 1 1 0

When you program a ROM,

you are specifying this

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 ROM – View #1

• An addressable memory
– Send in address (addr)
– Receive data (d) stored addr2
8x5
addr1
at that location addr0
ROM

– Can have multi-bit data

d4 d3 d2 d1 d0

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 ROM – View #2
• A hardware implementation of a truth table

A
A B C F B
0 0 0 0 F
B
0 0 1 0 C
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0 A
8x1
1 1 0 1 B ROM F
1 1 1 1 C

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 ROM – Two Different Views

• Both views are accurate

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 ROM Internal Structure

n Input n:2n .
.. Memory Array
Lines . decoder .
. 2n words x m bits

...

m Output Lines

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 ROM Memory Array Resistor – pulls column
down to ‘0’ if no row
0V 0V 0V 0V 0V wire drives it high.

m0=A’B’C’
m1=A’B’C
m2=A’BC’
A
3:8 m3=A’BC
B m4=AB’C’
Decoder
C m5=AB’C
m6=ABC’
m7=ABC

F0 = m0 + m3 F4 F3 F2 F1 F0
F1 = m2 + m7
F2 = m4 + m6 Diode - acts like a one-way
F3 = m0 + m1 + m2 + m5  conduit. Its presence causes the
F4 = m1 + m4 + m7 column to become ‘1’ when the
row is decoded.

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 ROM Memory Array
0V 0V 0V 0V 0V

m0=A’B’C’
m1=A’B’C
m2=A’BC’
A
3:8 m3=A’BC
B m4=AB’C’
Decoder
C m5=AB’C
m6=ABC’
m7=ABC

F4 F3 F2 F1 F0
A B C F4 F3 F2 F1 F0
0 0 0 0 1 0 0 1
0 0 1 1 1 0 0 0
0 1 0 0 1 0 1 0
0 1 1 0 0 0 0 1
1 0 0 1 0 1 0 0
1 0 1 0 1 0 0 0
1 1 0 0 0 1 0 0
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 ROM Technologies:
Not Always Diode-Based
• PROM (Programmable Read Only Memory)
– Mask programmable
– Fusible Link
• EPROM (Erasable PROM)
– Can be erased with ultraviolet light
• EEPROM (Electronically Erasable PROM)
– Can be electrically erased
• Flash
– Can also be electronically erased
– Available in very high densities
– Used in cell phones, MP3 players, cameras, and more!

The details of these technologies are beyond the scope of this class.

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 Using a ROM For Logic

F = AB + A’BC’ A B C F G H
G = A’B’C + C’ 0 0 0
H = AB’C’ + ABC’ + A’B’C 0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

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 Using a ROM For Logic

F = AB + A’BC’ A B C F G H
G = A’B’C + C’ 0 0 0 0
H = AB’C’ + ABC’ + A’B’C 0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

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 Using a ROM For Logic

F = AB + A’BC’ A B C F G H
G = A’B’C + C’ 0 0 0 0 1 0
H = AB’C’ + ABC’ + A’B’C 0 0 1 0 1 1
0 1 0 1 1 0
0 1 1 0 0 0
1 0 0 0 1 1
1 0 1 0 0 0
1 1 0 1 1 1
1 1 1 1 0 0 What size
ROM is this?
Just fill out the truth table

CAD tools usually do the rest…

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Using ROM for Combinational Logic
A B C D Q
0 0 0 0 1
0
0
0
0
0
1
1
0
0
1
ROM16X1
A
0 0 1 1 1 a3
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0 B a2
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0 C a1
1 0 1 0 1
1 0 1 1 0 INIT=????
1 1 0 0 0 D a0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1 • ROM16X1 is a Xilinx cell
• Insert it into schematics like any other primitive
• Set its contents by double-clicking on inserted
cell in schematic.

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Using ROM for Combinational Logic
A B C D Q
1000 0100 0000 1101 Note that ABCD = 0000 is
0 0 0 0 1
the least significant bit
0 0 0 1 0 8 4 0 D
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 ROM16X1
0 1 0 1 0 A
0 1 1 0 0
a3
0 1 1 1 0
1 0 0 0 0
B a2
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0 C a1
1 1 0 1 0 INIT=840D
1 1 1 0 0
1 1 1 1 1 D a0

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 ROM Types in Xilinx FPGAs

• ROM16X1 = 4-input LUT

– Specify INIT contents with 4-digit HEX value
• ROM32X1 = 5-input LUT
– Specify INIT contents with 8-digit HEX value

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