Systems Test

BUILT-IN SELF-TEST

A new technology
for System-on-Chip
Traditional test
technologies, such as
ATPG, cannot cope with
the manufacturing
challenges posed by
System-on-Chip (SoC).
Use Built-In Self-Test
(BIST) to get adequate
fault coverage in SoCs.
The use of Automatic Test Pattern
Generation (ATPG) programs to
generate manufacturing tests for
VLSI designs became popular in the
early 1990s. Soon, it was also
recognized that test circuitry must be
added to a design to simplify ATPG.
This technique is called Design For
Test (DFT).
ATPG limitations
It is now possible to efficiently
fabricate ICs with several million
gates due to the rapid advances in
semiconductor manufacturing tech-
nology. The increased size and
complexity of System-on-Chip (SoC)
designs have, however, reduced the
effectiveness of ATPG. SoC designers
may not have the entire gate level
model available for performing
ATPG. Also the CPU time and
memory requirements of ATPG grow
non-linearly with the number of gates
on a chip.
Thus full-chip ATPG techniques do
not scale to handle SoC designs. Scan
ATPG patterns for SoC also exceed

Tap

Controller
O
I u
n t
p S R
p
u t e
u
P t i s P
t
a m p a
RAM d
d l u o
By Bejoy G. Oomman s l n l s
o o
President g u s
g
Genesys Testware Inc. i s e
i
c c

Figure 11: BIST is the only test technology that performs at-speed testing since the circuitry uses the
same technology as the CUT.

2 Electronics Engineer April 2000

 Systems Test
BUILT-IN SELF-TEST
ORE
Result
BIC
DPG
Command APG
Address
Data
Control
Figure 2
2: The FBS circuit is used to select between the BIST stimulus and the functional inputs to
the memory.
the test-time and tester-memory
capabilities of the current generation
of Automatic Test Equipment (ATE).
This reduces the effective fault
coverage affecting product quality or
increases test application time in-
creasing unit cost. In addition, deep
submicron ICs also exhibit dynamic
failure mechanisms that can only be
detected by at-speed testing. ATE
cannot keep up with the high clock
rates of the latest ICs since they are
built using older semiconductor
technology.
Because of the limitations of
conventional ATPG techniques, a
relatively new DFT method called
Built-In Self-Test (BIST) was devel-
oped. Instead of storing test patterns
in an ATE system, a stimulus circuit
and a response circuit are added to the
circuit under test (CUT) as shown in
figure 1. The stimulus circuit gener-
ates large amounts of stimulus on the
fly, applies it to the CUT and the
response circuit evaluates the re-
sponse of the CUT. Unlike ATE, BIST
performance is not limited by the
electrical characteristics of the load
board or the test head.
It is also possible to significantly
reduce the complexity of SoC test
3 Electronics Engineer April 2000
FBS RAM
generation by using BIST on reusable
designs (cores) or on large blocks
within the SoC. Cores with embedded
test circuitry free SoC developers
from the responsibility of generating
manufacturing tests. This enables a
true plug-and-play SoC design.
Once BIST circuits are embedded
into most of the ICs in a system, it can
also be used for simplifying manufac-
turing test and system integration at
the Multi-Chip Module (MCM),
board- or system-level. With the
widespread adoption of BIST tech-
niques in SoC, manufacturing manag-
ers can reduce capital expenditures by
using simpler ATE since few external
test patterns are needed.
Testing embedded memory
Various types of embedded memories
(SRAM, FIFO, DRAM, ROM,
FLASH, EEPROM, CAM) occupy a
large percentage of the die area of an
SoC. Memories exhibit complex
failure mechanisms due to their dense
layout. The common memory prob-
lems are address, cell stuck-at, cell-
transition, coupling, pattern-sensitive
and dynamic faults.
Embedded memories tend to be
much wider than stand-alone memo-
Whats Online
Testing mixed-signal ICs
using digital BIST
As the number of complex, mixed-signal
circuits increase, designers are looking
for a test solution that will reduce
costs and development time. An all-
digital BIST approach to mixed-signal
test will offer you the industrial
strength solution.
www.ee.globalsources.com/
ART_8800009576.HTM
Design for test
considerations for ATPG
This article describes techniques for
designing ICs to facilitate ATPG, and
explains the importance of compact
test vector generation in the overall
design flow.
www.ee.globalsources.com/
ART_8800018027.HTM
www.ee.globalsources.com
ries due to the absence of any package
limitations. The standard memory
algorithms can be extended to large
memories by using multiple data
backgrounds.
The block diagram of a typical
BIST circuit for embedded SRAM is
shown in figure 2. The major blocks
are a Function to BIST Selector
(FBS), BIST Interface Controller
(BIC), Address Pattern Generator
(APG), Data Pattern Generator
(DPG), and Output Response Evalua-
tor (ORE).
Embedded DRAMs are now widely
used in portable graphics and net-
working chips. In addition to the
static faults exhibited by SRAMs,
DRAMs exhibit various dynamic
failure mechanisms, such as retention
faults, recovery faults and address
decoder stuck-open faults. Additional
tests have to be performed on
DRAMs for detecting these faults.
Embedded DRAMs, unlike stand-
alone DRAMs, tend to have de-
multiplexed address buses. They also
contain spare rows and columns such
that a single-bit failure does not cause
a rejection of the manufactured SoC.
 Systems Test
BUILT-IN SELF-TEST
orc
Result
RSC
Control
Address
Clock
Figure 3
3: Typical ROM BIST circuit block diagram. You need to calculate the signature of the ROM
contents using a CRC circuit.
Faulty cells are substituted with spare
cells by blowing fuses using a laser.
This capability is essential for produc-
ing SoCs with embedded DRAM
having adequate yield. So, an embed-
ded test circuit for DRAM should not
only perform self-test, but also self-
diagnosis and self-repair as well.
You can test a ROM by calculating
the signature of its contents using a
cyclic redundancy check (CRC)
circuit (figure 3). The major blocks
are the FBS, the ROM State Control-
ler (RSC) and the Output Response
Compressor (ORC).
Flash memories operate like an
SRAM with a very long write cycle.
In some flash memories only block
writes are allowed. The unit cost of
embedded flash memory can be
high due to the high test application
time caused by the slow writes. BIST
can significantly reduce test applica-
tion time by testing multiple arrays
in parallel.
Content Addressable Memories
(CAMs) are widely used for cache
applications and for network packet
processing. You can extend the
SRAM test algorithms to CAMs by
4 Electronics Engineer April 2000
FBS ROM
performing indirect reads using the
match output port. The comparator
present in each CAM cell also has to
be tested thoroughly to achieve high
fault coverage.
A typical SoC will have several
small SRAMs and FIFOs, a few
ROMs and a few large SRAMs. It is
important to share the BIST circuit
among the small FIFOs and SRAMs
to reduce the area overhead of BIST.
Logic test
Logic BIST circuits typically gener-
ate pseudo random stimuli, which are
transported using scan chains into
the core under test. The response of
the CUT is shifted out and com-
pressed into a signature after each
test. After all the BIST tests are
applied, the final signature is
scanned out and compared with the
expected signature.
The stimulus generator is imple-
mented using a circuit called the
Parallel Random Pattern Generator
(PRPG). The PRPG is often imple-
mented using a class of circuits
called Linear Feedback Shift Regis-
ters (LFSR). An LFSR with N flip-
flops creates a pseudo random
sequence of states that repeats after
(2N 1) cycles. The all 0 state is an
illegal state for an LFSR. The length
of the LFSR must be made larger
than the number of pseudo random
channels driven by it to compensate
for this.
The response evaluator is imple-
mented using a circuit called a
Multiple Input Signature Register
(MISR). The major blocks are the
BIC, PRPG and MISR (figure 4).
Note that there is a PRPG that drives
parallel inputs and a PRPG that drives
serial scan chains. There is also an
MISR that compresses parallel
output responses and another that
compresses the response of the serial
scan chains.
The test application time for scan-
based BIST depends primarily on the
length of the longest scan chain in the
circuit. You would usually create
separate scan chains for flip-flops in
separate clock domains. For ATPG
patterns the number of scan chains in
the design is usually limited to eight
due to ATE limitations.
A much larger number of scan
chains is used for BIST applications
since the number of scan tests
generated by the embedded test
circuitry is much higher. The maxi-
mum scan-chain length is usually
limited to 256 in order to reduce test
application time. It is not unusual for
logic BIST circuits to interface to 32
or 64 scan chains.
Since the circuit response is not
compared with the expected response
for each test pattern, it is possible
that some faults, if present in the
manufactured circuit, would result in
a signature that is identical to the
expected signature. This problem is
called aliasing and can reduce the
effective fault coverage of the test.
Fortunately the aliasing probability
for an N bit MISR is approximately
2-N. In practice, the aliasing probabil-
ity can be practically eliminated by
making N large.
 Systems Test
BUILT-IN SELF-TEST
The fault coverage achieved by
logic BIST depends on the functional-
ity of the CUT. Hence, calculate the
fault coverage achieved by logic BIST
test patterns on a particular CUT
using fault simulation programs.
Higher fault coverage can usually be
achieved by increasing the test length.
A control point is implemented by
adding a multiplexer, which selects
between the functional node and a
control point, to a node with poor
controllability. The control point is
MISR
P M
R I
PI P
CUT
G R
PRPG
BIC
TDI
Figure 4
4: If the core under test is fully registered, the parallel PRPG and the parallel MISR can be
eliminated.
selected during BIST operation.
Control points are controlled by scan
flip-flops or primary inputs. Observe
points are usually passed through
exclusive OR gates before being
observed using scan flip-flops or
primary outputs.
Pitfalls
Control points can affect the perfor-
mance of the design by increasing the
delay of the critical paths in your
design. Another problem with test
point insertion is its incompatibility
with high-level design flows. Physical
5 Electronics Engineer April 2000
synthesis tools used for large SoCs
produce a fully placed netlist to
simplify the problem of timing
convergence. So gate-level test-point
insertion in the post-synthesis netlist
can invalidate the placement and
timing results produced by the
physical synthesis process. You can
use other techniques, such as
weighted random and biased random-
pattern generators, to increase fault
coverage in random pattern resistant
circuits without test point insertion.
PO
S
TDO
Another major issue with response
compression using MISR is signature
corruption. An internal tristate bus can
create unknown states (X) due to bus
contention if the bus control logic is
in an illegal state. A pass transistor
logic circuit can also produce an X at
its output due to wire contention if the
inputs are in an illegal state.
It is difficult to prevent such illegal
stimulus from causing unknown states
in the circuit, since BIST stimulus is
random. Also, since the feedback
logic in an MISR is entirely made of
exclusive OR gates, its state rapidly
becomes all X within a few cycles
after an X state is captured in any of
its flip-flops.
The best solution to the problem of
unknown states is to create a circuit
that cannot produce unknown states.
Pass transistor logic should be
designed such that illegal states
disable all paths to the output node,
and the output node has a resistive
pullup or pulldown circuit. Synchro-
nous memories can be used to prevent
timing violations.
You can also solve the signature
corruption problem by adding appro-
priate mechanism to the CUT. The
outputs of an asynchronous memory
can be forced to a fixed value (all 0 or
all 1) during logic BIST operation
using scan flip-flops and output
multiplexers. This functionality can
be easily added to the BIST wrapper
of the embedded memory.
It is also possible to mask the scan
flip-flops or primary outputs where
the unknown states can be observed in
the logic BIST controller. You can
constrain certain scan flip-flops or
primary inputs to a fixed 0 or 1 value
during logic BIST operation.
Scan-based logic BIST is the logical
extension of a synchronous, full-scan
design methodology. The circuit
structures that reduce the effective-
ness of full-scan ATPG, like internally
generated clocks, resets and clears,
can also significantly impact the
effectiveness of logic BIST.
SoC presents a new paradigm in
the design and manufacture of
electronic systems. It is not sufficient
to extrapolate proven manufacturing
test generation techniques such as
ATPG from VLSI to SoC. Wide-
spread adoption of BIST techniques
by core developers is essential for
producing of a cost-effective SoC in
a timely manner.
You may e-mail your comments to Bejoy
G. Oomman at bejoygo@genesystest.com
or fax: 1-510-4988734.