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March 2017
Introduction
For systems demanding a large number of synchronized concerns by providing three multichip synchronization
clock signals, a clock tree using multiple clock devices options: EZSync, ParallelSync, and EZParallelSync/
is often required. Multiple clock devices can add system EZ204Sync. This application note provides step by
complexity when compared to a single clock distribution step design examples for each multichip synchronization
device. One complexity created is the ability to synchronize method.
the clock phases and start times across multiple clock
Table 1 provides a summarized comparison of each
devices. The other challenge created is maintaining the
synchronization method. Application Note 165 provides
desired low jitter clock performance when cascading
detailed descriptions and trade-offs of each synchronization
multiple clock devices.
method.
Linear Technologys family of PLL/VCO and clock distribu- L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
LTC6951Wizard, EZ204Sync, EZParallelSync, EZSync and ParallelSync are trademarks of
tion ICs address both the synchronization and performance Analog Devices, Inc. All other trademarks are the property of their respective owners.
Table of Contents
Introduction..........................................................................................................................1
EZSync Design Example...........................................................................................................2
ParallelSync Design Example.................................................................................................. 10
JESD204B ParallelSync Design Example 2 (Based off DC2226 Demo Board)........................................... 21
EZParallelSync Design Example............................................................................................... 32
EZ204Sync Design Example..................................................................................................... 42
Appendix: Model Reference Noise for LTC6951Wizard Simulations..................................................... 53
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Application Note 161
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Application Note 161
An LTC6954 output is set to FOLLOW mode when the LTC6951 EZSync Design Rules
respective LTC6954 SYNC_ENx register bit is set high.
1. CONTROLLER set to CONTROL Mode. For LTC6951
Follower-Driver: CONTROLLERs clock output that is register settings:
connected to a FOLLOWERs clock input. DC coupling
a. SN=0
is required between the CONTROLLER output and FOL-
LOWER input. b. SR=0
During a SYNC event, the Follower-Driver outputs are set 2. FOLLOWER outputs set to FOLLOW Mode. For LTC6954
to a logic low. set register setting SYNC_ENX=1 for each output.
Follower-Synchronous: CONTROLLERs clock output that 3. EZSync CONTROLLER to FOLLOWER Connection re-
is synchronized to a FOLLOWER devices clock outputs. quires DC coupling.
During a SYNC event the Follower-Synchronous output 4. EZSync timing requirements:
is set to a logic low. a. Sync Pulse width > 1ms
Following a SYNC event the Follower-Synchronous and b. Sync Pulse skew between parts <10s
FOLLOWER clock edges are aligned based on the delay
settings in the CONTROLLERs and FOLLOWERs register EZSync Design Example
map.
This design example will use the LTC6951Wizard to
Synchronization Disabled: Outputs that are not synchro- aid in the design process. Download LTC6951Wizard at
nized to Follower-Driver or Follower-Synchronous outputs. http://www.linear.com/LTC6951Wizard.
These outputs remain active during synchronization.
This example assumes the following list of design inputs:
Synchronizing the LTC6951 outputs in Figure1 involves
Reference
sending a common sync signal that meets EZSync tim-
fREF=100MHz
ing requirements. These are provided in Figure1 and the
LTC6951 EZSync Design Rules section. LTC6951: EZSync CONTROLLER
OUT0 2.4GHz Follower-Synchronous
The section titled LTC6951 EZSync Design Rules summa- OUT1 1.2GHz Follower-Driver Outputs
rizes the EZSync design rules. The section titled EZSync OUT2 1.2GHz Follower-Driver Outputs
Design Example section provides the design process used OUT3 37.5MHz Follower-Synchronous
to develop the block diagram in Figure 1. The section OUT4 100MHz Synchronization Disabled FPGA clock
titled Delay and Layout Recommendations provides how
LTC6954: EZSync FOLLOWERs
to minimize skew between parts by accounting for line
F6954#1-OUT0=300MHz
length delays, FOLLOWER propagation delays and deltas
F6954#1-OUT1=37.5MHz
in FOLLOWER and CONTROLLER rise and fall times. The
F6954#1-OUT2=300MHz
section titled Synchronization Routines, provides initial
F6954#2-OUT0=37.5MHz
power-up, power-down and resynchronization sequences.
F6954#2-OUT1=300MHz
The Expandable Solution section discusses how the block F6954#2-OUT2=37.5MHz
diagram in Figure1 can expand to support more clock
Delay Align the rising edge of LTC6951 and LTC6954 SYSREF
outputs. settings signal to the falling edge of the clock signals.
Performance Optimization Request
Design for low jitter.
Minimize the output skew between devices.
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Application Note 161
LTC6951 Setup The values calculated in Steps 1 and 2 and conditions pro-
Based on the EZSync Design Rules and the above design vided at the start of this design example are summarized
below for a quick reference. These values will be used
inputs, the following steps provide input conditions for
the LTC6951Wizard. for inputs to the LTC6951Wizard to calculate the register
settings and loop filter values for both LTC6951s in this
Step 1: Design input: optimize the LTC6951 charge pump design example.
current for low jitter.
LTC6951Wizard Inputs for Figure2:
Based on the LTC6951 data sheet the best jitter performance
is obtained by maximizing the LTC6951 ICP current. f6951.REF=100MHz
f6951.OUT0=2.4GHz
ICLK6951.CP=11.2mA f6951.OUT1=1.2GHz
Step 2: Design input: align LTC6951 SYSREF rising edge f6951.OUT2=1.2GHz
to the LTC6951 2.4GHz falling edge. f6951.OUT3=37.5MHz
f6951.OUT4=100MHz
Assign the LTC6951 output invert bits as follows:
I6951.CP=11.2mA
OINV06951=1 (OUT0=2.4GHz) OUT0 Delay=0
OINV16951=0 (OUT1=SYSREF) OUT3 Delay=7
The section Delay and Layout Recommendations will Figures2 and3 provide the remaining steps necessary
discuss how to determine delay register settings to align to complete the LTC6951 portion of this design. Several
LTC6951 Follower-Synchronous outputs and LTC6954 steps in these Figures2 and3 require the following ad-
outputs. This example will assume the following inputs ditional information.
to the LTC6951Wizard tool Importing Reference Noise
OUT0 Delay=0* Refer to Appendix: Model Reference Noise for
OUT3 Delay=7* LTC6951Wizard Simulations, which describes how to
import reference noise into the LTC6951Wizard and the
*These values are equivalent to Dx in Equation2 under impact of reference noise on loop filter calculations and
the section Delay and Layout Recommendations. output noise simulations. The CCHD575_REFNOISE.txt
file provided with the LTC6951Wizard should be used for
LTC6951Wizard this example.
This section demonstrates the LTC6951Wizards ability to Loop Filter Selection
ease the register setting creation and loop filter design for
the LTC6951. Under the LTC6951Wizards Help Menu a Figure3s step 10 selected Filter 2. Through experimenta-
Help Guide is provided that will aid in understanding the tion Filter 2 was found to be the best option to optimize
operations performed in this section. performance and board space.
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Application Note 161
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Application Note 161
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Application Note 161
DLY06954#2=2 DEL16954#2=0
DLY16954#2=0 M26954#2=32
DLY26954#2=2 DEL26954#2=2
Step 6: Design input: minimize the output skew perfor- Delay and Layout Recommendations
mance between the LTC6954-1 #1 and LTC6954-1 #2.
Minimizing output skew between an LTC6951 EZSync
Per the LTC6954 data sheet output to output skew is best CONTROLLER output and an EZSync FOLLOWER output
when all LTC6954 divider values are either equal to /1 or
can be performed by solving Equations2 to 6 (refer to
all divider values are greater than /1. In this example the
Figure5).
LTC6954 input frequency was chosen such that all LTC6954
dividers are greater than /1. Equations1 and 2 align the starting edges of the CON-
TROLLERs Follower-Synchronous output and Followers
Step 7: LTC6954 settings summarized: outputs. Equation1 is provided in the LTC6951 data sheet
Register settings: and shown below for consistency. Equation2 expands upon
Equation1 by translating the trace lengths, FOLLOWER
SYNCENX6954=1
propagation delay and rise time to the nearest LTC6951
PDIVX6954=0
P-divider cycle delay value.
PDOUTX6954=0
CONTROLLER Follower-Synchronous
M06954#1=4
DEL06954#1=0 DFSX=Dx + MFDY 7 (1)
M16954#1=32 DFSX = Dx +MFDY 7 + (2)
DEL16954#1=2
M26954#1=4 (d2+ d3 d1)
DEL26954#1=0
M06954#2=32
int +tpd(FOLLOWER) f PD+ 0.5
DEL06954#2=2 + tr(FOLLOWER)
M16954#2=4 2
LTC6951 CONTROLLER
REF PLL
P-DIVIDER
REF+ VCO
OUT4+
OUT4
L1
fPD OUT3+ CLK+
DFSX MFSX
OUT3 CLK
EZSync: FOLLOWER-SYNCHRONOUS
OUT0+
OUT0
OUT1+
OUT1 LTC6954 FOLLOWER
L2 L3
MFDY OUT2+ DFY MFY OUT0+ CLK+
OUT2 OUT0 CLK
EZSync: FOLLOWER-DRIVER
NOTE: REQUIRES DC COUPLING OUT1+
OUT1 tr(FOLLOWER)
OUT2+
tpd(FOLLOWER) OUT2 AN161 F05
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Application Note 161
Equations3 and 4 convert the boards trace length to a Synchronization Routines
signal delay.
On initial power-up:
Trace Length
1. Program LTC6954 and LTC6951 SPI registers
dx=LX/Vp (3) 2. Wait for LTC6951 bias voltages to stabilize
c
Vp = (4) 3. Calibrate LTC6951 VCO
r
4. Wait for VCO calibration to complete
Equation5 calculates the FOLLOWERs delay setting in
5. Send EZSync pulse
terms of the CONTROLLER delay settings. Equation 6
calculates the desired delay delta between a Follower- Power-down:
Synchronous output and a FOLLOWER output. 1. Power down LTC6951 (PDALL=1)
FOLLOWER Output 2. Power down LTC6954 (PDALL=1)
Dy=DFY MFDY (5) Resynchronization (post power-down):
DDelta(FStoFOLLOWER)=Dx Dy (6) 1. Power up LTC6954 (PDALL=0)
where: 2. Power up LTC6951 (PDALL=0)
c: speed of light (m/s) 3. Send EZSync pulse
DFSX: LTC6951 Follower-Synchronous delay (s)
Expandable Solution
DFY: FOLLOWER delay (s)
EZSync solutions are infinitely expandable. As shown in
Dx: desired delay of Follower-Synchronous output Figure6 the EZSync design example can be expanded by
with respect to a FOLLOWER output when Dy=0. Dx adding fanout buffers to distribute additional clocks. The
is the delay value input for the LTC6951Wizard tool in remainder of this section provides considerations when
Figure2. selecting a fanout buffer, the fanout buffer register settings
Dy: desired delay of FOLLOWER output with respect to in Figure6 and comments regarding further expansion.
Follower-Synchronous output when Dx=0. The fanout buffer in Figure6 does not require an EZSync
DDelta(FStoFOLLOWER): desired delta delay between pulse. Therefore the fanout buffer does not need to be
CONTROLLER and FOLLOWER outputs, in terms of an EZSync device. However, the fanout buffer must be
the CONTROLLER delay settings. capable of accepting a DC-coupled input from an EZSync
CONTROLLER and driving a DC-coupled input to an EZSync
dX: signal delay, electrical trace length(s)
FOLLOWER.
fPD: LTC6951 P-Divider output frequency
Each stage of a clock distribution architectures produces
LX: trace length (m) additive jitter. Referring to Equation7, the addition of the
MFDY: LTC6951 Follower-Driver divide value fanout buffer will increase the total jitter.
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Application Note 161
3.3V 5V
10
0.47F
56.2
V+ VCP+ VVC0+ CP
BB
1nF 1.5nF 56.2
CMA
CMB LTC6951 68nF
1F CMC EZSync
TB CONTROLLER
1F TUNE
EZSync: SYNCHRONIZATION DISABLED
BVC0 OUT4+
100MHz, CLOCK
OUT4
1F 1F OUT3+
37.5MHz, SYSREF
100MHz OUT3
REF EZSync: FOLLOWER-SYNCHRONOUS
REFERENCE OUT0+
2.4GHz, CLOCK
50 1F OUT0
REF+ OUT1+
OUT1 DC-COUPLED
EZSync: FOLLOWER-DRIVER IN+ LV/CM+
EZSync OUT2+ 100 LV/CM DC-COUPLED
1.2GHz IN+
SYNC PULSE SYNC OUT2 LTC6954-1 #1
WIDTH 1ms IN PECL0+ 100 EZSync FOLLOWER
1.2GHz
PECL0
IN M0 = /4 OUT0+
FANOUT PECL1+ VCC DLY0 = 0 OUT0 300MHz, CLOCK
EZSync BUFFER PECL1 10k
OUT0SEL
SYNC PULSE SKEW PECL2+ OUT1+
10k M1 = /32
BETWEEN PARTS 10s PECL2 OUT1SEL OUT1 37.5MHz, SYSREF
DLY1 = 2
10k
PECL3+ OUT2SEL OUT2+
M2 = /4
LTC6950 PECL3 OUT2 300MHz, CLOCK
DLY2 = 0
SYNC
DC-COUPLED
IN+ LTC6954-1 #2
EZSync FOLLOWER
1.2GHz 100
OUT0+
IN M0 = /32
VCC DLY0 = 2 OUT0 37.5MHz, SYSREF
10k
OUT0SEL
OUT1+
10k M1 = /4
OUT1SEL OUT1 300MHz, CLOCK
DLY1 = 0
10k
OUT2SEL OUT2+
M2 = /32
SYNC OUT2 37.5MHz, SYSREF
DLY2 = 2
DC-COUPLED
IN+ LTC6954-1 #3
1.2GHz 100 EZSync FOLLOWER
IN M0 = /4 OUT0+
VCC DLY0 = 0 OUT0 300MHz, CLOCK
10k
OUT0SEL
OUT1+
10k M1 = /32
OUT1SEL OUT1 37.5MHz, SYSREF
DLY1 = 2
10k
OUT2SEL OUT2+
M2 = /4
SYNC OUT2 300MHz, CLOCK
DLY2 = 0
DC-COUPLED
IN+ LTC6954-1 #4
EZSync FOLLOWER
1.2GHz 100
OUT0+
IN M0 = /32
VCC DLY0 = 2 OUT0 37.5MHz, SYSREF
10k
OUT0SEL
OUT1+
10k M1 = /4
OUT1SEL OUT1 300MHz, CLOCK
DLY1 = 0
10k
OUT2SEL OUT2+
M2 = /32
SYNC OUT2 37.5MHz, SYSREF
DLY2 = 2
AN161 F06
The LTC6950 in Stage 1 is set to distribution only mode, All other registers setting can be set to 0.
by powering down the PLL circuitry (PDPLL = 1) and For further expansion it is possible to choose larger fanout
connecting the Follower-Driver Signal to the LTC6950 buffers or add additional fanout buffer stages. When
VCO input. Below is a summary of the LTC6950 register designing a multi-stage clock distribution network, take
settings for Figure6: into account the additive properties of
SM1[5]=SM2[5]=0x20 channel to channel skew
PDPLL=1
IBIAS0=IBIAS1=IBIAS2=IBIAS3=1 additive jitter (Equation7)
M0=M1=M2=M3=M4=1
PD_DIV4=1
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Application Note 161
BVC0 OUT4+
250MHz, CLOCK
OUT4
1F OUT3+
250MHz, CLOCK
OUT3
REF
OUT0+
1GHz, CLOCK
100 1F OUT0
REF+ OUT1+
1GHz, CLOCK
OUT1
REFERENCE DISTRIBUTION OUT2+
250MHz, CLOCK
LTC6954-4 SYNC OUT2
1F 1F OUT0+ 3.3V 5V
100MHz IN+ 10
REFERENCE
/1 OUT0 0.47F
1F 56.2
50 OUT1+ V+ VCP+ VVC0+ CP
BB
IN
/1 OUT1 1nF 1.5nF 56.2
CMA
VCC 10k OUT2+ CMB LTC6951 #2 68nF
OUT0SEL /1 OUT2 1F CMC
10k TB
OUT1SEL 1F TUNE
10k
OUT2SEL BVC0 OUT4+
250MHz, CLOCK
OUT4
1F OUT3+
CK CK 250MHz, CLOCK
OUT3
SYNC REF
D Q D Q OUT0+
PULSE 1GHz, CLOCK
100 1F OUT0
LTC6951
OUT1+
REF INPUT REF+ 1GHz, CLOCK
OUT1
LTC6951
SYNC PULSE OUT2+
250MHz, CLOCK
SYNC TO REF TIMING SYNC OUT2
SYNC HELD HIGH A MINIMUM OF 1ms AN161 F07
ParallelSync Design Overview known time is useful in systems that require known and
ParallelSync is a method to synchronize multiple LTC6951s precise initial placement of clock edges.
running in parallel driven by a common reference clock In Figure7, the LTC6954-4 is the common reference clock
fanout buffer network. Synchronization is achieved through fanout network. The LTC6954-4 was selected to configure
a common reference aligned sync signal. OUT0 and OUT1 as LVDS signals to the LTC6951 refer-
ence inputs. The LTC6954 LVDS outputs optimize power
Synchronizing the LTC6951 outputs in Figure7 involves
consumption and LTC9651 performance when compared
sending a common sync signal that meets setup and hold
to the LTC6954's PECL and CMOS options. In addition,
time requirements to the common reference signal. This
OUT2 can be configured as a CMOS signal to drive the D
architecture provides the ability to synchronize all LTC6951
flip-flop circuitry. The LTC6954 OUT2- CMOS output was
outputs with a known latency to the sync signals falling
selected, instead of the OUT2+ CMOS output, because
edge. The ability to synchronize all LTC6951 outputs at a
OUT2- can be inverted which adds some SYNC to REF
timing flexibility.
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Application Note 161
The section titled ParallelSync Design Rules summarizes LTC6951 Setup
the ParallelSync design rules. The section titled Paral- Based on the ParallelSync Design Rules and the above
lelSync Design Example 1 section provides the design design inputs the following steps provide input conditions
process used to develop the block diagram in Figure7. For for the LTC6951Wizard.
a comparison of synchronization methods, this example
mirrors the frequency plan of the EZParallelSync Design Step 1: Design input: assign output frequencies to optimize
Example. Layout Recommendations discusses matching the LTC6951 fPFD for low jitter.
line lengths to minimize skew between parts. The section ParallelSyncs Design Rule 1 sets RAO=1, making OUT0
titled Synchronization Routines, provides initial power-up, part of the PLL feedback loop. As a result OUT0 affects
power-down and resynchronization sequences. The Ex- the LTC6951 PLLs PFD frequency (fPFD). Maximizing the
pandable Solution section discusses how the block diagram LTC6951 fPFD allows for a wider loop bandwidth and as a
in Figure7 can expand to support more LTC6951 devices. result optimal jitter performance. For more details, refer
ParallelSync Design example 2 provides the DC2226 to the LTC6951 data sheet sections Reference Source
JESD204B frequency plan. The DC2226 is a demo board Considerations and In-Band Output Phase Noise. The
that includes the LTC6951 and two JESD ADCs (LTC2123). LTC6951 maximum fPFD frequency is 100MHz.
LTC6951 ParallelSync Design Rules Referring to the LTC6951 data sheet, Equations8 and 9
can be derived when RAO6951=1.
1. LTC6951 register settings:
f6951.OUT0
a. RAO=1 (enabled) f6951.PFD = (8)
NDIV6951
b. SN=1
fREF
c. SR=1 f6951.PFD = (9)
RDIV6951
2. Meet LTC6951 data sheet SYNC to REF setup and hold
times. Equations8 and 9 can be rearranged as follows:
f6951.OUT0 NDIV6951
ParallelSync Design Example 1 = (10)
fREF RDIV6951
This design example will use the LTC6951Wizard to aid in
the design process. Download LTC6951Wizard at http:// Substituting the desired output clock frequencies and
www.linear.com/LTC6951Wizard. known fREF=100MHz into Equation45, determine the
least common multiple for NDIV and RDIV. Then use
This example assumes the following list of design inputs.
Equations8 and 9 to determine fPFD.
Reference
If f6951.OUT0=250MHz:
fREF=100MHz
LTC6951s 250MHz/100MHz=NDIV6951/RDIV6951
Four 1GHz clock signals NDIV6951=5
Six 250MHz clock signals
RDIV=1
RDIV6951=2
RAO=1 fPFD=50MHz
Delay Align LTC6951 outputs rising edge to LTC6951 reference
settings input rising edge.
If f6951.OUT0=1GHz:
Performance Optimization Request 1GHz/100MHz=NDIV6951/RDIV6951
Design for low jitter.
NDIV6951=10
Minimize the output skew between the LTC6951#1 and LTC6952#2
RDIV6951=1
fPFD=100MHz
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Application Note 161
Assigning f6951.OUT0 to 1GHz allows for the largest fPFD LTC6951Wizard
and as a result minimizes the LTC6951 output jitter.
This section demonstrates the LTC6951Wizards ability to
OUT4 is an LVDS output with an 800MHz maximum out- ease the register setting creation and loop filter design for
put frequency and higher jitter than the other LTC6951 the LTC6951. Under the LTC6951Wizards Help Menu a
CML outputs. The rest of the output frequencies can be Help Guide is provided that will aid in understanding the
assigned as desired. operations performed in this section.
f6951#1.OUT0=f6951#2.OUT0=1GHz The values calculated in Steps 1-3 and conditions provided
f6951#1.OUT1=f6951#2.OUT1=1GHz at the start of this design example are summarized below
f6951#1.OUT2=f6951#2.OUT2=250MHz for a quick reference. These values will be used for inputs
f6951#1.OUT3=f6951#2.OUT3=250MHz to the LTC6951Wizard to calculate the register settings and
f6951#1.OUT4=f6951#2.OUT4=250MHz loop filter values for both LTC6951s in this design example.
Note: The EZParallelSync Design Example uses the same LTC6951Wizard inputs for Figure9:
output frequencies as this ParallelSync Design Example1. f6951.REF=100MHz
However, because EZParallelSync Design Rule 1 limits f6951.OUT0=1GHz
OUT0s frequency selection a smaller fPFD (50MHz) was f6951.OUT1=1GHz
used. The smaller fPFD resulted in the EZParallelSync f6951.OUT2=250MHz
example having ~10fs degraded jitter performance when f6951.OUT3=250MHz
compared to this example. The frequencies in these two
f6951.OUT4=250MHz
examples were chosen specifically to highlight this dif-
I6951.CP=11.2mA
ference. Depending on the desired reference and output
NDIV6951=10
frequencies, differences in fPFD between these two syn-
RDIV6951=1
chronization methods may or may not result. This note
FILT6951=0
is directed at the LTC6951, as other Linear Technology
PLL/VCOs may not have the LTC6951s pre-scalar divider RAO6951=1
architecture. As a result the LTC6951 EZParallelSync Design Figures9 and 10 provide the remaining steps necessary
rule #1 may not apply to other PLL/VCOs. to complete the LTC6951 portion of this design. Several
Step 2: Design input: optimize the LTC6951 charge pump steps in these Figures9 and 10 require the following ad-
current for low jitter. ditional information.
Based on the LTC6951 data sheet the best jitter performance Importing Reference Noise
is obtained by maximizing the LTC6951 ICP current. Refer to Appendix: Model Reference Noise for
LTC6951Wizard Simulations, which describes how to
ICLK6951.CP=11.2mA
import reference noise into the LTC6951Wizard and the
Step 3: Design input: minimize the output skew perfor- impact of reference noise on loop filter calculations and
mance between the LTC6951#1 and LTC6952#2. output noise simulations. Example 1 in the appendix cre-
The LTC6951 device to device skew is best when the ates the reference noise profile for this example.
LTC6951 register value FILT=0.
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Application Note 161
Delay setting: DLYX BITS SYNCENX Bits
For this example, the request was made to align the rising Ensure the LTC6951 SYNCENX bits are set to a 1 for all
edge of the LTC6951 outputs with the rising edge of the signals that require synchronization. Refer to Figure 9,
LTC6951 reference input. The LTC6951 Wizard automati- Step 2b.
cally calculates the DLYX bits based off of Equation11.
LTC6951 OINV Bit
Figure9, step 2b sets the Delay value=0. A LTC6951Wizazd
Figure9, step 6 sets the OINVX values for each output.
Delay value=0 forces the LTC6951Wizard to calculate the
Figure8 provides a recommendation for OINVX settings
LTC6951 DLYX settings to align the LTC6951 output and
based on schematic connections to the device being clock.
reference input rising edges. Figure10 shows the DLYX
In this example all LTC6951 outputs will use the Standard
bits=2 based off the wizard calculation. Figure11 shows
OUTX Connection, setting OINVX=0 (not inverted).
that the LTC6951 output and reference inputs rising edges
are aligned.
STANDARD OUTX CONNECTION
Solving Equation11 for Dx (DLYX) from the values pro-
OUTPUT INVERT OUTX+
vided below match the LTC6951Wizard Delay results in CLK+
OINVX 100
Figures10 and 11. OUTX
CLK
LTC6951
18
Dx = Dxi+ CEILING N M0 18 (11) SET OINVX = 0
N M0
HARDWARE INVERTED OUTX CONNECTION
M0=8
18 Figure8. LTC6951 OINVX STATE
Dx = 0 + CEILING 2 10 18
10 2
Loop Filter Selection
Dx=2 (DLYX delay settings) Figure9s step 11 selected Filter 2. Through experimenta-
tion Filter 2 was found to be the best option to optimize
performance and board space.
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Application Note 161
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Application Note 161
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Application Note 161
1 RDIV 20 PDIV
17. Select Scope Plot CYCLE CYCLES
18 PDIV
CYCLES
2 PDIV
CYCLES
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Application Note 161
LTC6954 Setup STANDARD REFERENCE CONNECTION
Step 4: Design input: minimize the output skew perfor- DELAY DIVIDE OUTX+
REF+
mance between the LTC6951#1 and LTC6952#2. REFERENCE
INPUT
OINVX /1 100
OUTX
REF
Skew in reference signals will result in skew between LTC6954-4 LTC6951
With ParallelSync, the LTC6951 outputs are phase aligned DELAY DIVIDE OUTX+
REF+
to the LTC6951s internal reference dividers output. As REFERENCE
OINVX /1 100
INPUT
a result, a fanout buffer can be used for reference distri- OUTX
REF
LTC6954-4
bution. In this example the LTC6954 was chosen for the LTC6951
M06954=1
SYNC TO REF TIMING CIRCUIT
M16954=1
DELAY DIVIDE OUTX+
M26954=1 REFERENCE
INPUT
OINVX /1
OUTX
SYNC
According to the LTC6954 data sheet, best skew per- LTC6954-4 LTC6951
For this example, both LTC6951 reference inputs can Figure12. Reference Distribution Connection
use Figure12s Hardware Inverted Reference Connection
with a LTC6954 divide value equal to 1. Figure12s Sync
to Ref Timing Circuit should use a divide value of 1. It is
also recommended to use the LTC6954 OUTX- CMOS
output, which has an output invert bit, for the Sync to
Ref Timing Circuit.
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Application Note 161
Step 6: LTC6954 settings summarized: Layout Recommendations
OUTXSEL Pin Settings To minimize LTC6951 output skew match electrical
OUT0SEL=VCC (LVDS) trace lengths as shown in Equations12 and 13 (refer to
OUT1SEL=VCC (LVDS) Figure13).
OUT2SEL=GND (CMOS) LREF#1=LREF#2 (12)
Register Settings L#1.OUTX=L#2.OUTX (13)
When all LTC6954 divide values equal 1, the LTC6954 DLYX
and SYNCEN settings have no effect phase relationship LREF#1 L#1.OUT4
CLK+
and can be set to any value. REF
REF+
OUT4+
OUT4 CLK
SYNCEN06954=1 OUT3+
OUT3 L#1.OUT3
M06954=1 REFIN OUT0+ +
LTC6951 #1 OUT0 L#1.OUT0
DEL06954=0 OUT0 OUT0
OUT1+
PDIV06954=0 LTC6954
OUT1+ OUT1 L#1.OUT1
OUT1 CS
PDOUT06954=0 SCLK OUT2+
L#1.OUT2
OUT2+ SDATA OUT2
SYNCEN16954=1 OUT2
M26954=1
L#2.OUT4
DEL16954=0 REF OUT4+ CLK+
REF+ OUT4 CLK
PDIV16954=0 LREF#2
OUT3+
PDOUT16954=0 OUT3 L#2.OUT3
+
LTC6951 #2 OUT0
SYNCEN26954=1 OUT0 L#2.OUT0
M26954=1 OUT1+
OUT1 L#2.OUT1
CS
DEL26954=0 SCLK OUT2+
OUT2 L#2.OUT2
PDIV26954=0 SDATA
AN161 F31
PDOUT26954=0
CMSINV26954=0 Figure13. Trace Length Matching
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Application Note 161
Synchronization Routines When R>1
On initial power-up: REFCYCLES=R Ceiling(1ms fREF/R) +1 (14)
1. Program LTC6954 and LTC6951 SPI registers Sync Pulse Width=REFCYCLES/fREF (15)
2. If MX6954 > 1, Toggle LTC6954 SYNC pin (minimum Refer to the LTC6951 data sheet for more details.
1ms)
Expandable Solution
3. Wait for LTC6951 bias voltages to stabilize
The ParallelSync solution is infinitely expandable. As
4. Calibrate all LTC6951 VCOs
shown in Figure 14 the ParallelSync design example 1
5. Send SYNC pulse to LTC6951 Sync pins (see LTC6951 can be repeated by adding an additional fanout buffer to
SYNC Pulse Width section) distribute the reference.
Power-down: Distributing a reference aligned synchronization signal in
1. Power down LTC6951 (PDALL=1) a multi-stage fanout architecture across multiple daugh-
ter cards is an additional challenge with the ParallelSync
2. Power down LTC6954 (PDALL=1) architecture. Each stage in the reference fanout network
Resynchronization(post power-down): has a propagation delay that should be accounted for.
Figure14 accounts for propagation delays by retiming the
1. Power Up LTC6954 (PDALL=0) sync signal in both reference distribution stages.
2. Power Up LTC6951 (PDALL=0) The LTC6950 in Stage 1 is set to distribution only mode,
3. If MX6954 > 1, Toggle LTC6954 SYNC pin (minimum by powering down the PLL circuitry (PDPLL = 1) and
1ms) connecting the reference to the LTC6950 VCO input. It
is also recommended to use the LTC6950 LVCM CMOS
4. Send SYNC pulse to LTC6951 Sync pins (see LTC6951
output, which has an output invert bit, for the Sync to Ref
SYNC Pulse Width section)
timing circuit.
LTC6951 Sync Pulse Width Below is a summary of the LTC6950 register settings for
The requirements for the sync pulse width depend on the Figure14:
LTC6951 Rdivider setting. When the LTC6951 internal SM1[5]=SM2[5]=0x20
reference divider equals 1, the latency from the reference PDPLL=1
input to any output will be consistent. In this configuration IBIAS0=IBIAS1=IBIAS2=IBIAS3=1
the sync pulse width should be greater than 1ms. M0=M1=M2=M3=M4=1
When R=1 All other registers setting can be set to 0.
Sync Pulse Width > 1ms (12) For further expansion it is possible to choose larger fanout
When the LTC6951 internal reference divider is > 1, the buffers in Stages 1 or 2 and/or cascade additional reference
latency from the reference input to any output has R dif- distribution stages between Stage 1 and Stage 2. When
ferent possibilities depending on where SYNC falls relative designing a multi-stage reference distribution network,
to R DIV. By creating a SYNC pulse exactly REFCYCLES take into account the additive properties of
wide, all outputs will begin with the same latency to the channel to channel skew
reference input every time a synchronization event occurs.
Equations14 and 15 calculate the SYNC pulse width that noise floor at frequency offsets less than the LTC6951
allows for consistent latency, when R > 1. loop filters pass-band.
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Application Note 161
3.3V 5V
10
0.47F
56.2
V+ VCP+ VVC0+ CP
BB
1nF 1.5nF 56.2
CMA
CMB LTC6951 #1 68nF
1F CMC
TB
1F TUNE
BVC0 OUT4+
250MHz, CLOCK
OUT4
1F OUT3+
250MHz, CLOCK
OUT3
REF
OUT0+
1GHz, CLOCK
100 1F OUT0
REF+ OUT1+
1GHz, CLOCK
OUT1
STAGE 2 OUT2+
REFERENCE DISTRIBUTION 250MHz, CLOCK
SYNC OUT2
STAGE 1
REFERENCE DISTRIBUTION LTC6954-4
3.3V 5V
OUT0+ 10
PECL0+ TO CARD #1 IN+
100MHz /1 OUT0 0.47F
REFERENCE
/1 PECL0 56.2
100
OUT1+ V+ VCP+ VVC0+ CP
BB
PECL1+ TO CARD #2 IN
/1 OUT1 1nF 1.5nF 56.2
/1 PECL1 CMA
VCC 10k OUT2+ CMB LTC6951 #2 68nF
PECL2+ TO CARD #3
OUT0SEL 1F
/1 OUT2 CMC
/1 PECL2 10k TB
OUT0SEL 1F TUNE
PECL4+ TO CARD #4 10k
/1 PECL4 OUT2SEL BVC0 OUT4+
250MHz, CLOCK
OUT4
LTC6950 LVCM+ 1F
DISTRIBUTION OUT3+
ONLY MODE LVCM OUT3 250MHz, CLOCK
REF
CK CK OUT0+
100 1F 1GHz, CLOCK
TO CARD #1 OUT0
D Q D Q
CK CK TO CARD #2 REF+ OUT1+
1GHz, CLOCK
SYNC SYNC OUT1
D Q D Q TO CARD #3
PULSE DISTRIBUTION
OUT2+
TO CARD #4 SYNC 250MHz, CLOCK
OUT2
DAUGHTER CARD #1
DAUGHTER CARD #2
DAUGHTER CARD #3
DAUGHTER CARD #4
AN161 F14
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Application Note 161
BVC0 OUT4+
125MHz, FPGA CLOCK
OUT4
1F OUT3+
15.625MHz, ADC2 SYSREF
OUT3
REF
OUT0+
2GHz, MUTED
100 1F OUT0
REF+ OUT1+
250MHz, ADC2 CLOCK
OUT1
OUT2+
REFERENCE DISTRIBUTION PWRDN
SYNC OUT2
LTC6954-4
3.3V 5V
1F 1F OUT0+ 10
100MHz IN+
REFERENCE
/1 OUT0 470nF
1F 56.2
50 OUT1+ V+ VCP+ VVC0+ CP
BB
IN
/1 OUT1 1nF 1.5nF 56.2
CMA
VCC 10k OUT2+ CMB LTC6951 #1 68nF
OUT0SEL /1 OUT2 1F CMC U13
10k TB
OUT0SEL 1F TUNE
10k
OUT2SEL BVC0 OUT4+
15.625MHz, FPGA SYSREF
OUT4
1F OUT3+
CK CK 15.625MHz, ADC1 SYSREF
OUT3
SYNC REF
D Q D Q OUT0+
PULSE 2GHz, MUTED
100 1F OUT0
LTC6951
OUT1+
REF INPUT REF+ 250MHz, ADC1 CLOCK
OUT1
LTC6951
SYNC PULSE OUT2+
PWRDN
SYNC TO REF TIMING SYNC OUT2
SYNC HELD HIGH A MINIMUM OF 1ms AN161 F15
JESD204B ParallelSync Design Overview This example provides CLOCK and SYSREF signals to two
Figure 15 demonstrates the LTC6951 in JESD204B ADCs and one FPGA. The selection of LTC6951 CLOCK and
subclass 1 ParallelSync configuration. The frequencies SYSREF output pins were selected to ease board layout
chosen mirror that of the DC2226 JESD204B subclass1 and to optimize performance.
demonstration board which includes two LTC2123
Board Layout
JESD204B ADCs.
On the DC2226, an LTC6951 was placed next to each ADC
The reference and synchronization sections of this design
to minimize the ADC CLOCK and SYSREF trace lengths.
are identical to the ParallelSync Design Example 1. Design
Minimizing the trace lengths between the LTC6951 and
information for these sections will refer back to the relevant
the ADC has the effect of increasing the reference trace
section in ParallelSync Design Example 1.
length between the LTC6954 and the LTC6951, or vice
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Application Note 161
versa. Longer trace lengths typically increase the prob- The remaining three CML LTC6951 outputs, OUT1, OUT2,
ability of unwanted signals or noise coupling onto the and OUT3 are identical in operation and performance. A
signal of interest. CML output was chosen to drive the ADC Clock inputs,
Unwanted noise or signals coupling onto either the because the LTC6951 CML outputs have lower jitter than
LTC6951 reference input or LTC6951 clock output can the LTC6951 OUT4 LVDS output. OUT1 and OUT3 were
create random or deterministic clock jitter, respectively. chosen to drive the ADC CLOCK and SYSREF due to layout
Random ADC clock jitter degrades the ADC SNR, where considerations. OUT2 is closer to the LTC6951 reference
deterministic jitter degrades the ADC SFDR. For this reason input. Since not all outputs were required in this example,
the LTC6951 reference input and LTC6951 clock outputs OUT2 was powered down to limit board coupling concerns
are both critical signals. However, when making trade-offs between OUT2 and the LTC6951 reference input.
on trace length, it is recommended to treat the ADC clock The section titled ParallelSync Design Example 2 section
signal as the more sensitive signal for the following reasons: provides the design process used to develop the block
Filtering: LTC6951 reference inputs signals are naturally diagram in Figure15. Layout Recommendations discusses
filtered by the existing narrowband PLL loop filter. The matching line lengths to minimize skew between parts.
PLL loop filter does not affect LTC6951 output to output The section titled Synchronization Routines, provides
skew. Conversely, unwanted signals coupling onto an ADC initial power-up, power-down and resynchronization
clock can only be removed by adding a clock filter, which sequences. The Expandable Solution section discusses
increases BOM cost and degrades clock to clock skew. how the block diagram in Figure7 can expand to support
more LTC6951 devices.
Impedance Matching: PLL reference frequencies are
typically slower than ADC clock frequencies. Slower fre- ParallelSync Design Example 2
quencies ease impedance matching and signal integrity
This design example will use the LTC6951Wizard to aid in
concerns.
the design process. Download LTC6951Wizard at http://
LTC6951 Output Selection www.linear.com/LTC6951Wizard.
With ParallelSync, The LTC6951 OUT0 path is part of the This example assumes the following list of design inputs.
PLL feedback loop (RAO=1), which disables OUT0s delay Reference
functionality. Since not all LTC6951 outputs were needed fREF 100MHz
and OUT0 delay feature is disabled, the OUT0 output buf- LTC6951s
fer is powered down. The OUT0 divider network remains f6951#1.OUT1=250MHz
enabled to support the PLL feedback loop. Refer to the f6951#1.OUT3=15.625MHz
LTC6951 data sheet for more information regarding how f6951#1.OUT4=15.625MHz
the RAO bit affects the OUT0 operation. In addition, by f6951#2.OUT1=250MHz
not selecting OUT0 as a device clock this allowed for more f6951#2.OUT3=15.625MHz
flexibility in selecting the LTC6951 fPFD. Careful selection of f6951#2.OUT4=125MHz
fPFD optimizes the LTC6951 jitter performance. This point RAO=1
will be discussed more in the design example. Delay settings Best performance
The LTC6951s OUT4 is an LVDS output. The other four Performance Optimization Request
LTC6951 outputs are CML outputs. LTC6951#2s and Design for low jitter.
LTC6951#1s OUT4 pins were selected for the FPGA Minimize the output skew between the LTC6951#1 and LTC6952#2
CLOCK and SYSREF signal, because the FPGA accepted
LVDS signal levels.
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Application Note 161
LTC6951 Setup to the LTC6951Wizard to calculate the register settings and
Based on the ParallelSync Design Rules and the above loop filter values for both LTC6951s in this design example.
design inputs, the following steps provide input conditions LTC6951Wizard inputs for Figures 18 and19:
for the LTC6951Wizard.
f6951.REF=100MHz
Step 1: Design input: determine OUT0s frequency to f6951#1.OUT0=PwrDown
optimize the LTC6951 fPFD for low jitter. f6951#1.OUT1=250MHz
ParallelSyncs Design Rule 1 sets RAO=1, making OUT0 f6951#1.OUT3=15.625MHz
part of the PLL feedback loop. As a result OUT0 affects f6951#1.OUT4=15.625MHz
the LTC6951 PLLs PFD frequency (fPFD). Maximizing the f6951#2.OUT0=PwrDown
LTC6951 fPFD allows for a wider loop bandwidth and as a f6951#2.OUT1=250MHz
result optimal jitter performance. For more details, refer f6951#2.OUT3=15.625MHz
to the LTC6951 data sheet sections Reference Source f6951#2.OUT4=125MHz
Considerations and In-Band Output Phase Noise. The
LTC6951 specified maximum fPFD frequency is 100MHz. FILT6951=0
RAO6951=1
The LTC6951Wizard automatically calculates the optimal
OUT0 frequency in Figures18 and 20, when PwrDown is Figures18 to 24 provide the remaining steps necessary
chosen for OUT0. to complete the LTC6951 portion of this design. Several
steps in these figures require the following additional
f6951#1.OUT0=PwrDown information.
f6951#2.OUT0=PwrDown
Importing Reference Noise
Step 2: Design input: optimize the LTC6951 charge pump
current for low jitter. Refer to Appendix: Model Reference Noise for
LTC6951Wizard Simulations, which describes how to
Refer to Step 2 in the ParallelSync Design Example 1 import reference noise into the LTC6951Wizard and the
Step 3: Design input: minimize the output skew perfor- impact of reference noise on loop filter calculations and
mance between the LTC6951#1 and LTC6952#2. output noise simulations. Example 1 in the appendix cre-
ates the reference noise profile for this example.
Refer to Step 3 in the ParallelSync Design Example 1
Delay setting: CLOCK DLYX Bits
LTC6951Wizard For this example, the request was made to set delays
This section demonstrates the LTC6951Wizards ability to values of the LTC6951 outputs for best performance.
ease the register setting creation and loop filter design for Less than optimal performance can result if the reference
the LTC6951. Under the LTC6951Wizards Help Menu a frequency mixes with an LTC6951 output frequency on
Help Guide is provided that will aid in understanding the the board. An initial attempt to avoid mixing produce will
operations performed in this section. set the LTC6951 outputs delays so that the LTC6951 input
reference edges and the LTC6951 output clock edges oc-
The values calculated in Steps 1-3 and conditions provided
cur at different times.
at the start of this design example are summarized below
for a quick reference. These values will be used for inputs
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Application Note 161
Step 3a: Determine the LTC6951 PDIV cycles that coin- REF_CYCLE=20 PDIV cycles
cide with the LTC6951 OUT1s 250MHz clock rising and
REF Rising Edge=20 PDIV Cycles y (20)
falling edges.
REF Falling Edge=20 PDIV Cycles y + 10 (21)
fPIV
Clock _CYCLE = (16) Step 3c: Determine the LTC6951 PDIV cycles that coincide
fOUT1
with the LTC6951 OUT3s 250MHz SYSREF rising edge.
2GHz fPIV
Clock _CYCLE =
250MHz SYSREF _CYCLE = (22)
fREF
Clock _CYCLE = 8 PDIV Cycles
2GHz
SYSREF _CYCLE =
Clock Rising Edge=8 PDIV Cycles x + Dxi (17) 15.625MHz
Clock Falling Edge=8 PDIV Cycles x + 4 + Dxi (18) SYSREF_CYCLE=128 PDIV cycles
Where, SYSREF Rising Edge=128 PDIV Cycles x + Dxi (23)
x is any integer, To maximize JESD204B SYSREF to CLOCK setup and hold
times the SYSREF signals rising edge should occur on the
Dxi adjusted delay setting, when Dxi=0 the output
falling edge of the CLOCK signal.
aligns to the reference.
Step 3d: Determine Dxi by plotting results as shown below
Step 3b: Determine the number of LTC6951 PDIV cycles
in Figure16
with respect to LTC6951 Reference input frequency.
Dxi=1 or Dxi=3 meet the desired criteria of not having the
fPIV
REF _CYCLE = clock edges coincide with the reference edges. A Dxi=3
fREF for the Clock and Dxi=7 for the SYSREF were chosen for
(19)
Step 10 in Figure20.
2GHz
REF _CYCLE =
100MHz
PDIV CYCLES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
REF EDGES
CLK EDGES (Dxi=0)
CLK EDGES (Dxi=1)
CLK EDGES (Dxi=2)
CLK EDGES (Dxi=3)
SYSREF EDGES (Dxi=7)
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Application Note 161
Step 3e: Verify the LTC6951Wizard DLYx calculation. SYNCENX Bits
The LTC6951 Wizard automatically calculates the DLYX Ensure the LTC6951 SYNCENX bits are set to a 1 for all
bits based off of Equation24. This same equation is found signals that require synchronization. Refer to Figure18,
in the LTC6951 data sheet. Step 2b.
Solving Equation24 for Dx (DLYX) from the values provided LTC6951 OINV Bit
below match the LTC6951Wizard Delay results in Figure22.
Figure20, step 13 sets the OINVX values for each output.
18 Figure17 provides a recommendation for OINVX settings
Dx = Dxi+ CEILING N M0 18 (24)
N M0 based on schematic connections to the device being clock.
In this example all LTC6951 outputs will use the Standard
Dx=DLYx value in LTC6951 SPI map OUTX Connection, setting OINVX=0 (not inverted).
Dxi=adjusted delay setting, a 0 aligns output rising
edge to reference rising edge STANDARD OUTX CONNECTION
Dxi=3 OUTX+
OUTPUT INVERT CLK+
18 OINVX 100
Dx = 3+ CEILING 20 1 18 OUTX
CLK
20 1 LTC6951
SET OINVX = 1 AN161 F08
Dxi=7
18 Loop Filter Selection
Dx = 7 + CEILING 20 1 18
20 1 Figure21s step 18 selected Filter 2. Through experimenta-
tion Filter 2 was found to be the best option to optimize
Dx=9 (SYSREF DLYX delay settings) performance and board space.
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Application Note 161
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Application Note 161
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Application Note 161
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Application Note 161
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AN161-29
Application Note 161
1 RDIV 20 PDIV
23. Select Scope Plot CYCLE CYCLES
18 PDIV
CYCLES
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Application Note 161
LTC6954 Setup Power-down after JESD204b alignment sequence is
Step 4: Design input: minimize the output skew perfor- complete:
mance between the LTC6951#1 and LTC6952#2. 1. Power down LTC6951 SYSREF OUTX (MCX=2)
Step 5: Verify LTC6954 output to LTC6951 connection. (NOTE: power down LTC6951 output, but leave LTC6951
Step 6: LTC6954 settings summarized: output divider enable to avoid resynchronizing all clocks)
1. Program LTC6954 and LTC6951 SPI registers The ParallelSync solution is infinitely expandable, refer
ParallelSync Design Example 1 Section titled Expandable
2. If MX6954 > 1, Toggle LTC6954 SYNC pin (minimum Solution and Figure14 in for more details
1ms)
3. Wait for LTC6951 bias voltages to stabilize
4. Calibrate all LTC6951 VCOs
5. Send SYNC pulse to LTC6951 Sync pins (see LTC6951
SYNC Pulse Width section)
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Application Note 161
BVC0 OUT4+
250MHz, CLOCK
OUT4
1F OUT3+
250MHz, CLOCK
OUT3
REF
OUT0+
250MHz, CLOCK
100 1F OUT0
REF+ OUT1+
1GHz, CLOCK
OUT1
CS
SPI SCLK OUT2+
REFERENCE DISTRIBUTION SYNC 1GHz, CLOCK
SDI OUT2
LTC6954-4
3.3V 5V
1F 1F OUT0+ 10
100MHz IN+
REFERENCE
/2 OUT0 470nF
1F 80.6
50 OUT1+ V+ VCP+ VVC0+ CP
BB
IN
OUT1 1nF 80.6 1.5nF
CMA
VCC 10k OUT2+ CMB LTC6951 #2 68nF
OUT0SEL /2 OUT2 1F CMC
10k TB
OUT2SEL 1F TUNE
EZSync
SYNC PULSE SYNC BVC0 OUT4+
WIDTH 1ms 250MHz, CLOCK
OUT4
1F OUT3+
250MHz, CLOCK
OUT3
REF
OUT0+
250MHz, CLOCK
100 1F OUT0
REF+ OUT1+
1GHz, CLOCK
OUT1
CS
SPI SCLK OUT2+
SYNC 1GHz, CLOCK
SDI OUT2
AN161 F25
EZParallelSync Design Overview phase aligned reference frequencies. The external RDIV
EZParallelSync is a simple way to synchronize multiple allows the LTC6951s internal RDIVs to equal 1. Setting
LTC6951s running in parallel driven by a common refer- the LTC6951 RDIV=1 allows for output phase alignment
ence clock divider/distribution network. Synchronization across multiple LTC6951s to a common reference edge.
is easily achieved through SPI commands. The LTC6951 This architecture provides the ability to synchronize any
SYNC pin can be used in lieu of the SPI command. LTC6951 to any other LTC6951 at any time. As a result
In Figure25, the LTC6954 is the common reference clock if any LTC6951 is not used continuously then the un-
used LTC6951 can be completely powered down. When
divider/distribution network. The LTC6954 acts as an exter-
needed the powered down LTC6951 can be powered up
nal reference divider (RDIV) to provide two LTC6951s with
and resynchronized independently without recalibrating
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Application Note 161
the LTC6951 VCO and without performing a full system EZParallelSync Design Example
clock synchronization. This ability to asynchronously
This design example will use the LTC6951Wizard to aid in
synchronize independent LTC6951 with EZParallelSync
the design process. Download LTC6951Wizard at http://
is also useful in plug and play (hot plug) applications.
www.linear.com/LTC6951Wizard.
This example uses the same fOUT0 and the same fREF for all
This example assumes the following list of design inputs.
LTC6951s. A variant of EZParallelSync is EZ204Sync. The
EZ204Sync Design Example provides an example where Reference
different OUT0 or REF frequencies are used. fREF=100MHz
LTC6951s
The section titled EZParallelSync Design Rules summa-
f6951#1.OUT0=f6951#2.OUT0=250MHz
rizes the EZParallelSync design rules. The section titled
f6951#1.OUT1=f6951#2.OUT1=1GHz
EZParallelSync Design Example section provides the design
f6951#1.OUT2=f6951#2.OUT2=1GHz
process used to develop the block diagram in Figure25.
f6951#1.OUT3=f6951#2.OUT3=250MHz
Layout Recommendations discusses matching line lengths
to minimize skew between parts. The section titled Syn- f6951#1.OUT4=f6951#2.OUT4=250MHz
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Application Note 161
The second design rule states that RDIV6951#1=1 and Since LTC6951#1 and LTC6951#2 have an identical fre-
RAO6951 = 1. Referring to the LTC6951 data sheet the quency plan.
following two equations are provided when RAO6951=1.
NDIV6951#1=NDIV6951#2=5
f6951# 1.REF
f6951# 1.PFD = (27) M06954=M26954=2
RDIV6951# 1
f6951#1.REF=f6951#2.REF=50MHz
f6951# 1.OUT0
f6951# 1.PFD = (28) Step 3: Design Rule 3 verification
NDIV6951# 1
Based on the results from step 2, Design Rule 3 is met.
Referring to the LTC6954 data sheet the following equa- f6951#1.OUT0/f6951#1.REF=f6951#2.OUT0/f 6951#2.REF
tion is provided. Step 4: Design input: optimize the LTC6951 for low jitter.
fREF Based on the LTC6951 data sheet, the jitter performance
f6951# 1.REF = (29)
M0 6954 is obtained by maximizing the fPFD frequency (see Step2)
and maximizing the LTC6951 ICP current.
Since RDIV6951#1=1, Equations27, 28, and 29 can be ICLK6951.CP=11.2mA
rearranged as follows:
Note: The ParallelSync Design Example #1 uses the same
M0 6954 f6951# 1.OUT0
NDIV6951# 1 = (30) output frequencies as this EZParallelSync Design Example.
fREF However, because ParallelSync does not require the low-
est output frequency on OUT0 (EZParallelSync Design
Substituting the known values for fREF = 100MHz and Rule1) a larger fPFD (100MHz) could be obtained. The
f6951#1.OUT0=250MHz into Equation30 results in larger fPFD resulted in the ParallelSync example having
M0 6954 250MHz ~10fs improved jitter performance when compared to
NDIV6951# 1 = (31) this example. The frequencies in these two examples were
100MHz chosen specifically to highlight this difference. Depending
Which simplifies to on the desired reference and output frequencies, differences
in fPFD between these two synchronization methods may
NDIV6951#1=2.5 M06954 (32) or may not result. This note is directed at the LTC6951,
Based on the LTC6951 data sheet, to optimize for the as other Linear Technology PLL/VCOs may not have the
lowest jitter possible f6951#1.PFD should be as large as pos- LTC6951s pre-scalar divider architecture. As a result the
sible, which allows for a wider bandwidth loop filter. This LTC6951 EZParallelSync Design rule #1 may not apply to
statement assumes the reference input signal noise level other PLL/VCOs.
is not limiting the LTC6951s in-band noise performance. Step 5: Design input: minimize the output skew perfor-
Therefore, solve Equation32 for the least common integer mance between the LTC6951#1 and LTC6952#2.
multiple for NDIV and M0.
The LTC6951 device to device skew is best when the
NDIV6951#1=5 LTC6951 register value FILT=0.
M06954=2
LTC6951Wizard
Next solve Equation29 and 27.
This section demonstrates the LTC6951Wizards ability to
f6951#1.REF=50MHz ease the register setting creation and loop filter design for
f6951#1.PFD=50MHz the LTC6951. Under the LTC6951Wizards Help Menu a
Help Guide is provided that will aid in understanding the
operations performed in this section.
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Application Note 161
The values calculated in Steps 1 to 5 and conditions pro- 18
vided at the start of this design example are summarized Dx = Dxi+ CEILING N M0 18 (33),
N M0
below for a quick reference. These values will be used
for inputs to the LTC6951Wizard to calculate the register Solving Equation33 from the values shown match the
settings and loop filter values for both LTC6951s in this LTC6951Wizard results, shown in Figures28 and 29.
design example.
Dxi=0 (align to reference)
LTC6951Wizard inputs for Figure27: 18, number of PDIV cycles
f6951.REF=50MHz N= 5
f6951.OUT0=250MHz M0=8
f6951.OUT1=1GHz 18
Dx = 0 + CEILING 5 8 18
f6951.OUT2=1GHz 5 8
f6951.OUT3=250MHz Dx=22 (delay settings)
f6951.OUT4=250MHz
I6951.CP=11.2mA SYNCENX BITS
NDIV6951=5 Ensure the LTC6951 SYNCENX bits are set to a 1 for all
RDIV6951=1 signals that require synchronization. Refer to Figure27,
FILT6951=0 Step 2b.
RAO6951=1
LTC6951 OINV Bit
Figures27 and 28 provide the remaining steps necessary
Figure27, step 7 sets the OINVX values for each output.
to complete the LTC6951 portion of this design. Several
Figure26 provides a recommendation for OINVX settings
steps in Figures27 and 28 require the following additional
based on schematic connections. In this example all
information.
LTC6951 outputs will use the Standard OUTX Connection,
Importing Reference Noise setting OINVX=0 (not inverted).
Refer to Appendix: Model Reference Noise for STANDARD OUTX CONNECTION
ates the reference noise profile for this example. SET OINVX = 0
For this example, the request was made to align the rising OUTPUT INVERT OUTX+
CLK+
edge of the LTC6951 outputs with the rising edge of the OINVX 100
OUTX
LTC6951 reference input. The LTC6951 Wizard automati- LTC6951
CLK
cally calculates the DLYX bits based off of Equation33. SET OINVX = 1 AN161 F08
AN161-35
Application Note 161
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AN161-36
Application Note 161
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AN161-37
Application Note 161
18 PDIV 22 PDIV
CYCLES CYCLES
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AN161-38
Application Note 161
LTC6954 Setup For this example, both reference inputs were required to
Step 6: Design input: minimize the output skew between use Figure30s Hardware Inverted Reference Connection.
the LTC6951#1 and LTC6952#2. Therefore, set DEL06954=DEL26954.
If it is desired to connect LTC6951#1 to Figure30s Standard
The LTC6951 outputs are phase aligned to the reference
Reference Connection and LTC6951#2 to the Hardware
input. Skew in reference signals will result in skew between
Inverted Reference Connection, then the reference inputs
LTC6951s. Therefore, it is recommended to match trace
will be inverted with respect to each other.
lengths on the reference signals during board layout.
To account for this schematic inversion, invert one of the
According to the LTC6954 data sheet best skew per-
formance is obtained when either one of following two LTC6954 output signals by delaying one LTC6954 output
conditions are met: a cycle using the LTC6954 delay bits (see Table C1).
Using the LTC6954 delay registers in this manner is only
Condition 1: all LTC6954 output divider settings equal 1 possible when all LTC6954 divide values are even numbers.
Condition 2: all LTC6954 output divider settings are >1. Table 2. LTC6954 Register Settings, when Schematic Chooses
Different Reference Connections
In Step 2 the LTC6954 was design for optimal outputs LTC6954 Register Settings
skew, since Condition 2 was met. LTC6954 OUTX MX DELX
M06954=2 LTC6951: Standard
Even Number Y*
Reference Connection
M26954=2
LTC6951: Hardware Inverted min (MX )
Even Number + Y*
Step 7: Verify LTC6954 output to LTC6951 connection. Reference Connection 2
It is recommended to choose an identical reference sche- * Y, integer, same value for all DELX
matic from Figure30 for both LTC6951s. This ensures
Step 8: LTC6954 register settings summarized:
both LTC6951 PLLs align to the same reference edge.
SYNCEN06954=1
STANDARD REFERENCE CONNECTION
M06954=2
DELAY DIVIDE OUTX+ DEL06954=0
REF+
REFERENCE
DELX MX 100 PDIV06954=0
INPUT OUTX
LTC6954-4
REF PDOUT06954=0
LTC6951
LT6951 INPUT
PDIV16954=1
SYNCEN26954=1
HARDWARE INVERTED REFERENCE CONNECTION M26954=2
DELAY DIVIDE OUTX+ DEL26954=0
REF+
REFERENCE
DELX MX 100
PDIV26954 =0
INPUT OUTX
REF PDOUT26954=0
LTC6954-4 LTC6951
LT6951 INPUT
AN161 F30
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AN161-39
Application Note 161
Layout Recommendations Power down Idle LTC6951:
To minimize LTC6951 output skew match electrical 1. Power down idle LTC6951 (PDALL=1)
trace lengths as shown in Equations34 and 35 (refer to
2. Power down LTC6954 OUTX connected to idle
Figure31).
LTC6951 (PD_OUTX=1)
LREF#1 =LREF#2 (34) Resynchronization of Idle LTC6951:
L#1.OUTX=L#2.OUTX (35) 1. Power up idle LTC6951 (PDALL=0)
LREF#1
REF OUT4+
L#1.OUT4
CLK+
2. Power up LTC6954 OUT X connected to idle LTC6951
REF+ OUT4 CLK (PD_OUTX=0)
OUT3+
OUT3 L#1.OUT3
3. Toggle LTC6951 SPI SSYNC bit or SYNC pin
REFIN OUT0+ +
LTC6951 #1 OUT0 L#1.OUT0 (minimum 1ms)
OUT0 OUT0
OUT1+
LTC6954
OUT1+
OUT1 CS
OUT1 L#1.OUT1
Expandable Solution
SCLK OUT2+
OUT2+ SDATA OUT2 L#1.OUT2
The EZParallelSync solution is infinitely expandable. As
OUT2
shown in Figure32, the EZParallelSync design example
can be repeated by adding an EZSync CONTROLLER to
L#2.OUT4
REF OUT4+ CLK+ distribute the reference.
REF+ OUT4 CLK
LREF#2
OUT3+
L#2.OUT3
For ease of synchronization, in Figure32 the divide by
OUT3
+ two function was moved from Stage 2 to the LTC6950
LTC6951 #2 OUT0
OUT0 L#2.OUT0
in Stage 1. As a result, Stage 2 can now use a low noise
OUT1+
OUT1 L#2.OUT1 fanout buffer such as the LTC6957.
CS
SCLK
SDATA
OUT2+
OUT2 L#2.OUT2 For further expansion, it is possible to cascade additional
AN161 F31
reference distribution stages between Stage 1 and Stage 2.
When designing a multi-stage reference divider/distribu-
Figure31. Trace Length Matching
tion network, take into account the additive properties of:
Synchronization Routines channel to channel skew
On initial power-up: noise floor at frequency offsets less than the LTC6951
loop filters pass-band. Refer to Appendix: Model Refer-
1. Program LTC6954 and LTC6951 SPI registers
ence Noise for LTC6951Wizard Simulations.
2. Toggle LTC6954 SYNC pin (minimum 1ms)
If some LTC6951s can power down during operation, then
3. Wait for LTC6951 bias voltages to stabilize selecting reference distribution parts with the ability to
4. Calibrate all LTC6951 VCOs power down individual outputs can save additional power.
an161f
AN161-40
Application Note 161
3.3V 5V
10
0.47F
56.2
V+ VCP+ VVC0+ CP
BB
1nF 80.6 1.5nF
CMA
CMB LTC6951 #1 68nF
1F CMC
TB
1F TUNE
BVC0 OUT4+
250MHz, CLOCK
OUT4
1F OUT3+
250MHz, CLOCK
REF OUT3
OUT0+
100 1F 250MHz, CLOCK
OUT0
REF+ OUT1+
1GHz, CLOCK
OUT1
CS
STAGE 2 SPI SCLK OUT2+
STAGE 1 FANOUT BUFFER SYNC 1GHz, CLOCK
SDI OUT2
REFERENCE DIVIDE
ANDDISTRIBUTION LTC6957-2
3.3V 5V
OUT1+ 10
PECL0+ TO CARD #1 IN+
100MHz OUT1 0.47F
REFERENCE
/2 PECL0 56.2
100
OUT2+ V+ VCP+ VVC0+ CP
BB
PECL1+ TO CARD #2 IN
OUT2 1nF 80.6 1.5nF
/2 PECL1 CMA
10k CMB LTC6951 #2 68nF
PECL2+ TO CARD #3
FILTA 1F CMC
/2 PECL2 10k TB
FILTB TUNE
EZSync PECL4+ TO CARD #4 1F
SYNC PULSE SYNC /2 PECL4 BVC0 OUT4+
250MHz, CLOCK
WIDTH 1ms OUT4
LTC6950 LVCM+ 1F
DISTRIBUTION OUT3+
LVCM OUT3
250MHz, CLOCK
ONLY MODE REF
OUT0+
100 1F 250MHz, CLOCK
OUT0
REF+ OUT1+
1GHz, CLOCK
OUT1
CS
SPI SCLK OUT2+
SYNC 1GHz, CLOCK
SDI OUT2
DAUGHTER CARD #1
DAUGHTER CARD #2
DAUGHTER CARD #3
DAUGHTER CARD #4
AN161 F32
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AN161-41
Application Note 161
REF+ OUT1+
15.625MHz, SYSREF
OUT1
CS
SPI
SCLK OUT2+
15.625MHz, SYSREF
SYNC
SDI OUT2
AN161 F33
AN161-42
Application Note 161
if any LTC6951 is not used continuously, then the un- This example assumes the following list of design inputs.
used LTC6951s can be completely powered down. When
Reference
needed, the powered down LTC6951s can be powered up
fREF=100MHz
and resynchronized independently without recalibrating
CLOCK-LTC6951
its VCO and without performing a full system clock syn-
fCLK6951.OUT0=250MHz
chronization. This ability to asynchronously synchronize
fCLK6951.OUT1=1GHz
independent LTC6951s with EZ204Sync is useful for
fCLK6951.OUT2=1GHz
JESD204B subclass 1 applications.
fCLK6951.OUT3=250MHz
The section titled EZ204Sync Design Guidelines sum- fCLK6951.OUT4=250MHz
marizes the EZ204Sync design rules. The section titled RDIV=1
EZ204Sync Design Example section provides the design RAO=1
process used to develop the block diagram in Figure33. SYSREF-LTC6951
Layout Recommendations discusses matching line lengths
fCLK6951.OUT0
to minimize skew between parts. The section titled Syn- fSYS6951.OUTX = (38)
16
chronization Routines provides the initial power-up, power-
down and resynchronization sequences. The Expandable RDIV=1
Solution section discusses how the block diagram in RAO=1
Figure33 can expand to support more LTC6951 devices. Performance Optimization Request
Design CLOCK LTC6951 for low jitter.
EZ204Sync Design Rules Design SYSREF LTC6951 for low power.
Optimize skew between CLOCK LTC6951 to SYSREF LTC6951 outputs.
When compared to ParallelSync, EZ204Sync has the ad-
Part Placement And Routing
ditional design rule that the LTC6951 OUT0 pin is assigned
The LTC6954 and both LTC6951s will be placed on the top side of the
to the lowest output frequency per LTC6951. Refer to the board. For the most direct routing connect:
LTC6951 data sheet for details related to PDIV and RAO. LTC6954 OUTX+ to LTC6951 IN
1. LTC6951 OUT0 pin assigned to the lowest output fre- LTC6954 OUTX to LTC6951 IN+
quency per LTC6951 This creates a reference signal inversion at the LTC6951 inputs.
This design example will use the LTC6951Wizard to aid in The second design rule states that RDIV=1 and RAO=1.
the design process. Download LTC6951Wizard at http:// Referring to the LTC6951 data sheet the following two
www.linear.com/LTC6951Wizard. equations are provided when RAO=1.
fCLK6951.REF
fCLK6951.PFD = (39)
RDIVCLK6951
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Application Note 161
fCLK6951.OUT0 SYSREF LTC6951 Setup
fCLK6951.PFD = (40)
NDIVCLK6951 Step 5: Calculate the SYSREF frequencies, using
Equation38.
Referring to the LTC6954 data sheet, the following equa-
tion is provided. fSYS6951.OUTX=15.625MHz
fCLK6951.REF=50MHz M26954=100MHz/3.125MHz
Step 3: Design input: optimize the CLOCK LTC6951 for M26954=32
low jitter.
Step 7: Design input: optimize the SYSREF LTC6951 for
Based on the LTC6951 data sheet the jitter performance low power.
is obtained by maximizing the LTC6951 ICP current.
SYSREF is only used for the JESD204B alignment rou-
ICLK6951.CP=11.2mA tines and is not a high performance clock. Therefore, the
Step 4: Design input: optimize the skew performance SYSREF LTC6951 can be placed in a lower power mode
between the CLOCK LTC6951 and SYSREF LTC6951. than the CLOCK LTC6951.
The LTC6951 device to device skew is best when the Set ISYS6951.CP=2mA
LTC6951 register value FILT=0.
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AN161-44
Application Note 161
LTC6951Wizard impact of reference noise on loop filter calculations and
This section demonstrates the LTC6951Wizards ability to output noise simulations. Examples 2 & 3 in the appendix
ease the register setting creation and loop filter design for create the reference noise profile for this example.
both the SYSREF LTC6951 and CLOCK LTC6951. Under SYNCENX BITS
the LTC6951Wizards Help Menu a Help Guide is provided
Ensure the CLOCK LTC6951 and SYSREF LTC6951
that will aid in understanding the operations performed
SYNCENX bits are set to a 1 for all signals that require
in this section.
synchronization. Refer to Figure35 Step 2b and Figure36
The values calculated in Steps 1 to 7 and conditions pro- Step 15b.
vided at the start of this design example are summarized
Loop Filter Selection
below for a quick reference.
Figure 35s step 11 selected Filter 1 for the SYSREF
LTC6951Wizard inputs for the SYSREF LTC6951 in
LTC6951. The simplest filter was selected for board space
Figure35
and cost reasons, because SYSREF jitter performance is
fSYS6951.REF=3.125MHz not important.
fSYS6951.OUTX=15.625MHz Figure36s step 24 selected Filter 2 for the CLOCK LTC6951.
ISYS6951.CP=2mA Through experimentation Filter 2 was found to be the best
NDIVSYS6951=5 option to optimize performance and board space.
RDIVSYS6951=1
FILTSYS6951=0 LTC6951 OINV Bit
RAOSYS6951=1 Figure35, step 6 and Figure36, step 19 set the OINVX
LTC6951Wizard inputs for the CLOCK LTC6951 in Figure36 values for each output. The LTC6951 OINV value can
be determined by referring to the schematics shown
fCLK6951.REF=50MHz Figure34. These OINVX settings, along with the DEL[X]
fCLK6951.OUT0=250MHz settings above, program the LTC6951s SYSREF rising
fCLK6951.OUT1=1GHz edge to start a CLOCK cycle before its paired LTC6951
fCLK6951.OUT2=1GHz CLOCKs rising edge.
fCLK6951.OUT3=250MHz
STANDARD OUTX CONNECTION
fCLK6951.OUT4=250MHz
ICLK6951.CP=11.2mA OUTPUT INVERT OUTX+ CLK+ OR
SYSREF+
NDIVCLK6951=5 OINVX 100
OUTX CLK OR
RDIVCLK6951=1 LTC6951 SYSREF
FILTCLK6951=0 WHEN CONNECTED TO
CLK: SET OINVX = 1
RAOCLK6951=1 SYSREF: SET OINVX = 0
Figures35, 36 and 37 provide the remaining steps nec- HARDWARE INVERTED OUTX CONNECTION
essary to complete the LTC6951 portion of this design.
OUTX+ CLK+ OR
Several steps in Figures35 to 37 require the following OUTPUT INVERT
SYSREF+
additional information. OINVX
OUTX
100
CLK OR
LTC6951 SYSREF
Importing Reference Noise
WHEN CONNECTED TO AN161 F34
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AN161-45
Application Note 161
DELAY Settings If Equation 46 calculates a DEL[X] > 255 PDIV cycles
Figure37, step 28 references Equation46. Equation46 (maximum delay setting), try increasing the LTC6951 PDIV
calculates DEL[X] in PDIV cycles. The same DEL[x] value value used in Figures35 and 36. This will create a larger
will be used for both SYSREF LTC6951 and CLOCK LTC6951 delay range. Repeat the steps in Figures35 and36 after
pairs. In Equation46 the number 18 refers to the number of the PDIV value is increased (check the box next to PDIV in
PDIV cycles when DEL[X]=0. For more information refer the LTC6951Wizard Design tab to avoid auto-calculating
to the LTC6951 data sheet OUTPUT SYNCHRONIZATION a new PDIV).
section titled Synchronization Events. SYSREF LTC6951 ALCEN Bit
M0CLK6951 Figure37, step 33 sets the SYSREF LTC6951 ALCEN bit
DEL[X] = Y M0SYS6951 18 + 1 (46)
M[X]CLK6951 high. If ALCHI or ALCLO are being monitored, then ALCEN
is set high to reset the ALC flags during power-down and
where Y is smallest integer that ensures DEL[X]>0. power-up routines for the SYSREF LTC6951. Refer to the
Synchronization Routines section.
As shown in Figure37, step 28
DEL1=1128 18 + (8/2) 1=113
DEL2=1 128 18 + (8/2) 1=113
DEL3=1 128 18 + (8/8) 1=110
DEL4=1 128 18 + (8/8) 1=110
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AN161-46
Application Note 161
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AN161-47
Application Note 161
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AN161-48
Application Note 161
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AN161-49
Application Note 161
STANDARD REFERENCE CONNECTION Table 4. Hardware Inverted Reference Connection
LTC6954 Register Settings
DELAY DIVIDE OUTX+
REF+
REFERENCE LTC6954 OUTX MX DELX
DELX MX 100
INPUT OUTX
REF MXCLOCK
LTC6954-4 LTC6951 To CLOCK LTC6951 Even Number + Y*
2
CLOCK
LT6951 INPUT MXSYSREF
SYSREF To SYSREF LTC6951 Even Number + Y*
2
LT6951 INPUT
SYNCHRONIZED ON RISING EDGES *Y, integer, same value for all DELX
an161f
AN161-50
Application Note 161
LREFCLK LCLK.OUT4 Power down SYSREF after JESD204b alignment sequence
REF OUT4+
REF+ OUT4 is complete:
OUT3+ CLK+
OUT3 LCLK.OUT3
CLK
1. Power down SYSREF LTC6951 (PDALL=1)
CLOCK OUT0+
REFIN OUT0+
LTC6951 OUT0 LCLK.OUT0 SYSREF+
SYSREF
2. Power down LTC6954 OUT2 (PD_OUT2=1)
OUT0 OUT1+
CS
OUT1 LCLK.OUT1 If JESD204 requires re-alignment:
OUT1+
LTC6954
OUT1 SCLK OUT2+
SDATA OUT2 LCLK.OUT2 1. Power up SYSREF LTC6951 (PDALL=0)
OUT2+ LSYS.OUT4
OUT2 REF OUT4+ 2. Power up LTC6954 OUT2 (PD_OUT2=0)
REF+ OUT4
LREFSYS
OUT3+
LSYS.OUT3 3. Toggle SYSREF LTC6951 SPI SSYNC bit or SYNC
OUT3
SYSREF OUT0+ pin (minimum 1ms)
LTC6951 OUT0 LSYS.OUT0
OUT1+
LSYS.OUT1 Expandable Solution
OUT1
CS
SCLK OUT2+
LSYS.OUT2 The EZ204Sync solution is infinitely expandable. As shown
SDATA OUT2 AN161 F39
in Figure40 the EZ204Sync design example can be re-
Figure39. Trace Length Matching peated by adding an EZSync CONTROLLER to distribute
the reference to multiple LTC6954s.
Synchronization Routines For further expansion it is possible to cascade additional
On initial power-up: reference distribution stages between Stage 1 and Stage2.
Refer to the EZSync Design Example for more details.
1. Program LTC6954 and LTC6951 SPI registers
When designing a multi-stage reference divider/distribu-
2. Toggle LTC6954 SYNC pin (minimum 1ms) tion network, take into account the additive properties of
3. Wait for LTC6951 bias voltages to stabilize channel to channel skew
4. Calibrate all LTC6951 VCOs noise floor at frequency offsets less than the CLOCK
5. Toggle all LTC6951 SPI SSYNC bits or SYNC pins LTC6951 loop filters pass-band. Refer to Appendix:
(minimum 1ms) Model Reference Noise for LTC6951Wizard Simulations.
If some LTC6951s can power down during operation, then
selecting reference distribution parts with the ability to
power down individual outputs can save additional power.
an161f
AN161-51
Application Note 161
3.3V 5V
10
470nF
80.6
V+ VCP+ VVC0+ CP
BB
1nF 1.5nF 80.6
CMA
CMB CLOCK 68nF
1F CMC LTC6951
TB
1F TUNE
BVC0 OUT4+
250MHz, CLOCK
OUT4
1F OUT3+
250MHz, CLOCK
REF OUT3
OUT0+
100 1F 250MHz, CLOCK
OUT0
REF+ OUT1+
1GHz, CLOCK
STAGE 2 OUT1
CS
EZSync FOLLOWER SPI SCLK OUT2+
STAGE 1 REFERENCE DISTRIBUTION 1GHz, CLOCK
SYNC SDI OUT2
EZSync CONTROLLER
REFERENCE DISTRIBUTION LTC6954-4
3.3V 5V
OUT0+ 10
PECL0+ TO CARD #1 IN+ M0 = /2
100MHz VCO OUT0 50MHz 470nF
REFERENCE
/1 PECL0 DLY0 = 1
100
OUT1+ V+ VCP+ VVC0+ CP
BB
PECL1+ TO CARD #2 IN
OUT1 0.33nF 2050
/1 PECL1 CMA
VCC 10k OUT2+ CMB SYSREF 68nF
PECL2+ TO CARD #3
OUT0SEL M0 = /32 1F
OUT2 3.125MHz CMC LTC6951
/1 PECL2 10k DLY2 = 16 TB
OUT2SEL 1F TUNE
EZSync PECL4+ TO CARD #4
SYNC PULSE SYNC /1 PECL4 SYNC BVC0 OUT4+
15.625MHz, SYSREF
WIDTH 1ms OUT4
LTC6950
DISTRIBUTION 1F OUT3+
15.625MHz, SYSREF
ONLY MODE REF OUT3
OUT0+
TO CARD #1 100 1F 15.625MHz, SYSREF
OUT0
TO CARD #2
EZSync REF + OUT1+
15.625MHz, SYSREF
TO CARD #3 SYNC PULSE SKEW OUT1
CS
TO CARD #4 BETWEEN PARTS <10s SPI SCLK OUT2+
SYNC 15.625MHz, SYSREF
SDI OUT2
DAUGHTER CARD #1
DAUGHTER CARD #2
FOR FURTHER EXPANSION
1. REPLACE LTC6954 WITH LTC6950 DAUGHTER CARD #3
2. CASCADE MORE REFERENCE DISTRIBUTION
STAGES BETWEEN STAGE 1 AND STAGE 2 DAUGHTER CARD #4
AN161 F40
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AN161-52
Application Note 161
110
120
130
140
REF #1
150 REF #2
CCHD575
160
1k 10k 100k 1M 10M 100M
OFFSET FREQUENCY (MHz)
AN161 F41
Figure42. LTC6951Wizard Reference Noise File Format
Figure41. Comparing LTC6951Wizard Results with
Different Reference Profiles
AN161-53
Application Note 161
Distributed Reference Noise not available, Equation48 scales the phase noise from
A distributed references phase noise is the product of the nearest available frequency to the desired frequency.
the reference phase noise and the additive phase noise f
of the fanout buffer. PNY (X) = PN Y DS(X) 20 LOG Y DS
fREF (48)
REFERENCE DISTRIBUTION
FAN-OUT BUFFER Where:
REFERENCE fY-DS, carrier frequency of phase noise curve
(PNY-DS)
fREF, desired reference frequency at LTC6951 refer-
ence input
PNY, phase noise at fREF
AN161 F44
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AN161-54
Application Note 161
CCHD-575 LTC6954-4 Example 2: Divided And Distributed Reference
Offset Frequency 100MHz 100MHz (EZParallelSync and EZ204Sync CLOCK6951)
(Hz) (dBc/Hz) (dBc/Hz)
10 90 141.8 Estimate the reference phase noise curve to import into
100 121 149.8 LTC6951Wizard using Crysteks CCHD-575 100MHz ref-
1k 143.5 157.8 erence and the LTC6954-4 as the LVDS reference divide/
10k 155 162.8 distribution IC. The LTC6954-4 divider will be set to 2 to
100k 162 162.8 create a 50MHz reference at the LTC6951 input.
1M 166 163.8
10M 168 163.8
Step 1: Refer to vendors data sheets for phase noise
100M 168 163.8
curves provided in table below
LTC6954-4
CCHD-575 30.72MHz
Step 3: Calculate the total reference distribution network Offset Frequency 100MHz (122.88MHz/4)
phase noise using the values in Step 2 with Equation47. (Hz) (dBc/Hz) (dBc/Hz)
10 90 140
Offset CCHD-575 LTC6954-4 PNTOT
Frequency 100MHz 100MHz 100MHz 100 121 152
(Hz) (dBc/Hz) (dBc/Hz) (dBc/Hz) 1k 143.5 161
10 90 141.8 90 10k 155 166
100 121 149.8 121 100k 162 166
1k 143.5 157.8 143.3 1M 166 166
10k 155 162.8 154.3 10M 168 166
100k 162 162.8 159.8 100M 168 166
1M 166 163.8 161.8
10M 168 163.8 162.4 Step 2: Use Equation 48 to adjust the CCHD-575 and
100M 168 163.8 162.4
LTC6954-4 phase noise profiles to 50MHz
an161f