Hysteresis due to trap

charges in 2DEG
(or graphene) FETs

BY: SUBMITTED TO:

Prashant Khatri Prof. Anjan Kumar Gupta
10514 Department Of Physics
Trapping
The ungated
sites in region between
typical the gate edge and
2DEG interface
Modfet

Metal Gate
Buffer layer
Interface

2DEG interface
Trapping effects in FET
transistors

Gate lag
Current
Dispersion

Hysteresis Kink effect

 Source of trapping

The defects and dislocations can potentially act as the

charge carrier traps creating localized levels inside the
bandgap.
While the majority of the trapping effects result in similar
degradation of the transistor characteristics at high
frequencies, the dominating trapping mechanisms could
vary in devices grown by different methods or subjected
to different processing procedures. It is essential,
therefore, that any characterization method
differentiate between various trapping centers.
 How to detect?

Transient spectroscopy: Transient spectroscopy allows

extraction of the activation energy of the trap and the
trap cross-section .
As In the presence of an electric field, the characteristics
of the capture and emission process change. The
apparent activation energy in this case may significantly
differ from the zero-field binding energy of the trap. To
determine the position of the trap level with respect to
the conduction band accurately, the effect of the
perturbing electric field must be taken into account.
 Mechanism of lag
Delayed response of the drain current with respect to
the gate voltage variation.
Consider a system of equivalent localized trapping
centers in the vicinity of the gate contact, with the
ground level of trap within the bandgap.
The potential at the gate electrode defines the position
of the trap levels with respect to the Fermi level and
therefore, its variation causes changes in the occupation
factor of the trapping center.
 Formulism

= 1 + 1 + ( )

the first term represents electron tunnelling from the gate
into the semiconductor .
other two terms represent electron exchange between the
trapping level and the conduction band, where c and e
are the capture and the emission probabilities, and n/N is
the occupation factor of the conduction band. In the
barrier, the occupation factor is very small.
The density of the 2DEG is affected by the electric field of
the trapped charge.
The emission and capture rates and can be measured by
monitoring the time evolution of the drain current.
The emission probability depends on the temperature and
the position of the trap level with respect to the bottom of
the conduction band.
Activation energy and capture cross section

Richardsons law

= 2

Capture cross section

2 3
=
3 2 8 2

Both characteristics of the trap can be found by

fitting the temperature dependence of e(T) to the
experimentally measured emission rate.
 Dynamics of the trapped charge

Directly reflected in a deviation of channel current

from the steady state level
2

1. Barrier traps Gate 2DEG

interface interface
2
2 = (1 )

2. Surface traps
2 = Trapped
position
 Results
The induced channel charge is proportional to the amount of the
trapped charge . The carrier mobility in the channel remains
unchanged for relatively small variation of the carrier density in the
channel.
The trapped charge, therefore, is directly proportional to the
difference between the steady state current and the transient
current.
In reality there is a trap band so there are different levels of traps so
at switching of gate potential at different depths will show the
different recovery time of the current as the tunnelling probability will
increase with more reduction in gate potential hence more filling of
trap levels and different trap levels do have different emiision rates so
transient curve might not show the exponential curve , as now the
band levels will have different emission rates , hence the transient
curve wont be exponential.
As the depth and duration of the filling pulse increases the slow
dynamics becomes more pronounced.
Channel current transient after a 500 ns gate filling pulse. The current is
normalized to the steady state value. The insets show the difference between
the steady state and the transient current for the shallow ( = 3 V) and the
deep ( = 10 V) filling pulses.
 Pool Frenkel Effect

1 2
3
= 1 2

= 0

= (0)exp( )

O. Mitrofanov, M. Manfra / Superlattices and Microstructures 34 (2003) 3353.

Hence on increasing the drain voltage the emission

rate increases. Therefore this will lead to drain lag.
Trap levels in bulk region

+
( = )
 Bulk Trapping

Deep donor level traps in substrate region

Electrons from 2DEG gets trapped in it.
Due to net reduced charge bulk attains negative.
For the neutral sake positive charges are induced and
which will affect the field in channel hence current lag
will occur.
At higher fields these holes are injected back into the
substrate and the emission mechanism increases.
 Effective current
Knowing the widths of two region one has to equal the
no. density * width on both side like on substrate site:
, in interface depleted region width will
depend on applied field.
This will give no. density of interface charges , this will
decide the effective field in the channel and ultimately the
no. of states in the channel .
= 2

= gate width,
2 = 2DEG no.density of states , which will be affected by
the amount of
= electron velocity in channel
 CONCLUSION
Emission rate/Capture rate for particular level is same .
Emission rate for different levels are different.
Trapping depends on the amount of pulse time and depth of
pulse, as it will traps of more levels will be exposed for different
time.
Hysteresis will be there if proper gate bias and applied fields are
not chosen and that will be different for different types of
devices.
At higher fields more emission rate due to poole frenkell effect.
Impact ionization effect shows kink effect.
Memory effect on change in gate bias.
 REFERENCES

Solid-State Electronics Vol. 35, No. 10, pp. 1543-1548, 1992.

Qualitative and Quantative Characterization of Trapping Effects

inAlGaN/GaN High Electron Mobility Transistors By Hyeong

Nam Kim.

Mechanisms of gate lag in GaN/AlGaN/GaN high electron

mobility transistors by Oleg Mitrofanov, Michael Manfra.

IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 42. NO. 10.