AIM

To design & develop Temperature based Fan Speed Controller, which can be
used to automate any organization. The major blocks of our system are as follows:-

1.1 SPECIFICATION

Power Supply :
We will need a +5V/500mA power supply for our project. For this purpose we
will use a step down transformer to convert 220VAC/50Hz into 12VAC. The out of
transformer is rectified through bridge rectifier using diode 1N4001. Linear voltage
regulator IC LM7805 is used to provide a stable regulated +5V supply for
microcontroller and other parts in the project.
Microcontroller AT 89S51 :
ATMEL make microcontroller AT89S51 is the main controller being used in this
project due to its easy availability and low cost. The function of the microcontroller
is to read the pulses collected by electronics hardware. The collected pulses are
analyzed by microcontroller & displayed in per minute format on LCD display.
The Temperature control information may be further processed & send to any
remote monitoring station.
LCD :
In our project we will be using a LCD for displaying the Temperature control
information of Temperature and its presence. We will be using a 16x2 LCD for this
purpose.
SENSORS :
In our project we will use electrode for sensing effect of Temperature control.
These electrodes basically will sense the change in resistance due to compression
& decompression of Temperature, which is required to circulate the automatic.
AMPLIFIER & FILTER :
The function of electronics amplifier & filter is to amplify the weak signal
received by electrodes without noise. The amplification and filtering is done in
multiple stage One LCD display is connected to the port 0. Here we use two line
and 16 character LCD display.

1
There is total 8 data line on the lcd for data receiving , but here we use only 4 data
lines for data receiving from the microcontroller. Pin no 33,34,35,36 is connected
to thepin no 11,12,13,14 of the lcd data lines. Pin no 4,5,6 is the RS/RW/ENABLE
pin no of the lcd , These pins are connected to the pin no 39,38,37 of the
microcontroller. Pin no 40 of controller is connected to the positive supply. On this
pin we provide a positive 5 volt and its from 7805 regulator. Ic 7805 is a 5 volt
regulator and provide a 5 volt regulated supply. IC 7805 is a three pin regulator .
Pin no 1 is input pin , pin no 2 is ground pin and pin no 3 is output pin. Here 78
mean positive voltage and 5 means 5volt. 79 means negative voltage . There are so
many regulator available from 7805 to 7818 volt, here 18 means 18 volt. Pin no 20
of the controller is connected to ground pin. Pin no 1 to 8 is for the port 1. Pin no 9
is for the reset pin. On this pin we connect one resistor and one capacitor with
positive and resistance is to be ground. With the help of this circuit controller is
automatic reset when power is on. Pin no 10 to 17 is for the port p3. Pin no 18, 19
2
is the pin for crystal pins. On this pin we connect a crystal to provide a proper
clock to the controller. In this project we use 12 Mhtz crystal to pin no 18,19. Pin
no 20 of the controller is connected to the ground pin. Pin no 21 to 28 is for the
port p2 and pin no 39 to 32 is for the port p0. Pin no 30 is ale pin , pin no 29 is
Psen and pin no 31 is excess enable. We use these three pin when we require a
extra memory for controller. If not required then we connect a pin no 31 to the
positive supply. In this project there is no need of extra memory so we connect pin
no 31 to the positive supply.

1.2 CIRCUIT SPECIFICATION

3
 U2 LCD1
7805 LM016L
TR1 D6 1 3
VI VO
GND

1N4001 R15

1
C2 1k
RN1
2

1000u

VDD
VSS

VEE

RW
RS
10k

D0
D1
D2
D3
D4
D5
D6
D7
D8 C3

E
D12

10
9
8
7
6
5
4
3
2

1
2
3

4
5
6

7
8
9
10
11
12
13
14
1N4001 LED-RED 1000u
TRAN-2P2S
R1
C5 1k

Cicuit diagram
33p X1 U1
19 39
XTAL1 P0.0/AD0
38
C4 P0.1/AD1
37
CRYSTAL P0.2/AD2
18 36
XTAL2 P0.3/AD3
35

4
P0.4/AD4
33p 34
P0.5/AD5
33
P0.6/AD6
9 32
R9 RST P0.7/AD7 D1
21
10k
C1 P2.0/A8
22
P2.1/A9
23 1N4001
P2.2/A10
29 24
PSEN P2.3/A11
10u 30 25
ALE P2.4/A12
31 26
C6 EA P2.5/A13
27
151p U4 P2.6/A14
28
P2.7/A15
1 20
CS VCC
2 18 1 10
RD DB0(LSB) P1.0 P3.0/RXD
3 17 2 11
WR DB1 P1.1 P3.1/TXD
U3
4
CLK IN
ADC0804
DB2
16 3
P1.2 P3.2/INT0
12
RV1 R3
1 5 15 4 13 1k
INTR DB3 P1.3 P3.3/INT1
8 14 5 14
A GND DB4 P1.4 P3.4/T0
10 13 6 15

A
D GND DB5 P1.5 P3.5/T1
9 12 7 16

50%
27.0 VREF/2 DB6 P1.6 P3.6/WR
19
CLK R DB7(MSB)
11 8
P1.7 P3.7/RD
17 D2
LED-RED
2 6 80C51
VOUT VIN+

K
7 1k
VIN-
3 LM35 R4 Q1 R2
SL 100 1k
D3 1k
Q2
BC558
1N4001
Reset Circuitry :

As soon as you give the power supply the 8051 doesnt start. You need to restart
for the microcontroller to start. Restarting the microcontroller is nothing but giving
a Logic 1 to the reset pin at least for the 2 clock pulses. So it is good to go for a
small circuit which can provide the 2 clock pulses as soon as the microcontroller is
powered. This is not a big circuit we are just using a capacitor to charge the
microcontroller and again discharging via resistor.

Crystals :

Crystals provide the synchronization of the internal function and to the

peripherals. Whenever ever we are using crystals we need to put the capacitor

behind it to make it free from noises. It is good to go for a 33pf capacitor.

5
We can also resonators instead of costly crystal which are low cost and

externalcapacitor can be avoided. But the frequency of the resonators varies a lot.

And it is strictly not advised when used for communications projects.

POWER SUPPLY :
In the power supply section we use one step down transformer to step
down the voltage from 220 volt ac to 9 volt dc. Oiut put of the transformer is
further connected to the two diode circuit. Here two diode work as a full
wave rectifier circuit. Output of the full wave rectifier is now filtered by the
capacitor. Capacitor convert the pulsating dc into smooth dc with the help
of charging and discharging effect. Output of the capacitor is now
regulated by the ic 7805 regulator. IC 7805 provide a 5 volt regulation to the
circuit and provide a regulated 5 volt power supply. Output of the regulator
is now again filter by the capacitor . In the output of the capacitor we use
one resistor and one l.e.d in series to provide a visual indication to the
circuit.

6
.

COMPONENTS USED :
1. MICROCONTROLLER 89S52 ( 40 PIN CONTROLLER)
2. LCD ( 2 BY 16 ) 5 BY 7 MATRIX
3. MEMORY 24C02 ( SERIAL EEPROM )
4. RF READER COIL.
5. SWITCH PUSH TO ON (12 SWITCHES)
7
 2. MICROCONTROLLER AT89C51

2.1 Architecture of 8051 family:-

The figure 1 above shows the basic architecture of 8051 family of

microcontroller.

2.2 Features
Compatible with MCS-51 Products
4K Bytes of In-System Reprogrammable Flash Memory
Endurance: 1,000 Write/Erase Cycles
Fully Static Operation: 0 Hz to 24 MHz
Three-Level Program Memory Lock
128 x 8-Bit Internal RAM
32 Programmable I/O Lines

8
 Two 16-Bit Timer/Counters
Six Interrupt Sources
Programmable Serial Channel
Low Power Idle and Power Down Modes

2.3 Description

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with

4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM). The
device is manufactured using Atmels high density nonvolatile memory technology
and is compatible with the industry standard MCS-51 instruction set and pinout.
The on-chip Flash allows the program memory to be reprogrammed in-system or
by a conventional nonvolatile memory programmer. By combining a versatile 8-bit
CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful
microcomputer which provides a highly flexible and cost effective solution to
many embedded control applications. The AT89C51 provides the following
standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit
timer/counters, five vector two-level interrupt architecture, a full duplex serial port,
and on-chip oscillator and clock circuitry.
In addition, the AT89C51 is designed with static logic for operation down to zero
frequency and supports two software selectable power saving modes. The Idle
Mode stops the CPU while allowing the RAM, timer/counters, serial port and
interrupt system to continue functioning. The Power down Mode saves the RAM
contents but freezes the oscillator disabling all other chip functions until the next
hardware reset.

9
Pin Description

VCC
Supply voltage.

GND
Ground.

Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can
sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as
high impedance inputs. Port 0 may also be configured to be the multiplexed low
order address/data bus during accesses to external program and data memory. In
this mode P0 has internal pull-ups. Port 0 also receives the code bytes during Flash
programming, and outputs the code bytes during program verification.
External pull-ups are required during program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output
buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they
are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1
pins that are externally being pulled low will source current (IIL) because of the
internal pull-ups. Port 1 also receives the low-order address bytes during Flash
programming and verification.

Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output
buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they
are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source current (IIL) because of the
internal pull-ups. Port 2 emits the high-order address byte during fetches from
10
external program memory and during accesses to external data memory that uses
16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pull-
ups when emitting 1s. During accesses to external data memory that uses 8-bit
addresses (MOVX @ RI); Port 2 emits the contents of the P2 Special Function
Register. Port 2 also receives the high-order address bits and some control signals
during Flash programming and verification.

Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output
buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they
are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source current (IIL) because of the
pull-ups. Port 3 also serves the functions of various special features of the
AT89C51 as listed below:
Port 3 also receives some control signals for Flash programming and verification.

RST
Reset input. A high on this pin for two machine cycles while the oscillator is
running resets the device.

ALE/PROG
Address Latch Enable output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG)
during Flash programming. In normal operation ALE is emitted at a constant rate
of 1/6 the oscillator frequency, and may be used for external timing or clocking
purposes. Note, however, that one ALE pulse is skipped during each access to
external Data Memory. If desired, ALE operation can be disabled by setting bit 0
11
of SFR location 8EH. With the bit set, ALE is active only during a MOVX or
MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-
disable bit has no effect if the microcontroller is in external execution mode.

PSEN
Program Store Enable is the read strobe to external program memory.

Port Pin Alternate Functions

P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)

When the AT89C51 is executing code from external program memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are skipped
during each access to external data memory.

EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the
device to fetch code from external program memory locations starting at 0000H up
to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally
latched on reset. EA should be strapped to VCC for internal program executions.

12
This pin also receives the 12-volt programming enable voltage (VPP) during Flash
programming, for parts that require 12-volt VPP.

XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating
circuit.

XTAL2
Output from the inverting oscillator amplifier.

Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left unconnected while
XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle
of the external clock signal, since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and maximum voltage high and
low time specifications must be observed.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain
active. The mode is invoked by software. The content of the on-chip RAM and all
the special functions registers remain unchanged during this mode. The idle mode
can be terminated by any enabled
Interrupt or by hardware reset. It should be noted that when idle is terminated by a
Hardware reset, the device normally resumes program execution, from where it left
off, up to two machine cycles before the internal reset algorithm takes control. On-
13
chip hardware inhibits access to internal RAM in this event, but access to the port
pins is not inhibited. To eliminate the possibility of an unexpected write to a port
pin when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or to external memory.

Status of External Pins during Idle and Power down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Idle Internal 1 Data
Idle External 1 Float Data Address Data
Power down Internal 0 Data
Power down External 0 Float Data

Power down Mode

In the power down mode the oscillator is stopped, and the instruction that invokes
power down is the last instruction executed. The on-chip RAM and Special
Function Registers retain their values until the power down mode is terminated.
The only exit from power down is a hardware reset. Reset redefines the SFRs but
does not change the on-chip RAM. The reset should not be activated before VCC
is restored to its normal operating level and must be held active long enough to
allow the oscillator to restart and stabilize.

Program Memory Lock Bits

On the chip are three lock bits which can be left un-programmed (U) or can be
programmed (P) to obtain the additional features listed in the table below:
When lock bit 1 is programmed, the logic level at the EA pin is sampled and
latched during reset. If the device is powered up without a reset, the latch

14
initializes to a random value, and holds that value until reset is activated. It is
necessary that the latched value of EA be in agreement with
The current logic level at that pin in order for the device to function properly.

Lock Bit Protection Modes

Program Lock Bits Protection Type
LB1 LB2 LB3
1 U No program lock features.
2 P U MOVC instructions executed from external program memory are disabled
from fetching code
Bytes from internal memory, EA is sampled and latched on reset, and further
programming of the
Flash is disabled.
3 P U Same as mode 2, also verify is disabled.
4 P same as mode 3, also external execution is disabled.

Programming the Flash

The AT89C51 is normally shipped with the on-chip Flash memory array in the
erased state (that is, contents = FFH) and ready to be programmed. The
programming interface accepts either a high-voltage (12-volt) or a low-voltage
(VCC) program enable signal. The low voltage programming mode provides a
convenient way to program the AT89C51 inside the users system, while the high-
voltage programming mode is compatible with conventional third party Flash or
EPROM programmers. The AT89C51 is shipped with either the high-voltage or
low-voltage programming mode enabled. The respective top-side marking and
device signature codes are listed in the following table. The AT89C51 code
memory array is programmed byte-by byte
15
In either programming mode. To program any nonblank byte in the on-chip Flash
Memory, the entire memory must be erased using the Chip Erase Mode.

Programming Algorithm:
Before programming the AT89C51, the address, data and control signals should
be set up according to the Flash programming mode table and Figures 3 and 4. To
program the AT89C51, take the following steps.
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V for the high-voltage programming mode.
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The
byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps
1 through 5, changing the address and data for the entire array or until the end of
the object file is reached.

Data Polling:
The AT89C51 features Data Polling to indicate the end of a write cycle. During a
write cycle, an attempted read of the last byte written will result in the complement
of the written datum on PO.7. Once the write cycle has been completed, true data
are valid on all outputs, and the next cycle may begin. Data Polling may begin any
time after a write cycle has been initiated.

Ready/Busy:
The progress of byte programming can also be monitored by the RDY/BSY
output signal. P3.4 is pulled low after ALE goes high during programming to

16
indicate BUSY. P3.4 is pulled high again when programming is done to indicate
READY.

Program Verify:
If lock bits LB1 and LB2 have not been programmed, the programmed code data
can be read back via the address and data lines for verification. The lock bits
cannot be verified directly. Verification of the lock bits is achieved by observing
that their features are enabled.

Chip Erase:
The entire Flash array is erased electrically by using the proper combination of
control signals and by holding ALE/PROG low for 10 ms. The code array is
written with all 1s. The chip erase operation must be executed before the code
memory can be re-programmed.

Reading the Signature Bytes:

The signature bytes are read by the same procedure as a normal verification of
locations 030H,
031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The
values returned are as follows.
(030H) = 1EH indicates manufactured by Atmel
(031H) = 51H indicates 89C51
(032H) = FFH indicates 12V programming
(032H) = 05H indicates 5V programming

17
Programming Interface
Every code byte in the Flash array can be written and the entire array can be
erased by using the appropriate combination of control signals. The write operation
cycle is self timed and once initiated, will automatically time itself to completion.
All major programming vendors offer worldwide support for the Atmel
microcontroller series. Please contact your local programming vendor for the
appropriate software revision.

3. P.C.B. LAYOUT
The entire circuit can be fabricated on a veroboard. However, actual-size
PCB layout for the circuits of figs is given in fig. The component layout for the
PCB of fig. is given in fig.

Shielded wire may be used for connection of microphole. Low profile

sockets may be used for ICs for easy replacement and fault finding. Assembly of
the components may be done in the following sequence: IC sockets, resistors,
18
capacitors, diodes, transistors, LEDS, etc., observing correct polarity of
components. While soldering, clean the flux using isopropyl alcohol. Heat sink
may be used for IC10 (7805).

Before putting the ICs in their respective sockets, it is better to measure the
resistance between their pins and ground point using multimeter. It should not be
very low.

Observe PCB for dry joints, solder splashes and bridges between tracks.
After that connect the power supply from transformer X1. Use good quality
transformer and relay of proper rating as required for the load.

Layout of desired circuit preparation is finest and most important operation

in any printing circuit be and manufacturing process. For of all layout of
component side is to be made in accordance with available component dimension.
The following point are observed while forming the layout of PCB :
Between two component sufficient space should be maintained.
High voltage/max. dissipated components should be mounted at a sufficient
distance from semi-conductors and electrolytic capacitors.
The most important. Point is that the component layout is making proper
component. With copper side circuit layout. Printed Circuit Board (PCB) are
used to avoid most or all the disadvantages of conventional bread board. This
also avoid the use of thin wired for connecting the components.
They are small in size sufficient in performance.
The two most popular boards are singles sided board and the double
sided/board. The single sides PCB are widely used.

19
 For general purpose application where the cost it is to be low it the layout is
simple.
After etching the PCB in kept into clear water for about half-an hour. In
order to get PCB away from any acidic properties will be the cause of Poor
performance of circuit. After the PCB has been thoroughly caused, point is
removed by soft price of cloth dipped in thinner or turbine. Then PCB is checked
as per the layout now the PCB is ready for uses.

3.1 SPECIAL FUNCTION REGISTER (SFR) ADDRESSES:

ACC ACCUMULATOR 0E0H
B B REGISTER 0F0H
PSW PROGRAM STATUS WORD 0D0H
SP STACK POINTER 81H
DPTR DATA POINTER 2 BYTES
DPL LOW BYTE OF DPTR 82H
DPH HIGH BYTE OF DPTR 83H
P0 PORT0 80H
P1 PORT1 90H
P2 PORT2 0A0H
P3 PORT3 0B0H
TMOD TIMER/COUNTER MODE CONTROL 89H
TCON TIMER COUNTER CONTROL 88H
TH0 TIMER 0 HIGH BYTE 8CH
TLO TIMER 0 LOW BYTE 8AH
TH1 TIMER 1 HIGH BYTE 8DH
TL1 TIMER 1 LOW BYTE 8BH
20
SCON SERIAL CONTROL 98H
SBUF SERIAL DATA BUFFER 99H
PCON POWER CONTROL 87H

TMOD (TIMER MODE) REGISTER

Both timers are the 89c51 share the one register TMOD. 4 LSB bit for the timer 0
and 4 MSB for the timer 1.
In each case lower 2 bits set the mode of the timer
Upper two bits set the operations.
GATE : Gating control when set. Timer/counter is enabled only while the INTX
pin is high and the TRx control pin is set. When cleared, the timer is enabled
whenever the TRx control bit is set.
C/T : Timer or counter selected cleared for timer operation (input from internal
system clock)

M1 Mode bit 1
M0 Mode bit 0

M1 M0 MODE OPERATING MODE

0 0 0 13 BIT TIMER/MODE
0 1 1 16 BIT TIMER MODE
1 0 2 8 BIT AUTO RELOAD

21
1 1 3 SPLIT TIMER MODE

PSW (PROGRAM STATUS WORD)

CY PSW.7 CARRY FLAG

AC PSW.6 AUXILIARY CARRY
F0 PSW.5 AVAILABLE FOR THE USER FRO GENERAL
PURPOSE
RS1 PSW.4 REGISTER BANK SELECTOR BIT 1
RS0 PSW.3 REGISTER BANK SELECTOR BIT 0
0V PSW.2 OVERFLOW FLAG
-- PSW.1 USER DEFINABLE BIT
P PSW.0 PARITY FLAG SET/CLEARED BY HARDWARE

PCON REGISATER (NON BIT ADDRESSABLE)

If the SMOD = 0 (DEFAULT ON RESET)

TH1 = CRYSTAL FREQUENCY

256---- ____________________

384 X BAUD RATE

If the SMOD IS = 1

22
 CRYSTAL FREQUENCY

TH1 = 256--------------------------------------
192 X BAUD RATE
There are two ways to increase the baud rate of data transfer in the 8051
1. To use a higher frequency crystal
2. To change a bit in the PCON register
PCON register is an 8 bit register. Of the 8 bits, some are unused, and some are
used for the power control capability of the 8051. The bit which is used for the
serial communication is D7, the SMOD bit. When the 8051 is powered up, D7
(SMOD BIT) OF PCON register is zero. We can set it to high by software and
thereby double the baud rate
BAUD RATE COMPARISION FOR SMOD = 0 AND SMOD =1
TH1 (DECIMAL) HEX SMOD =0 SMOD =1
-3 FD 9600 19200
-6 FA 4800 9600
-12 F4 2400 4800
-24 E8 1200 2400
XTAL = 11.0592 MHZ
IE (INTERRUPT ENABLE REGISTOR)

EA IE.7 Disable all interrupts if EA = 0, no interrupts is acknowledged

If EA is 1, each interrupt source is individually enabled or disabled
By sending or clearing its enable bit.
IE.6 NOT implemented
ET2 IE.5 enables or disables timer 2 overflag in 89c52 only

23
ES IE.4 Enables or disables all serial interrupt
ET1 IE.3 Enables or Disables timer 1 overflow interrupt
EX1 IE.2 Enables or disables external interrupt
ET0 IE.1 Enables or Disables timer 0 interrupt.
EX0 IE.0 Enables or Disables external interrupt 0
INTERRUPT PRIORITY REGISTER

If the bit is 0, the corresponding interrupt has a lower priority and if the bit is 1 the
corresponding interrupt has a higher priority
IP.7 NOT IMPLEMENTED, RESERVED FOR FUTURE USE.
IP.6 NOT IMPLEMENTED, RESERVED FOR FUTURE USE
PT2 IP.5 DEFINE THE TIMER 2 INTERRUPT PRIORITY LELVEL
PS IP.4 DEFINES THE SERIAL PORT INTERRUPT PRIORITY LEVEL
PT1 IP.3 DEFINES THE TIMER 1 INTERRUPT PRIORITY LEVEL
PX1 IP.2 DEFINES EXTERNAL INTERRUPT 1 PRIORITY LEVEL
PT0 IP.1 DEFINES THE TIMER 0 INTERRUPT PRIORITY LEVEL
PX0 IP.0 DEFINES THE EXTERNAL INTERRUPT 0 PRIORITY LEVEL

SCON: SERIAL PORT CONTROL REGISTER, BIT ADDRESSABLE

SCON

SM0 : SCON.7 Serial Port mode specified

24
SM1 : SCON.6 Serial Port mode specifier
SM2 : SCON.5
REN : SCON.4 Set/cleared by the software to Enable/disable reception
TB8 : SCON.3 the 9th bit that will be transmitted in modes 2 and 3,
Set/cleared
By software
RB8 : SCON.2 In modes 2 &3, is the 9 th data bit that was received. In mode
1,
If SM2 = 0, RB8 is the stop bit that was received. In mode 0
RB8 is not used
T1 : SCON.1 Transmit interrupt flag. Set by hardware at the end of the 8 th
bit
Time in mode 0, or at the beginning of the stop bit in the
other
Modes. Must be cleared by software
R1 SCON.0 Receive interrupt flag. Set by hardware at the end of the 8 th
bit
Time in mode 0, or halfway through the stop bit time in the
other
Modes. Must be cleared by the software.
TCON TIMER COUNTER CONTROL REGISTER
This is a bit addressable
TF1 TCON.7 Timer 1 overflows flag. Set by hardware when the
Timer/Counter 1
Overflows. Cleared by hardware as processor
TR1 TCON.6 Timer 1 run control bit. Set/cleared by software to turn Timer
Counter 1 On/off
25
TF0 TCON.5 Timer 0 overflows flag. Set by hardware when the
timer/counter 0
Overflows. Cleared by hardware as processor
TR0 TCON.4 Timer 0 run control bit. Set/cleared by software to turn timer
Counter 0 on/off.
IE1 TCON.3 External interrupt 1 edge flag
ITI TCON.2 Interrupt 1 type control bit
IE0 TCON.1 External interrupt 0 edge
IT0 TCON.0 Interrupt 0 type control bit.

TF 1 T R1 T F0 T R0 IE IT IE 0 IT0

26
3.2 MCS-51 FAMILY INSTRUCTION SET

Notes on Data Addressing Modes

Rn - Working register R0-R7
Direct - 128 internal RAM locations, any l/O port, control or status register
@Ri - Indirect internal or external RAM location addressed by register R0 or R1
#data - 8-bit constant included in instruction
#data 16 - 16-bit constant included as bytes 2 and 3 of instruction
Bit - 128 software flags, any bit addressable l/O pin, control or status bit
A - Accumulator

Notes on Program Addressing Modes

addr16 - Destination address for LCALL and LJMP may be anywhere within the
64-Kbyte program memory address space. addr11 - Destination address for
ACALL and AJMP will be within the same 2-Kbyte page of program memory as
the first byte of the following instruction. Rel - SJMP and all conditional jumps
include an 8 bit offset byte. Range is + 127/ 128 bytes relative to the first byte of
the following instruction.

ACALL addr11
Function: Absolute call
Description: ACALL unconditionally calls a subroutine located at the indicated
address. The instruction increments the PC twice to obtain the address of the
following instruction, then pushes the 16-bit result onto the stack (low-order byte
first) and increments the stack pointer twice. The destination address is obtained by
successively concatenating the five high-order bits of the incremented PC, op code
bits 7-5, and the second byte of the instruction. The subroutine called must
27
therefore start within the same 2K block of program memory as the first byte of the
instruction following ACALL. No flags are affected. Example: Initially SP equals
07H. The labelSUBRTN is at program memory location 0345H. After executing
the instruction ACALL SUBRTN at location 0123H, SP will contain 09H, internal
RAM location 08H and 09H will contain 25H and 01H, respectively, and the PC
will contain 0345H.

Operation: ACALL
(PC) (PC) + 2
(SP) (SP) + 1
((SP)) (PC7-0)
(SP) (SP) + 1
((SP)) (PC15-8)
(PC10-0) Page address
Bytes: 2
Cycles: 2
Encoding: a10 a9 a8 1 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0

ADD A, <src-byte>
Function: Add
Description: ADD adds the byte variable indicated to the accumulator, leaving the
result in the accumulator. The carry and auxiliary carry flags are set, respectively, if
there is a
Carry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integers,
the carry flag indicates an overflow occurred. OV is set if there is a carry out of bit
6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise OV is
cleared. When adding signed integers, OV indicates a negative number produced as
28
the sum of two positive operands, or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register
indirect, or immediate.

Example: The accumulator holds 0C3H (11000011B) and register 0 holds 0AAH
(10101010B). The instruction ADD A, R0 will leave 6DH (01101101B) in the
accumulator with the AC flag cleared and both the carry flag and OV set to 1.

ADD A,Rn
Operation: ADD
(A) (A) + (Rn)
Bytes: 1
Cycles: 1

ADD A, direct
Operation: ADD
(A) (A) + (direct)
Bytes: 2
Cycles: 1
Encoding: 0 0 1 0 1 r r r
Encoding: 0 0 1 0 0 1 0 1 direct address

ADD A, @Ri
Operation: ADD
(A) (A) + ((Ri))
Bytes: 1
Cycles: 1

29
ADD A, #data
Operation: ADD
(A) (A) + #data
Bytes: 2
Cycles: 1
Encoding: 0 0 1 0 0 1 1 i
Encoding: 0 0 1 0 0 1 0 0 immediate data

ADDC A, < src-byte>

Function: Add with carry
Description: ADDC simultaneously adds the byte variable indicated, the carry flag
and the accumulator contents, leaving the result in the accumulator. The carry and
auxiliary
Carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared
otherwise. When adding unsigned integers, the carry flag indicates an overflow
occurred.
OV is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7
but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV
indicates a negative number produced as the sum of two positive operands or a
positive sum from two negative operands. Four source operand addressing modes
are allowed: register, direct, register indirect, or immediate.
Example: The accumulator holds 0C3H (11000011B) and register 0 holds 0AAH
(10101010B) with the carry flag set. The instruction ADDC A, R0 will leave 6EH
(01101110B) in the accumulator with AC cleared and both the carry flag and OV
set to 1.

30
ADDC A, Rn
Operation: ADDC
(A) (A) + (C) + (Rn)
Bytes: 1
Cycles: 1

ADDC A, direct
Operation: ADDC
(A) (A) + (C) + (direct)
Bytes: 2
Cycles: 1
Encoding: 0 0 1 1 1 r r r
Encoding: 0 0 1 1 0 1 0 1 direct address

ADDC A, @Ri
Operation: ADDC
(A) (A) + (C) + ((Ri))
Bytes: 1
Cycles: 1

ADDC A, #data
Operation: ADDC
(A) (A) + (C) + #data
Bytes: 2
Cycles: 1
Encoding: 0 0 1 1 0 1 1 i
Encoding: 0 0 1 1 0 1 0 0 immediate data
31
AJMP addr11
Function: Absolute jump
Description: AJMP transfers program execution to the indicated address, which is
formed at runtime by concatenating the high-order five bits of the PC (after
incrementing the PC twice), op code bits 7-5, and the second byte of the
instruction. The destination must therefore be within the same 2K block of
program memory as the first byte of the instruction following AJMP.
Example: The labelJMPADR is at program memory location 0123H. The
instruction
AJMP JMPADR is at location 0345H and will load the PC with 0123H.

Operation: AJM P
(PC) (PC) + 2
(PC10-0) Page address
Bytes: 2
Cycles: 2
Encoding: a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0

ANL <dest-byte>, <src-byte>

Function: Logical AND for byte variables
Description: ANL performs the bitwise logical AND operation between the
variables indicated and stores the results in the destination variable. No flags are
affected. The two operands allow six addressing mode combinations. When the
destination is an accumulator, the source can use register, direct, register-indirect,
or immediate addressing; when the destination is a direct address, the source can
be the accumulator or immediate data.
32
Note:
When this instruction is used to modify an output port, the value used as the
original
Port data will be read from the output data latch, not the input pins.
Example: If the accumulator holds 0C3H (11000011B) and register 0 holds 0AAH
(10101010B) then the instruction
ANL A, R0
Will leave 81H (10000001B) in the accumulator.
When the destination is a directly addressed byte, this instruction will clear
combinations of bits in any RAM location or hardware register. The mask byte
determining the pattern of bits to be cleared would either be a constant contained in
the instruction or a value computed in the accumulator at run-time.
The instruction ANL P1, #01110011B will clear bits 7, 3, and 2 of output port 1.

ANL A, Rn
Operation: ANL
(A) (A) (Rn)
Bytes: 1
Cycles: 1
Encoding: 0 1 0 1 1 r r r

ANL A, direct
Operation: ANL
(A) (A) (direct)
Bytes: 2
Cycles: 1

33
ANL A, @Ri
Operation: ANL
(A) (A) ((Ri))
Bytes: 1
Cycles: 1

ANL A, #data
Operation: ANL
(A) (A) #data
Bytes: 2
Cycles: 1

ANL direct, A
Operation: ANL
(direct) (direct) (A)
Bytes: 2
Cycles: 1
Encoding: 0 1 0 1 0 1 0 1 direct address
Encoding: 0 1 0 1 0 1 1 i
Encoding: 0 1 0 1 0 1 0 0 immediate data
Encoding: 0 1 0 1 0 1 0 1 direct address

ANL direct, #data

Operation: ANL
(direct) (direct) #data
Bytes: 3
Cycles: 2
34
Encoding: 0 1 0 1 0 0 1 1 direct address immediate data

ANL C, <src-bit>
Function: Logical AND for bit variables
Description: If the Boolean value of the source bit is logic 0 then clear the carry
flag; otherwise leave the carry flag in its current state. A slash (/ preceding the
operand in the assembly language indicates that the logical complement of the
addressed bit is used as the source value, but the source bit itself is not affected. No
other flags are affected. Only direct bit addressing is allowed for the source
operand.

Example: Set the carry flag if and only if, P1.0 = 1, ACC.7 = 1 and OV = 0:
MOV C, P1.0; Load carry with input pin state
ANL C, ACC.7; AND carry with accumulator bit 7
ANL C, /OV; AND with inverse of overflow flag

ANL C, bit
Operation: ANL
(C) (C) (bit)
Bytes: 2
Cycles: 2

ANL C, /bit
Operation: ANL
(C) (C) (bit)
Bytes: 2
Cycles: 2
35
Encoding: 1 0 0 0 0 0 1 0 bit address
Encoding: 1 0 1 1 0 0 0 0 bit address

CJNE <dest-byte >, < src-byte >, rel

Function: Compare and jump if not equal
Description: CJNE compares the magnitudes of the first two operands, and
branches if their values are not equal. The branch destination is computed by
adding the signed relative displacement in the last instruction byte to the PC, after
incrementing the PC to the start of the next instruction. The carry flag is set if the
unsigned integer value of <dest-byte> is less than the unsigned integer value of
<src-byte>; otherwise, the carry is cleared. Neither operand is affected. The first
two operands allow four addressing mode combinations: the accumulator may be
compared with any directly addressed byte or immediate data, and any indirect
RAM location or working register can be compared with an immediate constant.
Example: The accumulator contains 34H. Register 7 contains 56H. The first
instruction in the sequence CJNE R7, # 60H, NOT_EQ; . . . . . . . . ; R7 = 60H
NOT_EQ JC REQ_LOW; If R7 < 60H; . . . . . . . . ; R7 > 60H sets the carry flag
and branches to the instruction at label NOT_EQ. By testing the carry flag, this
instruction determines whether R7 is greater or less than 60H. If the data being
presented to port 1 is also 34H, then the instruction WAIT: CJNE A, P1, WAIT
clears the carry flag and continues with the next instruction in sequence, since the
accumulator does equal the data read from P1. (If some other value was input on
P1, the program will loop at this point until the P1 data changes to 34H).

CJNE A, direct, rel

Operation: (PC) (PC) + 3
if (A) < > (direct)
36
then (PC) (PC) + relative offset
if (A) < (direct)
then (C) 1
else (C) 0
Bytes: 3
Cycles: 2

CJNE A, #data, rel

Operation: (PC) (PC) + 3
if (A) < > data
then (PC) (PC) + relative offset
if (A) data
then (C) 1
else (C) 0
Bytes: 3
Cycles: 2

CJNE RN, #data, rel

Operation: (PC) (PC) + 3
if (Rn) < > data
then (PC) (PC) + relative offset
if (Rn) < data
then (C) 1
else (C) 0
Bytes: 3
Cycles: 2
Encoding: 1 0 1 1 0 1 0 1 direct address rel. address
37
Encoding: 1 0 1 1 0 1 0 0 immediate data rel. address
Encoding: 1 0 1 1 1 r r r immediate data rel. address

CJNE @Ri, #data, rel

Operation: (PC) (PC) + 3
if ((Ri)) < > data
then (PC) (PC) + relative offset
if ((Ri)) < data
then (C) 1
else (C) 0
Bytes: 3
Cycles: 2
Encoding: 1 0 1 1 0 1 1 i immediate data rel. address

CLR A
Function: Clear accumulator
Description: The accumulator is cleared (all bits set to zero). No flags are affected.
Example: The accumulator contains 5CH (01011100B). The instruction
CLR A
will leave the accumulator set to 00H (00000000B).
Operation: CLR
(A) 0
Bytes: 1
Cycles: 1
Encoding: 1 1 1 0 0 1 0 0

CLR bit
38
Function: Clear bit
Description: The indicated bit is cleared (reset to zero). No other flags are affected.
CLR can operate on the carry flag or any directly addressable bit. Example: Port 1
has previously been written with 5DH (01011101B). The instruction
CLR P1.2
will leave the port set to 59H (01011001B).

CLR C
Operation: CLR
(C) 0
Bytes: 1
Cycles: 1

CLR bit
Operation: CLR
(bit) 0
Bytes: 2
Cycles: 1
Encoding: 1 1 0 0 0 0 1 1
Encoding: 1 1 0 0 0 0 1 0 bit address

CPL A
Function: Complement accumulator
Description: Each bit of the accumulator is logically complemented (ones
complement). Bits which previously contained a one are changed to zero and vice
versa. No flags are
affected.
39
Example: The accumulator contains 5CH (01011100B). The instruction
CPL A
will leave the accumulator set to 0A3H (10100011 B).
Operation: CPL
(A) (A)
Bytes: 1
Cycles: 1
Encoding: 1 1 1 1 0 1 0 0

CPL bit
Function: Complement bit
Description: The bit variable specified is complemented. A bit which had been a
one is changed to zero and vice versa. No other flags are affected. CPL can operate
on the carry or any directly addressable bit.
Note:
When this instruction is used to modify an output pin, the value used as the
original data will be read from the output data latch, not the input pin.
Example: Port 1 has previously been written with 5DH (01011101B). The
instruction sequence
CPL P1.1
CPL P1.2
will leave the port set to 5BH (01011011B).

CPL C
Operation: CPL
(C) (C)
Bytes: 1
40
Cycles: 1

CPL bit
Operation: CPL
(bit) (bit)
Bytes: 2
Cycles: 1
Encoding: 1 0 1 1 0 0 1 1
Encoding: 1 0 1 1 0 0 1 0 bit address

DA A
Function: Decimal adjust accumulator for addition
Description: DA A adjusts the eight-bit value in the accumulator resulting from the
earlier addition of two variables (each in packed BCD format), producing two four-
bit digits. Any ADD or ADDC instruction may have been used to perform the
addition.
If accumulator bits 3-0 are greater than nine (xxxx1010-xxxx1111), or if the AC
flag
is one, six is added to the accumulator producing the proper BCD digit in the low
order
nibble. This internal addition would set the carry flag if a carry-out of the low order
four-bit field propagated through all high-order bits, but it would not clear the carry
flag otherwise.
If the carry flag is now set, or if the four high-order bits now exceed nine
(1010xxxx-
1111xxxx), these high-order bits are incremented by six, producing the proper
BCD digit in the high-order nibble. Again, this would set the carry flag if there was
41
a carryout of the high-order bits, but wouldnt clear the carry. The carry flag thus
indicates if the sum of the original two BCD variables is greater than 100, allowing
multiple precision decimal additions. OV is not affected.
All of this occurs during the one instruction cycle. Essentially; this instruction
performs the decimal conversion by adding 00H, 06H, 60H, or 66H to the
accumulator, depending on initial accumulator and PSW conditions.
Note:
DA A cannot simply convert a hexadecimal number in the accumulator to BCD
notation, nor does DA A apply to decimal subtraction.
Example: The accumulator holds the value 56H (01010110B) representing the
packed BCD digits of the decimal number 56. Register 3 contains the value 67H
(01100111B)
representing the packed BCD digits of the decimal number 67. The carry flag is
set.
The instruction sequence
ADDC A, R3
DA A
will first perform a standard twos-complement binary addition, resulting in the
value
0BEH (10111110B) in the accumulator. The carry and auxiliary carry flags will be
cleared.
The decimal adjust instruction will then alter the accumulator to the value 24H
(00100100B), indicating the packed BCD digits of the decimal number 24, the low
order

4. SOLDERING

42
 Soldering is the process of joining two metallic conductors the joint where
two metal conductors are to be joined or fused is heated with a device called
soldering iron and then as allow of tin and lead called solder is applied which melts
and converse the joint. The solder cools and solidifies quickly to ensure is good
and durable connection between the jointed metal converting the joint solder also
present oxidation.

How to Solder
Soldering is very important for assembling any electronic circuit. A properly
soldered joint or connection in electronic circuit is the important stops to be
followed circuit in good and concerned soldering.
1. Use of coned type of soldering iron and solder avoid the use of excessive
fault.
2. Keep the soldering iron hot during the working period and let it rest on its
stand when not in use.
3. All components leads and wires should be thoroughly cleared to remove
dust and rust before soldering.
4. Enough heat is applied to the joint so that the solder metal flows freely over
the joint.
5. Over heating of components in PCB is avoided, over heating may result in
damage to components on PCB.

43
 5. IC 7805 :

5.1 Three Terminal Positive Fixed Voltage Regulators

44
 These voltage regulators are monolithic integrated circuits designed as fixed
voltage. These regulators employ internal current limiting, thermal shutdown, and
safe-area compensation. With adequate heat sinking they can deliver output
currents in excess of 1.0A. Although designed primarily as a fixed voltage
regulator, these devices can be used with external components to obtain adjustable
voltages and currents.
Output Current in Excess of 1.0A
No external components required
Internal thermal overload protection
Internal short circuit current limiting
Output transistor safe area compensation
Output voltage offered in 2% and 4% tolerance

Available in surface mount D2pAK and standard 3-lead transistor packages

Previous commercial temperature range has been extended to a junction
temperature range of 40C to +125C

5.2 MAXIMUM RATING :

Absolute Maximum Rating :

Parameter Symbol Value Unit
Input Voltage (for VO = 5V to VI 35 V
18V) VI 40 V
(for VO =24V)
Thermal Resistance, Junction to RJC 5 C/W
Cases (TO-220)
Thermal Resistance, Junction to RJC 65 C/W
Air (TO-220)
Operating Temp. Range TOPR 0 - +125 C
Storage Temp. Range TSTG -65 - +150 C

45
 5.3 ELECTRICAL CHARACTERISTICS :

Electrical Characteristics (TA = 25C unless otherwise noted)

Parameter Symbo Mi Type Max Unit
l n. .
Output Voltage TJ =+25C VO 4.8 5.0 5.2 V
Line Regulation (Note 1) Reglin - 4.0 100 MV
VO =7V to 25V e
Load Regulation (Note 1) Regloa - 9 100 MV
IO = 5.0mA to 1.5A d
Quiescent Current TJ IQ - 5.0 8.0 mA
=+25C
Quiescent Current Change IQ - 0.03 0.5 mA
IO = 5.0mA to 1.0A
Output Voltage Drift VO/ - -0.8 - MV/
IO = 5.0mA T C
Output Noise Voltage VN - 42 - V/V
f=10Hz to 100MHz, O
TA=+25C
Ripple Rejection RR 62 73 - dB
f=120Hz, VO=8V to 18V
Dropout Voltage VDrop - 2 - V
IO = 1A, TA=+25C
Output Resistance rO - 15 - m
f=1KHz
Short Circuit Current ISC - 230 - MA
VI = 35V, TA=+25C
Peak Current IPK - 2.2 - A
TA=+25C

46
 NOTE : Load and line regulation are specified at constant junction

temperature. Changes in VO due to heating effects must be taken into

account separately. Pulse testing with low duty is used.

47
 48
 6. FLOW CHART :

Start

Initialize the , LCD, Variables, Timers and Interruption

Measure and display the value

Automatic Controlling of Fan

Stop

APPLICATIONS:

Temperature Control is used in Auto Monitoring in Fan speed.

49
7. HARDWARE REQUIREMENTS

PCB
MICROCONTROLLER AT89S51
STEP DOWN TRANSFORMER 12V/500mA
VOLTAGE REGULATOR LM7805
RECTIFIER DIODES 1N4001
ELECTROLYTIC CAPACITORS
LCD DISPLAY
LEDs
SENSING ELECTRODES
OPERATIONAL AMPLIFIER
PVC WIRES
LM-35
IC - 0809

8. DEVELOPMENT TOOLS REQUIREMENTS

INTEGRATED DEVELOPMENT ENVIRONMENT
COMPILER, ASSEMBLER, SIMULATOR
EMULATOR, PROGRAMMER

50
 9. BIBLIOGRAPHY

1. Basic Electronics : By V.K. Mehta

2. Electronics Projects : By K.A. Sakthidharan
3. Integrated Circuit : By K.R. Botkar
4. Switch And Protection : By B.V.S. Rao
5. Twisted Electronics Project : By M.D. Agrawal
6. Power Electronics : By S.M. Rai & M.S. Qureshi

APPENDIX

1. IC 7805
2. IC MT8870
3. IC 74154
4. IC 7447
5. IC UA741
6. IC UM9121B

51