SUBMITTING TO:ENGR.

SHAHZAD
SUBMITTING BY:AYESHA SADIQ(CIIT/FA14/BCE/035/ATK)
SUMMRA AROOJ(CIIT/FA14/BCE/022/ATK)
COURSE:DIGITAL SYSTEM DESIGN
LAB#NUMBER#03
IMPLEMENTATION OF 4BIT CARRY LOOK AHEAD ADDER USING GATE
LEVEL
OBJECTIVE:
(I)To familiarize with the working of carry look ahead adder at gate
level using Verilog hdl.
(ii)To minimize the delay in addition of 4bit input.
VERILOG CODING:
module CLA4BIT(sum,cout,a,b,c0);
input [3:0]a,b;
input c0;
output [3:0]sum;
output cout;
wire
G0,G1,G2,G3,p0,p1,p2,p3,w1,w2,w3,c1,c2,c3,w5,w6,w7,w8,w9,w10,w11,w12,w13,w
14;
and and1(G0,a[0],b[0]);// G0
and and2(G1,a[1],b[1]);// G1
and and3(G2,a[2],b[2]);// G2
and and4(G3,a[3],b[3]);// G3
xor xor1(p0,a[0],b[0]);// p0
xor xor2(p1,a[1],b[1]);// p1
xor xor3(p2,a[2],b[2]);// p2
xor xor4(p3,a[3],b[3]);// p3

and and5(w1,p0,c0);
or or1(c1,G0,w1); // c1 interms of c0
or ora(w9,w1,G0);
and anda(w10,p1,w9);
or or2(c2,G1,w10); // c2 in terms of c0

and andc(w11,p1,p0,c0);
and andd(w12,p1,G0);
or orb(w13,G1,w12,w11);
and ande(w14,p2,w13);
or or3(c3,G2,w14); // c3 in terms of c0

and and8(w5,p3,G2);
and and9(w6,p3,p2,G1);
and and10(w7,p3,p2,p1,G0);
and and11(w8,p3,p2,p1,p0,c0);
or or5(cout,G3,w5,w6,w7,w8); //cout in terms of c0

xor xor5(sum[0],a[0],b[0],c0); // sum0

xor xor6(sum[1],a[1],b[1],c1); // sum1
xor xor7(sum[2],a[2],b[2],c2); //sum2
xor xor8(sum[3],a[3],b[3],c3); // sum3
endmodule

RTL SCHEMATIC:
TEST BENCH:
initial begin
a = 4'b1111; // Initialize Inputs
b = 4'b1111;
c0 = 0;
#100; // Wait 100 ns for global reset to finish
a= 4'b0110;
b= 4'b0110;
c0=0;
end
endmodule

WAVEFORM: