LISTOFEXPERIMENTSFORDIGITALELECTRONICSCIRCUITLAB(DEC):

Sl. No Experiments Equipment List

1 To design and implement the logic gates (AND, OR, NOT, NAND, NOR) using
discrete components.

2. To (a) Minimize a Boolean function using Boolean Algebra and Karnaugh map
and verify the same using truth table. (b) Implement the circuit(s) with suitable
ICs.
3. To (a) Implement and test Half Adder using AND, OR, NOT gates. (b)
Implement and test Half adder using XOR, AND gates. (c) Realize Full adder
using two Half adders
4 To (a) Realize and test Half subtractor and full subtractor(b) design and
implement 4 bit adder/ subtractor for 2s complement binary number system (c)
Design a carry look ahead adder.

5 To (a) design and test 3 bit to 8 level bar-graph generator, (b) convert an octal
key to binary key, (c) design and test a divide by 2 circuit with one additional
control input
6. To (a) design a circuit to display in decimal a 2-bit binary number using 7-
segment display, (b) design a 5 input 1-output circuit to detect even parity of
input bits and display the output using 7-segment display
Digital Storage Oscilloscope, Function
7 To (a) design an excess-3 to BDC converter.. (b) Design a comparator for two 4- Generator, Universal trainer kit, IC
bit unsigned binary numbers to generate equality, greater than and less than Tester
logic output.

8. To (a) Implement and test a 4:1 multiplexer (MUX), (b) Implement and test a
1:4 demultiplexer, (c) cascade the above two units and test, (d) Replace MUX in
IC.

9 Familiarization with sequential circuits (a) NAND only SR Flip-flop, (b) NOR
only S-R flip-flop, (c) Gated SR Flip-flop and D Flip-flop, (d) Master slave JK
Flip-flop with NAND gates

10 To implement 3-bit shift registers (a) parallel in parallel out, (b) parallel in serial
out, (c) serial in parallel out, (d) serial in serial out using JK Flip-Flops.

11 To implement 3 bit (a) up counter, (b) down counter, (c) up-down counter, (d)
decade counter with count sequence 0 to 9.

12 To (a) Design and implement a mod-5 synchronous counter with a particular

state sequence using D-Flip Flop. (b) Design and test Johnson counter.

Datasheets: BC-548, BC-549, IC-7404 (NOT), IC-7486 (XOR), IC-7432 (OR), IC-7408 (AND), IC-74151 (MUX), IC-
7486 (XOR), LT543, IC-7448, IC-7402 (NOR), IC-7400 (NAND), IC-7473 (J-K FF), IC-7474 (D FF).

Text Book: Digital Logic and Computer Design by M. Morris Mano

Experiment 1:

Objective:
To design and implement the logic gates (AND, OR, NOT, NAND, NOR) using discrete components.

Theory Questions:
1. What are the application and importance of logic gates?
2. Write down truth tables for each basic gates and how can it be represented in Venn diagram?

Description:
1. Draw the circuit diagram realization of gates with basic circuit components like diodes, transistors, resistors etc.
2. List the required components and equipment for implementation.
3. Implement each circuits separately and verify truth table.
4. Write down your conclusion from this experiment.

Experiment 2:

Objective:
To (a) Minimize a Boolean function using Boolean algebra and Karnaugh map (K-map) and verify the same using truth
table. (b) Implement the circuit(s) with suitable ICs.

Theory Questions:
1. What are the postulates and theorems of Boolean algebra?
2. Why is it necessary to minimize any Boolean expression?
3. What are procedures to draw K-map?
4. `
5. 1Why are five- and six- variables K-maps not popular?

Description:
1. Minimize f(x,y,z)=xy+yz+xz+xy+yz and f(a,b,c)= (0,1,2,3,4,5). Use K-map and Boolean algebra as
appropriate.
2. List the required components and equipment for implementation.
3. Implement both circuits separately and verify truth table.
4. Write down your conclusion from this experiment.

Experiment 3:

Objective:
To (a) Implement and test Half Adder using AND, OR, NOT gates. (b) Implement and test Half adder using XOR, AND
gates. (c) Realize Full adder using two Half adders

Theory Questions:
1. What do you mean by combinational logic circuit and what are its design steps?
2. What are the difference between half adder and full adder?
3. Why are NAND and NOR gates are known as universal gates?
4. Is it possible to implement Half and full adder with NAND/NOR gates?

Description:
1. Write truth table of half adder and Full adder.
2. Realize the Half Adder using AND, OR, NOT and using XOR, AND gates separately. Realize Full adder using two
Half adders
3. List the required components and equipment for implementation.
4. Implement above circuits separately and verify their respective functionality.
5. Write down your conclusion from this experiment.

Experiment 4:

Objective:
To (a) Realizeand test half subtractor and full subtractor (b) design 4 bit adder/ subtractor for 2s complement binary number
system (c) Design a carry look ahead adder.

Theory Questions:
1. What are the differences between 2s complement and 1s complement?
2. What are specialty of carry look ahead adder? Explain its functionality with detailed block diagram.

Description:
1. Write truth table of half subtractor and Full subtractor and realize them with basic gates.
2. Design a 4-bit parallel adder/subtractor with a select input to decide addition or subtraction.
3. Design a carry look ahead adder.
4. List the required components and equipment for implementation.
5. Implement above circuits separately and verify their respective functionality.
6. Write down your conclusion from this experiment.

Experiment 5:

Objective:
To (a) design and test 3 bit to 8 level bar-graph generator, (b) convert an octal key to binary key, (c) design and test a divide
by 2 circuit with one additional control input

Theory Questions:
1. How does a 3 bit to 8 level bar graph generator work? What are its applications?
2. Explain the operation of octal key to binary key conversion.

Description:
1. Write truth table for 3 bit to 8 level bar graph generator and realize the same with Boolean expression.
2. Write truth table for an octal key to binary key converter.
3. Design a divide by 2 circuit with 3-bit input and 3-bit output and a remainder y with a control input c. If c=1, it
generates quotients and reminders, if c=0, it passes the input to the output.
4. List the required components and equipment for implementation.
5. Implement above circuits separately and verify their respective functionality.
6. Write down your conclusion from this experiment.

Experiment 6:

Objective:
To (a) design a circuit to display in decimal a 2-bit binary number using 7-segment display, (b) design a 5 input 1-output
circuit to detect even parity of input bits and display the output using 7-segment display

Theory Questions:
1. What is 7-segment display and how does it work?
2. What are the requirements for even parity bit detection?
3. What do you mean by decoder and encoder?

Description:
1. Write the truth table for the circuit to display in decimal a 2-bit binary number using LT543 7-segment display and
realize the circuit.
2. Write truth table for 5 input 1-output circuit to detect even parity of input bits with variations in one of the input
bit say in LSB. Realize the circuit.
3. List the required components and equipment for implementation.
4. Implement above circuits separately and display the output using LT543 7-segment display.
5. Write down your conclusion from this experiment.

Experiment 7:

Objective:
To (a) design an excess-3 to BDC converter.. (b) Design a comparator for two 4-bit unsigned binary numbers to generate
equality, greater than and less than logic output.
Theory Questions:
1. Why are the requirements for code conversion?
2. What are the advantages of excess-3 code?
3. Highlight few applications for comparators?

Description:
1. Write the truth table for an excess-3 to BDC converter and realize the circuit for displaying in seven segment
display in decimal using IC 7448.
2. Design a comparator for two 4-bit unsigned binary numbers. Display the output a three bit output: A<B, A=B,
A>B
3. List the required components and equipment for implementation.
4. Implement above circuits separately and display the output using LT543 7-segment display.
5. Write down your conclusion from this experiment.

Experiment 8:

Objective:
To (a) Implement and test a 4:1 multiplexer (MUX), (b) Implement and test a 1:4 demultiplexer, (c) cascade the above two
units and test, (d) Replace MUX in IC.

Theory Questions:
1. Why are the difference between decoder and demultiplexer?
2. Indicate few applications for MUX?

Description:
1. List the required components and equipment for the following implementations.
2. Implement (with AND-OR-NOT gates) and test a 4:1 multiplexer (MUX)
3. Implement (with AND-OR-NOT gates) and test a 1:4 demultiplexer.
4. Cascade the above two units and test.
5. Replace MUX in above (point 4) with IC 74151 and test.
6. Write down your conclusion from this experiment.

Experiment 9:

Objective:
Familiarization with sequential circuits (a) NAND only SR Flip-flop, (b) NOR only S-R flip-flop, (c) Gated SR Flip-flop and
D Flip-flop, (d) Master slave JK Flip-flop with NAND gates

Theory Questions:
1. How are the sequential circuits different from combinational circuits?
2. What is the difference between latch and Flip-flop?
3. How do you represent flip-flop excitation tables for RS-, JK-, D-, T-Flip flop?

Description:
1. Write the truth table for SR Flip-flop and realize the circuit with only NAND gates and only NOR gates.
2. Write the truth table for Gated SR Flip-flop, D flip-flop and realize a Master slave JK flip-flop with NAND gates.
3. List the required components and equipment for implementation.
4. Implement above circuits separately and verify the truth tables.
5. Write down your conclusion from this experiment.

Experiment 10:

Objective:
To implement 3-bit shift registers (a) parallel in parallel out, (b) parallel in serial out, (c) serial in parallel out, (d) serial in
serial out using JK Flip-Flops.
Theory Questions:
1. What do you mean by unidirectional and bidirectional shift register using suitable diagram?
2. What is the operating principle of a serial adder?

Description:
1. Write the state diagram 3-bit shift registers (a) parallel in parallel out, (b) parallel in serial out, (c) serial in parallel
out, (d) serial in serial out
2. Realize the circuit with JK flip-flop.
3. List the required components and equipment for implementation.
4. Implement above circuits separately and verify the state diagrams. Display the same in 7 segment display.
5. Write down your conclusion from this experiment.

Experiment 11:

Objective:
To implement 3 bit (a) up counter, (b) down counter, (c) up-down counter, (d) decade counter with count sequence 0 to 9.

Theory Questions:
1. What do you mean by state diagram of a circuit?
2. What is the design procedure of a clocked sequential circuit?

Description:
6. Write the state diagram of up counter, down counter, up-down counter and decade counter.
7. Realize the circuit with T- flip flop and JK flip-flop.
8. List the required components and equipment for implementation.
9. Implement above circuits separately and verify the state diagrams. Display decade counter in 7 segment display.
10. Write down your conclusion from this experiment.

Experiment 12:

Objective:
To (a) Design and implement a mod-5 synchronous counter with a particular state sequence using D-Flip Flop. (b) Design
and test Johnson counter.

Theory Questions:
3. What do you mean ring counter? Where are the ring counter used?
4. How to realize a Johnson counter?

Description:
1. Write the state diagram of a mod-5 synchronous counter with state sequence 2, 3, 0, 7, 6 and corresponding
excitation table.
2. Realize the circuit with using D-Flip Flop and JK flip-flop.
3. List the required components and equipment for implementation.
4. Implement above circuits separately and verify the state diagrams. Display the same in 7 segment display.
5. Write down your conclusion from this experiment.