Chapter 6: Hierarchical Structural Modeling

Chapter 6: Hierarchical Structural

Modeling

Prof. Ming-Bo Lin

Department of Electronic Engineering

National Taiwan University of Science and Technology

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-1
 Chapter 6: Hierarchical Structural Modeling

Syllabus
Objectives
Module
Module definitions
Parameters
Module instantiation
Module parameter values
Hierarchical path names
Generate statements
Generate-loop statement
Generate-conditional statement
Generate-case statement

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-2
 Chapter 6: Hierarchical Structural Modeling

Syllabus
Objectives
Module
Generate statements

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-3
 Chapter 6: Hierarchical Structural Modeling

Objectives
After completing this chapter, you will be able to:
Describe the features of hierarchical structural
modeling in Verilog HDL
Describe the features of Verilog modules
Describe how to define and override the parameters
within a module
Describe the port connection rules
Describe how to write a parameterized module
Describe how to use generate block statements

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-4
 Chapter 6: Hierarchical Structural Modeling

Syllabus
Objectives
Module
Module definitions
Parameters
Module instantiation
Module parameter values
Hierarchical path names
Generate statements

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-5
 Chapter 6: Hierarchical Structural Modeling

Module Definitions

// port list style

module module_name [#(parameter_declarations)][port_list];
parameter_declarations; // if no parameter ports are used
port_declarations;
other_declaration;
statements;
endmodule

// port list declaration style

module module_name [#(parameter_declarations)][port_declarations];
parameter_declarations; // if no parameter ports are used
other_declarations;
statements;
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-6
 Chapter 6: Hierarchical Structural Modeling

Port Declarations
Three types
input
net net
output net
net
inout variable net net
variable

module adder(x, y, c_in, sum, c_out);

input [3:0] x, y;
input c_in;
output reg [3:0] sum;
output reg c_out;

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-7
 Chapter 6: Hierarchical Structural Modeling

Syllabus
Objectives
Module
Module definitions
Parameters
Module instantiation
Module parameter values
Hierarchical path names
Generate statements

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-8
 Chapter 6: Hierarchical Structural Modeling

Types of Parameters
module parameters
parameter
localparam
specify parameters

parameter SIZE = 7;
parameter WIDTH_BUSA = 24, WIDTH_BUSB = 8;
parameter signed [3:0] mux_selector = 4b0;

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-9
 Chapter 6: Hierarchical Structural Modeling

Constants Specified Options

`define compiler directive
`define BUS_WIDTH 8
Parameter
parameter BUS_WIDTH = 8;
localparam
localparam BUS_WIDTH = 8;

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-10
 Chapter 6: Hierarchical Structural Modeling

Parameter Ports

module module_name
#(parameter SIZE = 7,
parameter WIDTH_BUSA = 24, WIDTH_BUSB = 8,
parameter signed [3:0] mux_selector = 4b0
)
(port list or port list declarations)
...
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-11
 Chapter 6: Hierarchical Structural Modeling

Syllabus
Objectives
Module
Module definitions
Parameters
Module instantiation
Module parameter values
Hierarchical path names
Generate statements

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-12
 Chapter 6: Hierarchical Structural Modeling

Module Instantiation
Syntax
module_name [#(parameters)]
instance_name [range]([ports]);
module_name [#(parameters)]
instance_name [{,instance_name}]([ports]);

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-13
 Chapter 6: Hierarchical Structural Modeling

Port Connection Rules

Named association
.port_id1(port_expr1),..., .port_idn(port_exprn)
Positional association
port_expr1, ..., port_exprn

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-14
 Chapter 6: Hierarchical Structural Modeling

Syllabus
Objectives
Module
Module definitions
Parameters
Module instantiation
Module parameter values
Hierarchical path names
Generate statements

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-15
 Chapter 6: Hierarchical Structural Modeling

Parameterized Modules
An example

module adder_nbit(x, y, c_in, sum, c_out);

parameter N = 4; // set default value
input [N-1:0] x, y;
input c_in;
output [N-1:0] sum;
output c_out;

assign {c_out, sum} = x + y + c_in;

endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-16
 Chapter 6: Hierarchical Structural Modeling

Module Parameters Values

Ways to change module parameters values
defparam statement
module instance parameter value assignment

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-17
 Chapter 6: Hierarchical Structural Modeling

Overriding Parameters
Using the defparam module counter_nbits (clock, clear, qout);
parameter N = 4; // define counter size
statement
always @(negedge clock or posedge clear)
begin // qout <= (qout + 1) % 2^n
if (clear) qout <= {N{1'b0}};
else qout <= (qout + 1) ;
End
// define top level module

output [3:0] qout4b;
output [7:0] qout8b;
// instantiate two counter modules
defparam cnt_4b.N = 4, cnt_8b.N = 8;
counter_nbits cnt_4b (clock, clear, qout4b);
counter_nbits cnt_8b (clock, clear, qout8b);
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-18
 Chapter 6: Hierarchical Structural Modeling

Overriding Parameters
module counter_nbits (clock, clear, qout);
Using module instance
parameter N = 4; // define counter size
parameter value
assignment--- always @(negedge clock or posedge clear)
begin // qout <= (qout + 1) % 2^n;
one parameter if (clear) qout <= {N{1'b0}};
else qout <= (qout + 1) ;
end

// define top level module

output [3:0] qout4b;
output [7:0] qout8b;
// instantiate two counter modules
counter_nbits #(4) cnt_4b (clock, clear, qout4b);
counter_nbits #(8) cnt_8b (clock, clear, qout8b);
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-19
 Chapter 6: Hierarchical Structural Modeling

Overriding Parameters
Using module // define top level module
instance module
parameter value
hazard_static #(4, 8) example (x, y, z, f);
assignment
--- two parameters
hazard_static #(.delay2(4), .delay1(6))
example (x, y, z, f);
module hazard_static (x, y, z, f);
parameter delay1 = 2, delay2 = 5; parameter value assignment by name ---
minimize the chance of error!
and #delay2 a1 (b, x, y);
x a
not #delay1 n1 (a, x); y
and #delay2 a2 (c, a, z); f
or #delay2 o2 (f, b, c);
b
endmodule z

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-20
 Chapter 6: Hierarchical Structural Modeling

Syllabus
Objectives
Module
Module definitions
Parameters
Module instantiation
Module parameter values
Hierarchical path names
Generate statements

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-21
 Chapter 6: Hierarchical Structural Modeling

Hierarchical Path Names

An identifier can be defined within
Modules
Tasks
Functions
Named blocks (See Section 7.1.3)
Hierarchical path names
4bit_adder // top level --- 4bit_adder
4bit_adder.fa_1 // fa_1 within 4bit_adder
4bit_adder.fa_1.ha_1 // ha_1 within fa_1
4bit_adder.fa_1.ha_1.xor1 // xor1 within ha_1
4bit_adder.fa_1.ha_1.xor1.S // net s within xor1

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-22
 Chapter 6: Hierarchical Structural Modeling

Syllabus
Objectives
Module
Generate statements
Generate-loop statements
Generate-conditional statements
Generate-case statements

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-23
 Chapter 6: Hierarchical Structural Modeling

generate Block Structures

The keywords used
generate and endgenerate

// convert Gray code into binary code

parameter SIZE = 8;
input [SIZE-1:0] gray;
output [SIZE-1:0] bin;
genvar i;
generate for (i = 0; i < SIZE; i = i + 1) begin: bit
assign bin[i] = ^gray[SIZE-1:i];
end endgenerate

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-24
 Chapter 6: Hierarchical Structural Modeling

The generate Loop Construct

// convert Gray code into binary code

parameter SIZE = 8;
input [SIZE-1:0] gray;
output [SIZE-1:0] bin;
reg [SIZE-1:0] bin;

genvar i;
generate for (i = 0; i < SIZE; i = i + 1) begin:bit
always @(*)
bin[i] = ^gray[SIZE - 1: i];
end endgenerate

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-25
 Chapter 6: Hierarchical Structural Modeling

Syllabus
Objectives
Module
Generate statements
Generate-loop statements
Generate-conditional statements
Generate-case statements

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-26
 Chapter 6: Hierarchical Structural Modeling

An n-bit Adder

// define a full adder at dataflow level.

module full_adder(x, y, c_in, sum, c_out);
// I/O port declarations
input x, y, c_in;
output sum, c_out;
// Specify the function of a full adder.
assign {c_out, sum} = x + y + c_in;
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-27
 Chapter 6: Hierarchical Structural Modeling

An n-bit Adder
module adder_nbit(x, y, c_in, sum, c_out);

genvar i;
wire [N-2:0] c; // internal carries declared as nets.
generate for (i = 0; i < N; i = i + 1) begin: adder
if (i == 0) // specify LSB
full_adder fa (x[i], y[i], c_in, sum[i], c[i]);
else if (i == N-1) // specify MSB
full_adder fa (x[i], y[i], c[i-1], sum[i], c_out);
else // specify other bits
full_adder fa (x[i], y[i], c[i-1], sum[i], c[i]);
end endgenerate

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-28
 Chapter 6: Hierarchical Structural Modeling

An n-bit Adder

module adder_nbit(x, y, c_in, sum, c_out);

genvar i;
wire [N-2:0] c; // internal carries declared as nets.
generate for (i = 0; i < N; i = i + 1) begin: adder
if (i == 0) // specify LSB
assign {c[i], sum[i]} = x[i] + y[i] + c_in;
else if (i == N-1) // specify MSB
assign {c_out, sum[i]} = x[i] + y[i] + c[i-1];
else // specify other bits
assign {c[i], sum[i]} = x[i] + y[i] + c[i-1];
end endgenerate

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-29
 Chapter 6: Hierarchical Structural Modeling

An n-bit Adder
module adder_nbit(x, y, c_in, sum, c_out);

genvar i;
reg [N-2:0] c; // internal carries declared as nets.
generate for (i = 0; i < N; i = i + 1) begin: adder
if (i == 0) // specify LSB
always @(*) {c[i], sum[i]} = x[i] + y[i] + c_in;
else if (i == N-1) // specify MSB
always @(*) {c_out, sum[i]} = x[i] + y[i] + c[i-1];
else // specify other bits
always @(*) {c[i], sum[i]} = x[i] + y[i] + c[i-1];
end endgenerate

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-30
 Chapter 6: Hierarchical Structural Modeling

A Twos Complement Adder

module twos_adder_nbit(x, y, mode, sum, c_out);

genvar i;
wire [N-2:0] c; // internal carries declared as nets.
wire [N-1:0] t; // true/ones complement outputs
generate for (i = 0; i < N; i = i + 1) begin:
// ones_complement_generator
xor xor_ones_complement (t[i], y[i], mode);
end endgenerate

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-31
 Chapter 6: Hierarchical Structural Modeling

A Twos Complement Adder

generate for (i = 0; i < N; i = i + 1) begin: adder

if (i == 0) // specify LSB
full_adder fa (x[i], t[i], mode, sum[i], c[i]);
else if (i == N-1) // specify MSB
full_adder fa (x[i], t[i], c[i-1], sum[i], c_out);
else // specify other bits
full_adder fa (x[i], t[i], c[i-1], sum[i], c[i]);
end endgenerate

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-32
 Chapter 6: Hierarchical Structural Modeling

A Twos Complement Adder

The RTL schematic from Synplify Pro.

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-33
 Chapter 6: Hierarchical Structural Modeling

A Twos Complement Adder

After dissolving the second and the third bits

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-34
 Chapter 6: Hierarchical Structural Modeling

Syllabus
Objectives
Module
Generate statements
Generate-loop statements
Generate-conditional statements
Generate-case statements

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-35
 Chapter 6: Hierarchical Structural Modeling

The generate Case Construct

generate for (i = 0; i < N; i = i + 1) begin: adder

case (i)
0: assign {c[i], sum[i]} = x[i] + y[i] + c_in;
N-1: assign {c_out, sum[i]} = x[i] + y[i] + c[i-1];
default: assign {c[i], sum[i]} = x[i] + y[i] + c[i-1];
endcase
end endgenerate

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-36
 Chapter 6: Hierarchical Structural Modeling

A UDP Example
// an example of sequential UDP instantiations
parameter N = 4;
input clk, clear;
output [N-1:0] qout;
.
genvar i;
generate for (i = 0; i < N; i = i + 1) begin: ripple_counter
if (i == 0) // specify LSB
T_FF tff (qout[i], clk, clear);
else // specify the rest bits
T_FF tff (qout[i], qout[i-1], clear);
end endgenerate

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-37