8D02E

SPECIFICATION FOR APPROVAL
CUSTOMER: _
PART TYPE: Integrated circuit _
PART NAME: 8D02E _
APPROVED BY

8Digit Technology Inc.
167 16
TEL: 886-3-5945532; FAX: 886-3-5111463
Mobile: 886-928-062098; fckuo.mail@msa.hinet.net
8Digit 8D02E TFT-LCD controller 5/10/2006 2/20
CONTROLLER IC8D02E
TARGET SPECIFICATION
Contents
1. General description ---------------------------------------------------------------------------------- 3
2. Features ----------------------------------------------------------------------------------------------- 3
3. Pin assignments ----------------------------------------------------------------------------------- 4
4. Block diagram --------------------------------------------------------------------------------------- 5
5. Pin description -------------------------------------------------------------------------------------- 6
6. Mode selection ------------------------------------------------------------------------------------ 8
7. DC electrical characteristics -----------------------------------------------------------------------15
8. AC electrical characteristics ---------------------------------------------------------------------- 16
9. Horizontal timing waveform ----------------------------------------------------------------------- 17
10. Vertical timing waveform ---------------------------------------------------------------------- 18
11. Package outline dimension --------------------------------------------------------------------- 19
This technical specification is subject to change without notice.
The information contained herein is the exclusive property of 8Digit Technology Inc. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of 8Digit Technology Inc.
,,,
TFT-LCD CONTROLLER
MAY 2006, Version E
1. General Description
The 8D02E is a timing controller for small analog TFT-LCD panel. It provides horizontal and
vertical control timing to TFT-LCD source and gate drivers. The controller has built-in phase
lock loop system, which can synchronize the master clock with the horizontal and vertical sync.
signals from a classical TV system.
2. Features
Support 16 kinds of 16:9 display mode.
Support 8 kinds of horizontal display resolution mode, from 240 to 2880.
Support 2 kinds of vertical display resolution mode, from 234 to 468.
Master clock frequency: 28.9 MHz max.
Including master clock frequencies divide by 2 function, and half function.
Acceptable the external & internal master clock input.
Acceptable the external & internal vertical sync. input.
Auto-detect NTSC/PAL TV system.
Auto-detect input synchronization signal polarity.
Separate VCO & H-POS adjustment.
Support both stripe and delta color arrangement
V-POS maximum 15 lines adjustment
Support 2 kinds of vertical overlap method.
Provides source and gate drivers control timing.
Shift clock signals for the source driver (3-phase Clock).
Provides control signals for external RGB decoder & AMP.
Provides flip and mirror scan control.
Line inverse driving scheme as vertical resolution is 234.
Column inverse driving scheme as vertical resolution is 468.
Single supply voltage: +5V or +3.3V.
LQFP 64 pins package
Note: The red color is the difference between 8D02D & 8D02E.
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3. Pin assignment
8D02E
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4. Block diagram
8D02E
D VP1-4 UD RL
V-POS UP-DOWN Right_Left

control control control
HSY Hsync IO
control
SV1-2
OE1-3
VSY Vsync IO o CPV
Counter
control RST
Q1H
Control
NTSC/PAL CP1-3
NPC Mode control SH1-2
control
OEH
FRP FRP,COM
COM control
o OSI
1-4 Counter
control Osc
OSO
RS1-4 Resolution
control
CSY PD HPI HPO
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5. Pin description
64 PIN FUNCTION DESCRIPTION - 1

Pin Name I/O Description Remark
1 VCC Power supply Note 1
2 CSY I Composite sync. Or external clock input pin
3 RS4 I Resolution mode setting pin 4 Note 2
7 DM4 I Display mode setting pin 4 default=1
11 SDC I Color arrangement mode selection pin,Stripe=1,Delta=0 default=1
12 DLT I Delta & DLT=0 (SDC=1) display modes selection pin default=1
13 HPO O H-POS position adjustment output signal
14 HPI I H-POS position adjustment input signal
15 PDA O Phase detect A output pin
16 CKC I Control HSY & VSY pin for select I/O direction default=1
17 OSO O Oscillator output pin
18 OSI I Oscillator input pin
19 FD2 I Master clock frequency divide by 2 or Half function. default=1
20 NC1 I/O Test pin 1 for output PDB, or input pin external clock Note #
21 ZMI I Connect capacitor to ground
22 ZMO O Connect Resistor to pin 21.
23 CBG I Simultaneous CP2, CP3 sampling clock select pin default=1
24 SAM I Simultaneous(1) or sequential(0) sampling select pin default=0
25 RLC I Source driver shift right/left select pin default=1
26 OEH O Source driver control signal
27 SH2 O Horizontal start pulse 2 for source driver (RLC=0,OUT)
28 SH1 O Horizontal start pulse 1 for source driver (RLC=1,OUT)
29 CP3 I/O Sampling clock 3 to source driver, or ext. HSY input Note #
30 CP2 I/O Sampling clock 2 to source driver, or ext. VSY input Note #
31 CP1 O Sampling clock 1 output to source driver
32 GND Ground
Note 1: a. All VCC should be 5V, when all I/O is 5V swing.
b. All VCC should be 3.3V, when all I/O is 3.3V swing.
Note 2: These input pins have no default value, must connect to VCC or GND.
Note #: Please contact 8Digit FC Kuo. +886-928-062098; +886-3-5111463
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64 PIN FUNCTION DESCRIPTION - 2

Pin Name I/O Description Remark
33 VCC Power supply Note 1
34 Q1H O Source driver control signal
35 RST O Vertical reset signal for source driver
36 CPV O Scan clock to gate driver
37 OE1 O Gate driver Scan output enable control
38 OE2 O Gate Scan output enable control, /OE1 (3OE=0,G24=1)
39 OE3 O Gate Scan output enable control, /OEH (3OE=0,G24=1)
40 NC2 I Test pin 2 for VCR or ext. clock switch. Note # default=0
41 SV1 O Vertical start pulse 1 for gate driver (UDC=1,OUT)
42 SV2 O Vertical start pulse 2 for gate driver (UDC=0,OUT)
43 UDC I Up/down scan direction select pin default=1
44 VP1 I Vertical position adjustment & overlap select pin (PVI=1) default=0
45 VP2 I Vertical position adjustment for display area default=0
48 POI I Power ON initialize; and UOB signal input Note 3
49 POD I Power ON delay; VCO adjust can connect to GND. Note 4
50 NC3 I Test pin 3 PWM signal Note 5
51 NPC O NTSC/PAL detect output & Control pin, NTSC=1,PAL=0 Note 6
52 NC4 I Test pin 4 PSI signal Note 5
53 G24 I Gate 240=1 or 244=0 select pin default=1
54 3OE I 3OEV=1 or 1OEV=0 select pin default=0
55 NC5 I Test pin 5 for PAL select default=1
56 VSY I/O Vertical sync. input/Negative output pin Pull high
57 HSY I/O Horizontal sync. input/ Negative output pin Pull high
58 BLK O Output for control RGB signal
59 ESY O Output external sync. for control chroma decoder
60 COM O Output VCOM polarity signal
61 FRP O Video polarity alternating signal
62 NC6 I Test pin 6 for PAL select default=1
63 VIY I Vertical sync. input, if no use please connect to GND. Note 2
64 GND Ground
Note 3: Connect C to GND for power ON initialize;
(If open, then POI will perform the auto initialize internally. A negative pulse UOB
Image down size on screen control signal can be input also.)
Note 4: Connect C to GND for power ON delay control; GND can help VCO adjustment.
Note 5: A negative polarity pulse needs a pull up resistor (50K).
Note 6: a. In normally, it is an auto-detect output pin. (Initial power ON 8D02E=0, 8D02D=1)
b. If connect to VCC directly, then it force to NTSC mode only.
c. If connect to GND directly, then it force to PAL mode only.
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6. Mode selection
This 8D02E controller IC specification applies to analog TFT-LCD module, for the following type
panels.
. Support 8 kinds of horizontal display resolution mode, from 240 to 2880. (Table 1)
H mode RS4 RS3 RS2 RS1 Resolution Master clock Tosc
480 0 0 0 0 480x234 9.6MHz 104ns
240 0 0 0 1 240x234 4.8MHz 208ns
480 0 0 1 0 480x468 9.6MHz 104ns
240 0 0 1 1 240x468 4.8MHz 208ns
1200 0 1 0 0 1200x468 24.1MHz 41.5ns
2400 0 1 0 1 2400x468 24.1MHz 41.5ns
1440 0 1 1 0 1440x468 28.9MHz 34.6ns
2880 0 1 1 1 2880x468 28.9MHz 34.6ns
960 1 0 0 0 960x234 19.2MHz 52ns
1920 1 0 0 1 1920x234 19.2MHz 52ns
960 1 0 1 0 960x468 19.2MHz 52ns
1920 1 0 1 1 1920x468 19.2MHz 52ns
1200 1 1 0 0 1200x234 24.1MHz 41.5ns
2400 1 1 0 1 2400x234 24.1MHz 41.5ns
1440 1 1 1 0 1440x234 28.9MHz 34.6ns
2880 1 1 1 1 2880x234 28.9MHz 34.6ns
Note: The frequency of master clock must be adjusted for keep PDA voltage average around the half of VCC.
. Acceptable the external & internal master clock input.

FD2 CKC Function Master clock HSY VSY
1 1 Internal clock OSI input output output
1 0 External clock CSY input input input
0 1 Internal clock OSI input * output output
0 0 Internal clock OSI input ^ input input
The frequency of the external master clock must be as same as the master clock frequency in table 1.
* Master clock frequency divide by 2 function when H-res. >= 1920. It is half when H-res. <= 1440.
^ CSY=external sampling clock input when SAM=1, and switch by NC2, (CSY, HSY, VSY to NC1, CP3, CP2); Note #.
.Acceptable input the separate sync. Or input the composite sync. (CKC=1)
Type Horizontal sync. input Pin 2 Vertical sync. input Pin 63
Composite sync. Internal CSY Internal GND
Separate sync. External HSY External VIY
. Support both stripe and delta color arrangement

SDC DLT Color arrangement Note
1 1 Stripe -
0 Stripe DLT Display modes
0 1 Delta type A The polarity of Q1H can be
(Max1440) inversed by SAM select pin
0 Delta type B
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. Provides flip and mirror scan control.

RLC SH1 SH2
1 Output Hi-z
0 Hi-z Output
UDC SV1 SV2

1 Output Hi-z
0 Hi-z Output
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. Support 16 kinds of 16:9 display mode.
16 Display modes DLT Mode (SDC=1 & DLT=0)

MODE DM4 DM3 DM2 DM1 Magnification Ratio Note Name DLT Mode
Mode 15 1 1 1 1 Full 1.33 16:9 Full screen 7FU Full
Mode 14 1 1 1 0 Wide 2 1.32 16:9 H 15 steps modify 6W2 Cinema1
Mode 13 1 1 0 1 Wide 1 1.14 Wide 1 center 5W1 C1+W6
Mode 12 1 1 0 0 Normal 1 Normal center 4NC Normal
Mode 11 1 0 1 1 x20, SDC=1 Stripe 2 2H,2V ( Zoom 2) 3ZM2 Cinema2
W4L, SDC=0 Delta 1.2 Wide 4 left 3W4L
Mode 10 1 0 1 0 x18, SDC=1 1.78 1.78H,1.78V center 2Z18 Wide 6
W4R, SDC=0 1.2 Wide 4 right 2W4R
Mode 9 1 0 0 1 Cinema1, SDC=1 1.33 1.33H,1.33V center 1C1 C2+W6
W3L, SDC=0 1.09 Wide 3 left 1W3L
Mode 8 1 0 0 0 Cinema2, SDC=1 1.33 1.33H,1.14V upper 0C2 Cinema2C
W3R, SDC=0 1.09 Wide 3 right 0W3R
Mode 7 0 1 1 1 Wide 6 1.31 16:9 H 9 steps modify 7W6 Cinema2
Mode 6 0 1 1 0 Cinema2C, SDC=1 1.33 1.33H,1.14V center 6C2C Normal_R
Full, SDC=0 1.33 16:9 Full screen 6FU
Mode 5 0 1 0 1 Wide 1 left 1.14 Wide 1 left 5W1L Normal_L
Mode 4 0 1 0 0 Normal left 1 Normal left 4NL C2C+W6
Mode 3 0 0 1 1 Wide 4 1.2 Wide 4 center 3W4 Cinema1
Mode 2 0 0 1 0 Wide 3 1.09 Wide 3 center 2W3 Wide 6
Mode 1 0 0 0 1 Wide1 right 1.14 Wide 1 right 1W1R Normal
Mode 0 0 0 0 0 Normal right 1 Normal right 0NR Full
W3 W1 W4
Normal
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D D D D
Display Display characteristics M M M M Note
Mode (4:3 aspect-ratio input) 4 3 2 1
4:3 Input signals are

Full H H H H displayed on the 16:9
(7FU) i i i i full screen
4:3 Input signals are displayed

Wide 2 H H H L on the 16:9 screen
(6W2) i i i o Horizontal modify 15 steps
Wide 1 H H L H 4:3 Input signals are

(5W1) i i o i displayed on the 16:9
screen in wide 1
center
Normal center 4:3 Input signals are

(4NC) H H L L displayed on the 16:9 screen
i i o o in normal center
4:3 Input signals of 117

lines are displayed in the
Zoom 2x
H L H H 16:9 screen center with zoom
(3ZM2)
i o i i 2 times
SDC=1, Color filter
arrangement is stripe

Zoom 1.78x lines are displayed in the
(2Z18) H L H L
16:9 screen center with zoom
i o i o
1.78 times
SDC=1, Color filter
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Display Display characteristics D D D D

Mode (4:3 aspect-ratio input) M M M M Note
4 3 2 1

Cinema 1 H L L H 16:9 screen center with zoom
Zoom 1.33x i o o i 1.33 times
(1C1) SDC=1, Color filter

Cinema 2 H L L L 16:9 screen center with
(0C2) i o o o cinema 2
SDC=1, Color filter
Wide 6 4:3 Input signals are

(7W6) L H H H displayed on the 16:9 screen
o i i i Horizontal modify 9 steps

16:9 screen with cinema 2
Cinema 2 L H H L center
center o i i o SDC=1, Color filter
(6C2C) arrangement is stripe
SDC=0, then Full mode

Wide 1 left L H L H displayed on the 16:9 screen
(5W1L) o i o i in wide 1 left

Normal left L H L L displayed on the 16:9 screen
(4NL) o i o o in normal left
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M M M M Note
Mode (4:3 aspect-ratio input)
4 3 2 1
Wide 4 center 4:3 Input signals are

(3W4) L L H H displayed on the 16:9 screen
o o i i in wide 4 center
Wide 3 center 4:3 Input signals are

(2W3) L L H L displayed on the 16:9 screen
o o i o in wide 3 center
Wide 1 right L L L H 4:3 Input signals are

(1W1R) o o o i displayed on the 16:9 screen
in wide 1 right
Normal right L L L L 4:3 Input signals are

(0NR) o o o o displayed on the 16:9 screen
in normal right
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M M M M Note
Mode (4:3 aspect-ratio input)
4 3 2 1

displayed on the 16:9 screen
Wide 4 left H L H H
in wide 4 left
(3W4L) i o i i
SDC=0, Color filter
arrangement is delta

Wide 4 right H L H L
in wide 4 right
(2W4R) i o i o
SDC=0, Color filter

Wide 3 left H L L H
in wide 3 left
(1W3L) i o o i
SDC=0, Color filter

Wide 3 right H L L L
in wide 3 right
(0W3R) i o o o
SDC=0, Color filter
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7. DC characteristics
1.Absolute maximum ratings:
SYMBOL PARAMETER RATING UNITS
VCC Power supply -0.3 to 6.0 V
VIN Input voltage -0.3 to VCC + 0.3 V
VOUT Output voltage -0.3 to VCC + 0.3 V
TSTG Storage temperature -40 to 125 oC
2. Recommended operating conditions:

SYMBOL PARAMETER MIN TYP MAX UNITS
VCC Power supply 3.0 3.3/5.0 5.5 V
VIN Input voltage 0 - VCC V
TOPR Operating temperature -30 - 85 oC
3. General DC characteristics:
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Remark
IIL Input low current no pull-up or -1 - 1 uA
pull-down
IIH Input high current no pull-up or -1 - 1 uA
pull-down
IOZ Tri-state leakage -10 - 10 uA
current
CIN Input capacitance - 3 - pF
COUT Output capacitance 3 - 6 pF
VIL Input low voltage CMOS - - 0.3Vcc V Note 1
VSIL Schmitt input low CMOS - 1.76 - V
voltage
VIH Input high voltage CMOS 0.7Vcc - - V Note 1
VSIH Schmitt input high CMOS - 3.2 - V
voltage
VOL Output low voltage IOL=4mA - - 0.4 V
VOH Output high voltage IOH=4mA 3.5 - - V
RI Input pull up/down VIL=0V or - 50 - Khom
resistance VIH=VCC
Note 1: The applicable pins are OSCI, VSY/I, Csync, HPI.
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8. AC characteristics
1. Timing condition
a. Input signal characteristics
Parameter Symbol Min. Typ. Max. Unit. Remark
Csync period Tosc Tosc-1 Tosc Tosc+1 ns Table 1
Csync period Th 61.5 63.5 65.5 s
Csync pulse width Tcsy 4 4.7 5.4 s
Csync rising time Tcr - - 700 ns
Csync falling time Tcf - - 300 ns
V-IN pulse width Tvsy 1 3 5 th
V-IN rising time Tvr - - 700 ns
V-IN falling Tvf - - 1.5 s
Horizontal lines per 257 262.5 268 line NTSC
field 307 312.5 318 line PAL
b. Output signal characteristics
Parameter Symbol Min. Typ. Max. Unit. Remark
rising time Tr - - 15 ns Note1
falling time Tf - - 15 ns Note1
Clock period Tcph - 3 - Tosc CP1~CP3
Clock pulse duty Tcwh 20 33.3 50 % CP1~CP3
3 clock phase Tc12 - 1/3 - Tcph
difference Tc23
Tc31
SH setup time Tsuh 0.5 - - Tcph
SH pulse width Tsth - 1 - Tcph
HSY pulse width Thsy - 4.7 - s
OEH pulse width Toeh 0.5 - - s
Start display time Tdis - 10.6 - s
OEV pulse width Toev 0.5 - - s
CPV pulse width Tcpv - 2.6 - s
HPO pulse width Thpo - 0.5 - Th
HSY-OEH Timing T1 - 1 - s
HSY-CPV Timing T2 - 2.0 - s
OEV-CPV Timing T3 - 2.5 - s
HSY-HPO Timing T4 - 2 - s
SV1,2 setup time Tsuv 0.5 - - Th
SV1,2 pulse width Tstv - 1 - Th
RST pulse width Trst 0.25 - - Th
VSY pulse width Tvsy - 4 - Th
VSY-RST timing Trs - 16 - Th
VSY-SV1,2 timing Tvs - 17 - Th
Note1: For all of logic signals & adjust the PDA voltage level=0.5VCC typically.
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9. Horizontal timing waveform
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10. Vertical timing waveform
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11. Package information
8D02E
LQFP 64 Pin
PIN Parameter mm
A B C D E F G H I J K
64 11.90~ 9.90~ 11.90~ 9.90~ 0.50 0.20 1.35~ 1.6 0.10 0.45~ 0.1~ 0 -7
12.10 10.10 12.10 10.10 TYP TYP 1.45 MAX TYP 0.75 0.2
(10X10)
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,,,

8D02E

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SPECIFICATION FOR APPROVAL

3. Pin assignments ----------------------------------------------------------------------------------- 4

4. Block diagram --------------------------------------------------------------------------------------- 5

5. Pin description -------------------------------------------------------------------------------------- 6

6. Mode selection ------------------------------------------------------------------------------------ 8

7. DC electrical characteristics -----------------------------------------------------------------------15

8. AC electrical characteristics ---------------------------------------------------------------------- 16

9. Horizontal timing waveform ----------------------------------------------------------------------- 17

10. Vertical timing waveform ---------------------------------------------------------------------- 18

11. Package outline dimension --------------------------------------------------------------------- 19

This technical specification is subject to change without notice.

V-POS UP-DOWN Right_Left

CSY PD HPI HPO

64 PIN FUNCTION DESCRIPTION - 1

64 PIN FUNCTION DESCRIPTION - 2

. Acceptable the external & internal master clock input.

. Support both stripe and delta color arrangement

. Provides flip and mirror scan control.

UDC SV1 SV2

. Support 16 kinds of 16:9 display mode.

16 Display modes DLT Mode (SDC=1 & DLT=0)

4:3 Input signals are

4:3 Input signals are displayed

Wide 1 H H L H 4:3 Input signals are

Normal center 4:3 Input signals are

4:3 Input signals of 117

4:3 Input signals of 132

Display Display characteristics D D D D

4:3 Input signals of 176

4:3 Input signals of 204

Wide 6 4:3 Input signals are

4:3 Input signals of 204

4:3 Input signals are

4:3 Input signals are

Display Display characteristics D D D D

Wide 4 center 4:3 Input signals are

Wide 3 center 4:3 Input signals are

Wide 1 right L L L H 4:3 Input signals are

Normal right L L L L 4:3 Input signals are

Display Display characteristics D D D D

4:3 Input signals are

4:3 Input signals are

4:3 Input signals are

4:3 Input signals are

2. Recommended operating conditions:

9. Horizontal timing waveform

10. Vertical timing waveform

11. Package information

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