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Refer to TRKA-10D815R Errata document for additional information specific to each code release.
Digital I/Os
Margin Up/Down, Reset In,
Power Good Out, Warning Out,
Reset Out, etc.
External Reference
Digital I/O
Control
PWM
Output
Main Active Trim
Engine Control Trim
Enable
Sequence
Up/Down
Control
DPoL or VRM Enables
Power System
Controller
Figure 1.
Sequence and Margin Controller Functional Block Diagram
76543 21076543210
N X
MSB MSB
The controller will assume full scale equal to the applied reference and assume that the monitored signals are
connected directly to the ADC inputs with no attenuation. If the monitored signals are delivered to the device by
a resistor divider the system interface will need to scale the values accordingly.
The controller will receive output voltage parameters and report output voltage values using the PMBus linear
mode. The voltage will be in the form Voltage = V*2N. The Mantissa and exponent in this equation will be read
and reported using 3 bytes. The first byte is the VOUT_MODE byte which will always contain 000 in the 3 MSBs.
The 5 LSBs are the exponent. The other 2 bytes will contain the Mantissa.
VOUT_MODE
Data Byte High Data Byte Low Data Byte
76543210 7654321076543210
Mode N V
000
In the above format N is a 5 bit 2s complement binary integer and V is a 16 bit unsigned binary integer. All 16 bits
are reported to be compatible with the PMBus protocol. The actual resolution will be based on 10 bit analog to
digital conversions. If using a 3.0V external reference the minimum actual voltage slice will be 2.93mV with a
3.0V full scale. All reported and read parameters will be truncated based on these limitations. The controller will
assume full scale equal to the applied reference and assume that the monitored signals are connected directly to
the ADC inputs with no attenuation. If the monitored signals are delivered to the device by a resistor divider the
system interface will need to scale the values accordingly.
When the CMD is powered on it determines the type of board it is installed on. It sets its address depending on
the type of board as follows:
Legend
<ST> Start Bit SCL=H, SDA=H->L
<RS> Repeated Start Bit
<SP> Stop Bit SCL=H, SDA=L->H
<R> Read Bit (1) SDA=H, SCL=L->H
<W> Write Bit (0) SDA=L, SCL=L->H
<M:xxx> Master communication
<S:xxx> Slave communication
<S:ACK> Slave acknowledge S:SDA=L, SCL=L->H
<M:NACK> Master not acknowledge M:SDA=H, SCL=L->H
<ADDR> 7-bit I2C address
<CMD> Command
<LSB> Low data byte
<MSB> High data byte
The expected order for writing or reading the bytes is transmitting or receiving the high data byte first.
<M:ST> <M:ADDR><M:W><S:ACK>
<M:CMD><S:ACK>
<M:MSB><S:ACK>
<M:LSB><S:ACK>
<M:SP>
Set up and monitoring parameters that are not specific to an individual PoL converter are always available and
can be sent and received across all pages.
To set up the parameters specific to a given PoL and to receive its voltage readback the CMD page pointer has to
be set to point to the page that corresponds to the converter that is to be set up or monitored.
The page command is a single byte command with command code 0x00.
The page command can be used to write the desired page pointer to the CMD. If read from it will return the active
page pointer.
The diagram below shows how the paging is configured relative to each PoL channel supported by the CMD.
Page 0
Not Used
Hard Coded
I2C Address
Page 1-8
APoL1-8
Set Point Control
Scaling
Margin Limits
I2C Engine PGD/Warning Limits
Voltage Reads
&
I2C Bus
Page Page 9-27
Switch DPoL1-19
Scaling
PGD/Warning Limits
Voltage Reads
Page 28-29
Analog x-y
Scaling
PGD/Warning Limits
Voltage Reads
Page Assignment
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 On State Margin State
0 0 x x x x x 1 Immediate Off No Sequencing N/A
0 1 x x x x x 1 Turn Off in Reverse Sequence N/A
Turn Off in Reverse Sequence then
0 1 1 1 0 0 0 1 N/A
Restore User Data
1 0 0 0 x x x 1 On Sequenced Start Up Off
1 0 0 1 0 1 1 x On Sequenced Start Up Margin Low Fault Detect Off
1 0 0 1 1 0 1 x On Sequenced Start Up Margin Low Fault Detect On
1 0 1 0 0 1 1 x On Sequenced Start Up Margin High Fault Detect Off
1 0 1 0 1 0 1 x On Sequenced Start Up Margin High Fault Detect On
The operation command is used to send the operation control word (OCW). The operation control word is used
as the software equivalent of the hardware board seated signal and hardware margining signals. The control
action as a function of the individual OCW bits is defined in the above table and is summarized as a function of
HEX values below.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Enable Method
0 0 0 x x x x 0 Not Supported
0 0 0 x x x x 1 Immediate Turn Off
0 0 1 x x x x 0 Active Low Control Pin (Board Seated)
0 0 1 x x x x 1 Active High Control Pin (Board Seated)
0 1 0 x x x x 0 On/Off Controlled by OPERATION Command only
0 1 0 x x x x 1 On/OFF Controlled by the Control Pin Only
0 1 1 x x x x 0 On/OFF Portion of the Operation Command is Ignored
0 1 1 x x x x 1 On/Off Portion of the Operation Command is Active
1 0 0 x x x x 0 Ignores Enable Commands - System Powers up on Valid Vin
1 0 0 x x x x 1 Enable uses OPERATION Command and Control Pin
The ON/OFF configuration command is used to send the ON/OFF configuration word (OOCW). The ON/OFF
configuration word is used modify how the device responds to various ON/OFF stimuli. The control configuration
as a function of the individual OOCW bits is defined in the above table and is summarized as a function of HEX
values below.
Note: The Clear all power down log data command (0x06 0x55) causes the CMD to perform a flash
memory erase operation to clear the log data. The host application should delay at least 100ms after using this
command before executing other commands to allow the CMD sufficient time to perform the flash memory
operations. If a master attempts to communicate with the slave CMD during this required delay, the CMD may
not generate an acknowledgement to the master. Also note that since the number of flash erase cycles is limited
by the device, the host application should not issue this command unnecessarily.
Note: This command causes the CMD to perform a flash memory erase/write operation to save the
configuration information. The host application should delay at least 100ms after using this command
before executing other commands to allow the CMD sufficient time to perform the flash memory
operations. If a master attempts to communicate with the slave CMD during this required delay, the CMD
may not generate an acknowledgement to the master. Also note that since the number of flash
erase/write cycles is limited by the device, the host application should not issue this command
unnecessarily.
Note: This command causes the CMD to perform a flash memory erase/write operation to save the
configuration information. The host application should delay at least 100ms after using this command
before executing other commands to allow the CMD sufficient time to perform the flash memory
operations. If a master attempts to communicate with the slave CMD during this required delay, the CMD
may not generate an acknowledgement to the master. Also note that since the number of flash
erase/write cycles is limited by the device, the host application should not issue this command
unnecessarily.
Note: This command causes the CMD to perform a flash memory read operation to restore configuration
information. The host application should delay at least 50ms after using this command before executing
other commands to allow the CMD sufficient time to perform the read and restore operation. If a master
attempts to communicate with the slave CMD during this required delay, the CMD may not generate an
acknowledgement to the master.
76543210 7654321076543210
Mode N V
000
A 1 in a corresponding bit location indicates the corresponding POL trim logic is positive. The higher trim
voltage, the higher POL output voltage.
Bit Name Description
B0 Reserved Not used.
B1 APoL 1 1 = Positive trim logic, 0 = Negative trim logic
B2 APoL 2 1 = Positive trim logic, 0 = Negative trim logic
B3 APoL 3 1 = Positive trim logic, 0 = Negative trim logic
B4 APoL 4 1 = Positive trim logic, 0 = Negative trim logic
B5 APoL 5 1 = Positive trim logic, 0 = Negative trim logic
B6 APoL 6 1 = Positive trim logic, 0 = Negative trim logic
B7 APoL 7 1 = Positive trim logic, 0 = Negative trim logic
B8 APoL 8 1 = Positive trim logic, 0 = Negative trim logic
B9 Reserved 1 = Positive trim logic, 0 = Negative trim logic
B10 Reserved 1 = Positive trim logic, 0 = Negative trim logic
B11 Reserved 1 = Positive trim logic, 0 = Negative trim logic
B12 Reserved Not used.
B13 Reserved Not used.
B14 Reserved Not used.
B15 Reserved Not used.
The output OV value is used for setting the initial value for the Vout Max value (0x24 command) which is
used to limit the output voltage set point (0x21 command) or margin high value (0x25 command).
Note that this command does not change the value used for output power-good monitoring. Use the Vout
OV Power Good Limit (0xEC command) for that purpose.
Note that this command does not change the value used for output power-good monitoring. Use the Vout
UV Power Good Limit (0xED command) for that purpose.
A 1 in a corresponding bit location indicates the corresponding DPoL or analog input error.
Bit Name Description
B0 DPoL 9 1 = fault, 0 = no fault
B1 DPoL 10 1 = fault, 0 = no fault
B2 DPoL 11 1 = fault, 0 = no fault
B3 DPoL 12 1 = fault, 0 = no fault
B4 DPoL 13 1 = fault, 0 = no fault
B5 DPoL 14 1 = fault, 0 = no fault
B6 DPoL 15 1 = fault, 0 = no fault
B7 DPoL 16 1 = fault, 0 = no fault
B8 DPoL 17 1 = fault, 0 = no fault
B9 DPoL 18 1 = fault, 0 = no fault
B10 DPoL 19 1 = fault, 0 = no fault
B11 Analog x 1 = fault, 0 = no fault
B12 Analog y 1 = fault, 0 = no fault
B13 Reserved
B14 Reserved
B15 Reserved
If PMBus pointer is 1, the read operation will return/enter the value as below;
B0 Is_Up 1 = System is powered up
B1 Pwr_Good 1 = Power is Good based on Power Good Conditions
B2 Warning 1 = Warning Condition Exists
B3 Vin_UVLO 1 = Vin at or below Under Voltage Lockout limit
B4 Vin_MIN 1 = Vin at or below Minimum Vin limit
B5 Vin_MAX 1 = Vin at or above Maximum Vin limit
B6 Vout_OK 1 = Vout is OK
B7 Enable_State 1 = Board seated is asserted
B8 OVP 1 = Output OVP has occurred on at least one Vout
B9 Failed_Pwr_Up 1 = Unit failed to power up during sequence up event
B10 Reset_A 1 = Reset A fault check is passed
B11 Reset_B 1 = Reset B fault check is passed
B12 Reset_C 1 = Reset C fault check is passed
B13 AD_WNG 1 = AD reference voltage is wrong
B14 Low_Power 1 = In Low Power Mode
B15 Mfg_Mode 1 = In Manufacturing Mode
If PMBus pointer is 2, the read operation will return/enter the value as below;
B0 PIF_Ramp_Fail 1 = Indicates that the PIF ramp test failed
B1 Config_Data_Changed 1 = Indicates that configuration settings have been changed and may be
different than the default settings. Using the 0x12 Restore All Defaults
command will clear this flag and restore the default settings.
B2 Fault_Latch_Off 1 = Indicates that a fault has the board latched off.
B3 Heat_Event 1 = Indicates that either Thermal Trip or VR Hot are set and shut down is
active.
B4 Dual_SP_Setting Indicates alternate setpoint setting: 0 = setting A, 1 = setting B
B5 Reserved
B6 Reserved
B7 Reserved
B8 Reserved
B9 Reserved
B10 Reserved
B11 Reserved
B12 Reserved
B13 Reserved
B14 Reserved
B15 Reserved
If Vout connects directly to ADC input, use 1023 for 10-bit ADC mode or 4095 for 12-bit ADC mode.
If voltage divider is used, enter 1023*(1+Ra/Rb) for 10-bit ADC mode or 4095*(1+Ra/Rb) for 12-bit ADC
mode.
With voltage divider enter 1023*(1+Ra/Rb) for 10-bit ADC mode or 4095*(1+Ra/Rb) for 12-bit ADC mode.
Upon receipt system is powered down in reverse sequence order. After a delay of approximately 3
seconds the system is re-started in proper sequenced order.
This command is the I2C equivalent to the hardware reset input signal as defined below:
0xF6 0x55 The equivalent action will be taken as if the hardware reset in is asserted.
0xF6 0xAA The equivalent action will be taken as if the hardware reset in is de-asserted.
This command can also be used to assert or de-assert the Warning output:
0xF6 0x10 0x55 Assert Warning output.
0xF6 0x10 0xAA De-assert Warning output.
A 1 in a corresponding bit location makes the corresponding output pin an open drain signal. A 0
makes the signal driven.
If PMBus pointer is 1, the read/write operation will return/enter the value for Open Drain Selects 1;
Bit Name Description
B0 Therm Mux Sel 0 1 = open drain signal, 0 = signal driven
B1 Therm Mux Sel 1 1 = open drain signal, 0 = signal driven
B2 Therm Mux Sel 2 1 = open drain signal, 0 = signal driven
B3 Reset A Out 1 = open drain signal, 0 = signal driven
B4 Reserved
B5 Reserved
B6 Power Good 1 = open drain signal, 0 = signal driven
B7 Reserved 1 = open drain signal, 0 = signal driven
B8 APoL 1 Enable 1 = open drain signal, 0 = signal driven
B9 APoL 2 Enable 1 = open drain signal, 0 = signal driven
B10 APoL 3 Enable 1 = open drain signal, 0 = signal driven
B11 APoL 4 Enable 1 = open drain signal, 0 = signal driven
B12 APoL 5 Enable 1 = open drain signal, 0 = signal driven
B13 APoL 6 Enable 1 = open drain signal, 0 = signal driven
B14 APoL 7 Enable 1 = open drain signal, 0 = signal driven
B15 APoL 8 Enable 1 = open drain signal, 0 = signal driven
If PMBus pointer is 2, the read/write operation will return/enter the value for Open Drain Selects 2;
Bit Name Description
B0 DPoL 1 Enable 1 = open drain signal, 0 = signal driven
B1 DPoL 2 Enable 1 = open drain signal, 0 = signal driven
B2 DPoL 3 Enable 1 = open drain signal, 0 = signal driven
B3 DPoL 4 Enable 1 = open drain signal, 0 = signal driven
B4 DPoL 5/9 Enable 1 = open drain signal, 0 = signal driven
B5 DPoL 6/10 Enable 1 = open drain signal, 0 = signal driven
B6 DPoL 7/11 Enable 1 = open drain signal, 0 = signal driven
B7 DPoL 8/12 Enable 1 = open drain signal, 0 = signal driven
B8 DPoL 13/15 Enable 1 = open drain signal, 0 = signal driven
B9 DPoL 14/16 Enable 1 = open drain signal, 0 = signal driven
B10 DPoL 17 Enable 1 = open drain signal, 0 = signal driven
B11 DPoL 18 Enable 1 = open drain signal, 0 = signal driven
B12 DPoL 19 Enable 1 = open drain signal, 0 = signal driven
B13 Reserved
B14 Reserved
Revision G1 TRKA-10D815R Page 25 of 48
B15 Warning 1 = open drain signal, 0 = signal driven
A 1 in a corresponding bit location makes the corresponding output pin positive logic. A 0 makes the
signal negative logic.
If PMBus pointer is 1, the read/write operation will return/enter the value for Output Logic Selects 1;
Bit Name Description
B0 Therm Mux Sel 0 1 = positive logic, 0 = negative logic
B1 Therm Mux Sel 1 1 = positive logic, 0 = negative logic
B2 Therm Mux Sel 2 1 = positive logic, 0 = negative logic
B3 Reset A Out 1 = positive logic, 0 = negative logic
B4 Reset B Out / Analog x Comparator 1 = positive logic, 0 = negative logic
B5 Reset C Out 1 = positive logic, 0 = negative logic
B6 Power Good 1 = positive logic, 0 = negative logic
B7 Reserved 1 = positive logic, 0 = negative logic
B8 APoL 1 Enable 1 = positive logic, 0 = negative logic
B9 APoL 2 Enable 1 = positive logic, 0 = negative logic
B10 APoL 3 Enable 1 = positive logic, 0 = negative logic
B11 APoL 4 Enable 1 = positive logic, 0 = negative logic
B12 APoL 5 Enable 1 = positive logic, 0 = negative logic
B13 APoL 6 Enable 1 = positive logic, 0 = negative logic
B14 APoL 7 Enable 1 = positive logic, 0 = negative logic
B15 APoL 8 Enable 1 = positive logic, 0 = negative logic
If PMBus pointer is 2, the read/write operation will return/enter the value for Output Logic Selects 2;
Bit Name Description
B0 DPoL 1 Enable 1 = positive logic, 0 = negative logic
B1 DPoL 2 Enable 1 = positive logic, 0 = negative logic
B2 DPoL 3 Enable 1 = positive logic, 0 = negative logic
B3 DPoL 4 Enable 1 = positive logic, 0 = negative logic
B4 DPoL 5/9 Enable 1 = positive logic, 0 = negative logic
B5 DPoL 6/10 Enable 1 = positive logic, 0 = negative logic
B6 DPoL 7/11 Enable 1 = positive logic, 0 = negative logic
B7 DPoL 8/12 Enable 1 = positive logic, 0 = negative logic
B8 DPoL 13/15 Enable 1 = positive logic, 0 = negative logic
B9 DPoL 14/16 Enable 1 = positive logic, 0 = negative logic
B10 DPoL 17 Enable 1 = positive logic, 0 = negative logic
B11 DPoL 18 Enable 1 = positive logic, 0 = negative logic
B12 DPoL 19 Enable 1 = positive logic, 0 = negative logic
B13 Reserved
B14 Reserved
B15 Warning 1 = positive logic, 0 = negative logic
If PMBus pointer is 1, the read/write operation will return/enter the value as below;
Bit Name Description
B0 Thermal Trip 0 1 = On, 0 = Off
B1 Thermal Trip 1 1 = On, 0 = Off
B2 Thermal Trip 2 1 = On, 0 = Off
B3 Thermal Trip 3 1 = On, 0 = Off
B4 Thermal Trip 4 1 = On, 0 = Off
B5 Thermal Trip 5 1 = On, 0 = Off
B6 Thermal Trip 6 1 = On, 0 = Off
B7 Thermal Trip 7 1 = On, 0 = Off
B8 VR Hot 0 1 = On, 0 = Off
B9 VR Hot 1 1 = On, 0 = Off
B10 VR Hot 2 1 = On, 0 = Off
B11 VR Hot 3 1 = On, 0 = Off
B12 VR Hot 4 1 = On, 0 = Off
B13 VR Hot 5 1 = On, 0 = Off
B14 VR Hot 6 1 = On, 0 = Off
B15 VR Hot 7 1 = On, 0 = Off
If PMBus pointer is 2, the read/write operation will return/enter the value as below;
B0 IO PIF 1 = On, 0 = Off
B1 Manufacturing Mode 1 = On, 0 = Off
B2 Ramp Test Fail SD 1 = Shut down board if PIF ramp fails; 0 = Dont shut down if fails
B3 PIF Ramp Test Input 1 = Analog X is selected for PIF ramp test; 0 = Analog Y is selected
Revision G1 TRKA-10D815R Page 27 of 48
B4 Alternate Voltage 1 = Disable alternate voltage support;
Setpoint Support 0 = Enable alternate voltage support (controlled by Alternate Voltage Setpoint
Control input)
B5 Reserved
B6 Reserved
B7 Reserved
B8 Reserved
B9 Reserved
B10 Reserved
B11 Reserved
B12 Reserved
B13 Reserved
B14 Reserved
B15 Reserved
If PMBus pointer is 2, the read/write operation will return/enter the value for Output Pin Flags 2;
Bit Name Description
B0 DPoL 1 Enable 1 = Asserted, 0 = Deasserted
B1 DPoL 2 Enable 1 = Asserted, 0 = Deasserted
B2 DPoL 3 Enable 1 = Asserted, 0 = Deasserted
B3 DPoL 4 Enable 1 = Asserted, 0 = Deasserted
B4 DPoL 5/9 Enable 1 = Asserted, 0 = Deasserted
B5 DPoL 6/10 Enable 1 = Asserted, 0 = Deasserted
B6 DPoL 7/11 Enable 1 = Asserted, 0 = Deasserted
B7 DPoL 8/12 Enable 1 = Asserted, 0 = Deasserted
B8 DPoL 13/15 Enable 1 = Asserted, 0 = Deasserted
B9 DPoL 14/16 Enable 1 = Asserted, 0 = Deasserted
B10 DPoL 17 Enable 1 = Asserted, 0 = Deasserted
B11 DPoL 18 Enable 1 = Asserted, 0 = Deasserted
B12 DPoL 19 Enable 1 = Asserted, 0 = Deasserted
B13 Reserved
B14 Reserved
B15 Warning 1 = Asserted, 0 = Deasserted
Each delay command is followed by 2 data bytes. The first data byte contains the MSB the second the
LSB. The corresponding 16 bit B0 integer represents the delay in 10us increments. The delay
commands are 0xDC through 0xDE.
Each reset has an associated bit map command each of which is followed by 2 data bytes. A 1 in the
bit that maps to a given converter will attach that converter to the reset condition for a given reset signal.
A 0 will ignore that converter for the specific signal.
If PMBus pointer is 1, the read/write operation will return/enter the value for Reset Mask x 1 (x=A, B, C);
Each delay command is followed by 2 data bytes. The first data byte contains the MSB the second the
LSB. The corresponding 16 bit B0 integer represents the delay in 10us increments. The delay
commands are 0xD9 through 0xDA.
The Power Good and Warning commands send a bit map that is 2 data bytes in length. A 1 in the bit
that maps to a given converter will attach that converter to the corresponding Power Good or Warning
checks. A 0 will ignore that converter for the specific signal.
If PMBus pointer is 1, the read/write operation will return/enter the value for Power Good Mask 1 or
Warning Mask 1;
Bit Map and Delay Chart for Power Good and Warning Set Up
If PMBus pointer is 2, the read/write operation will return/enter the value for Power Good Mask 2 or Warning
Mask 2;
Bit Map and Delay Chart for Power Good and Warning Set Up
If PMBus pointer is 1, the read/write operation will return/enter the value for Sequence n 1;
If PMBus pointer is 2, the read/write operation will return/enter the value for Sequence n 2;
There are a total of 20 delay commands for sequencing followed by 2 data bytes. The first data byte
contains the MSB the second the LSB. The corresponding 16 bit B0 integer represents the delay in 10us
increments. The delay commands are 0xD0 through 0xD8, 0x0A thru 0x0F and 0xAB thru 0xAE.
There are a total of 19 bit map commands for sequencing followed by 2 data bytes. A 1 in the bit that
maps to a given converter will enable that converter in the desired sequence. A 0 will ignore that
converter in a given sequence. Once a converter is enabled in a previous sequence a 0 in its location in
subsequent sequences will not turn it off. The sequence bit maps are ORed together as the sequencing
proceeds.
Bel provides three boot load .hex files with each code release. Using the boot loader commands and the contents
of the .hex files, the user application has the ability to update the firmware boot block, configuration data, and
application code. When each of the sections are downloaded, they are stored in download buffers and are only
used if the download is successful.
1. Send the Firmware Upgrade Command (0x09) specifying which code section is to be downloaded:
Command Subcommand Description Required Delay
0x09 0x02 Prepare for Application Code Download 750ms
0x09 0x03 Prepare for Configuration Data Download 450ms
0x09 0x05 Prepare for Boot Block Code Download 50ms
Once the CMD receives this command it erases the flash memory download buffers. Since this operation takes
some time to complete, the host should not attempt communication with the CMD during the required delay
indicated in the table.
2. Send packets of data (from the .hex files) using the Firmware Download Command (0x08). Each packet is 21
bytes containing the command, address (three bytes), boot data (16 bytes), and a checksum byte. After the CMD
receives 16 of these packets it writes a row to flash memory and the host should not attempt communication with
the CMD during this write time (5ms).
3. Send the Firmware Upgrade Command (0x09) with the image checksum. If the image checksum matches the
image checksum calculated by the CMD code, the CMD code will set flags to indicate that the data in the
download buffers are valid for upgrading.
Command Subcommand Description Required Delay
0x09 0x06 Send image checksum <5ms
4. Optionally send the Firmware Upgrade Command (0x09) specifying which code section is to be upgraded:
Command Subcommand Description Required Delay
0x09 0x00 Upgrade Application Code 1.5s
0x09 0x01 Upgrade Configuration Data 50ms
0x09 0x04 Upgrade Boot Block Code 100ms
Once the CMD receives this command it copies the information from download buffer segment to the working
segment of flash memory. Since this operation takes some time to complete, the host should not attempt
communication with the CMD during the required delay indicated in the table.
If this command is not sent, the upgrade is deferred until the next reboot or until the Upgrading Selection
Command (0x07) is sent:
Command Subcommand Description Required Delay
0x07 0xFF Upgrade Application Code 1.5s
0x07 0xAA Upgrade Configuration Data 50ms
0x07 0x55 Upgrade Boot Block Code 100ms
Note: The boot block code is to be upgraded first. After that, either the configuration data or application code can
be downloaded. You can download all three parts before performing the upgrade operation.
Note: Lower revisions can be upgraded to higher revisions, but downgrading the boot block code from higher
version to lower versions is not supported. Downgrading of application code or configuration data may not be
supported. Any boot loading restrictions are documented in the release notices.
The logging data can be read back from CMD via PMBus command 0x06 (Read back logging data command).
Logging Data
Byte Description
Byte1 ID bits low byte
Byte2 ID bits high byte
Byte3 Power down counter low byte
Byte4 Power down counter high byte
Byte5 POL fault flag low byte
Byte6 POL fault flag high byte
Byte7 Analog fault flag low byte
Byte8 Analog fault flag high byte
Byte9 CMD Flag bits low byte
Byte10 CMD Flag bits high byte
Byte11 CMD Flag_1 bits low byte
Byte12 CMD Flag_1 bits high byte
Byte13 Thermal flag bits high byte
Byte14 Thermal flag bits high byte
Byte15 External flag bits low byte
Byte16 External flag bits high byte
Byte17 Comparator Output flag bits low byte
Byte18 Comparator Output flag bits high byte
Byte19 Input Pin flag bits low byte
Byte20 Input Pin flag bits high byte
Byte21 Condition Response Flag bits low byte
Byte22 Condition Response Flag bits high byte
Byte23 Condition Response Flag_1 bits low byte
Byte24 Condition Response Flag_1 bits high byte
Byte25 POL trim logic flag bits low byte
Byte26 POL trim logic flag bits high byte
Byte27 Output Pin flag bits 1 low byte
Byte28 Output Pin flag bits 1 high byte
Byte29 Output Pin flag bits 2 low byte
Byte30 Output Pin flag bits 2 high byte
Byte31 Command flag bits low byte
Byte32 Command flag bits high byte
Byte33 Watchdog and reset status low byte
Byte34 Watchdog and reset status high byte
Byte35 PMBus command 0x01 low byte
Byte36 PMBus command 0x01 high byte
Byte37 PMBus command 0x02 low byte
Byte38 PMBus command 0x02 high byte
Byte39 Boot loader status low byte
Byte40 Boot loader status high byte
Revision G1 TRKA-10D815R Page 39 of 48
Byte Description
Byte41 Input voltage low byte
Byte42 Input voltage high byte
Byte43 APoL 1 output voltage low byte
Byte44 APoL 1 output voltage high byte
Byte45 APoL 2 output voltage low byte
Byte46 APoL 2 output voltage high byte
Byte47 APoL 3 output voltage low byte
Byte48 APoL 3 output voltage high byte
Byte49 APoL 4 output voltage low byte
Byte50 APoL 4 output voltage high byte
Byte51 APoL 5 output voltage low byte
Byte52 APoL 5 output voltage high byte
Byte53 APoL 6 output voltage low byte
Byte54 APoL 6 output voltage high byte
Byte55 APoL 7 output voltage low byte
Byte56 APoL 7 output voltage high byte
Byte57 APoL 8 output voltage low byte
Byte58 APoL 8 output voltage high byte
Byte59 DPoL 1 output voltage low byte
Byte60 DPoL 1 output voltage high byte
Byte61 DPoL 2 output voltage low byte
Byte62 DPoL 2 output voltage high byte
Byte63 DPoL 3 output voltage low byte
Byte64 DPoL 3 output voltage high byte
Byte65 DPoL 4 output voltage low byte
Byte66 DPoL 4 output voltage high byte
Byte67 DPoL 5 output voltage low byte
Byte68 DPoL 5 output voltage high byte
Byte69 DPoL 6 output voltage low byte
Byte70 DPoL 6 output voltage high byte
Byte71 DPoL 7 output voltage low byte
Byte72 DPoL 7 output voltage high byte
Byte73 DPoL 8 output voltage low byte
Byte74 DPoL 8 output voltage high byte
Byte75 DPoL 9 output voltage low byte
Byte76 DPoL 9 output voltage high byte
Byte77 DPoL 10 output voltage low byte
Byte78 DPoL 10 output voltage high byte
Byte79 DPoL 11 output voltage low byte
Byte80 DPoL 11 output voltage high byte
Byte81 DPoL 12 output voltage low byte
Byte82 DPoL 12 output voltage high byte
Byte83 DPoL 13 output voltage low byte
Byte84 DPoL 13 output voltage high byte
Byte85 DPoL 14 output voltage low byte
Byte86 DPoL 14 output voltage high byte
Byte87 DPoL 15 output voltage low byte
Byte88 DPoL 15 output voltage high byte
Byte89 DPoL 16 output voltage low byte
Revision G1 TRKA-10D815R Page 40 of 48
Byte Description
Byte90 DPoL 16 output voltage high byte
Byte91 DPoL 17 output voltage low byte
Byte92 DPoL 17 output voltage high byte
Byte93 DPoL 18 output voltage low byte
Byte94 DPoL 18 output voltage high byte
Byte95 DPoL 19 output voltage low byte
Byte96 DPoL 19 output voltage high byte
Byte97 Analog x voltage low byte
Byte98 Analog x voltage high byte
Byte99 Analog y voltage low byte
Byte100 Analog y voltage high byte
Byte101 Running minute time low byte before power down
Byte102 Running minute time high byte before power down
Byte103 Running hour time low byte before power down
Byte104 Running hour time high byte before power down
Byte105 Running day time low byte before power down.
Byte106 Running day time high byte before power down.
Byte107 Running year time low byte before power down.
Byte108 Running year time high byte before power down.
Byte109 Configuration Data Saved Counter low byte
Byte110 Configuration Data Saved Counter high byte
Byte111- Reserved
Byte120
Board ID
Board ID number.
Bootloader Status
010 = Prepare CMD for Application Firmware Download
000 = Reboot CMD and Upgrade Application Firmware
011 = Prepare CMD Configuration Table Download
Revision G1 TRKA-10D815R Page 47 of 48
001 = Reboot CMD and Upgrade Configuration Table
Others = Reserved
101 = Prepare CMD for boot block download
100 = Reboot CMD and upgrade boot block
Running Time
CMD running time before power down.