TRKA 10D815R Datasheet K

Power System Sequencer
TRKA-10D815R
April 14, 2014 Bel Power Inc., a subsidiary of Bel Fuse Inc.
On Board Power System Controller RoHS Compliant Rev. K
Features
Digital Signal Processor (DSP) Based with Bel Firmware
Provides Power Up and Power Down Sequencing Logic
Stand Alone or Command Based Feature Set
Fault Detection and Reporting
100-Pin 12mm x 12mm TQFP package
I2C, SMBus, or PMBus compatible serial interface options
Configurable through serial interface, Customizable through software
3V3 logic levels
Voltage Margining via Closed Loop Trim
Analog Input Monitoring
Comparator function
Programmed parameters saved in non-volatile memory
Intelligent configuration capability
Power-down data log for identifying fault conditions
Boot loader for in-system upgrading
Applications
Data Storage Servers
Networking
Telecommunications
Description
This on board power system controller provides a cost effective high performance solution for controlling,
monitoring, and sequencing multiple Point of Load (PoL) converters on a system board. The sequencer uses a
digital signal processor (DSP) engine and Bels firmware to implement a portfolio of board level control features
typically required in a multiple voltage configuration. There are three variations of this device with slightly
different pin assignments and functionality. The variation in use is controlled by the firmware based on the
specific board configuration. The core features are the same among the three variations.
Variation 1 Variation 2 Variation 3

Active trim APOLs 8 11 8
POL and VRM converters to enable and monitor 19 15 20
Additional analog input voltages to monitor 2 3 2
Number of enable output signals 21 19 22
Figure 1 provides a block diagram of the device.
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 Tel 201-432-0463 Fax 201-432-9542 www.belfuse.com
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TRKA-10D815R
Figure 1
Functional Block Diagram
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TRKA-10D815R
I/O Assignment Summary
I/O Type Variation 1 Variation 2 Variation 3
Analog Input 31 31 32
APoLs (8), DPoLs (19), Vin, Analog x Monitor, APoLs (11), DPoLs (15), Vin, Analog x Monitor, APoLs (8), DPoLs (20), Vin, Analog x Monitor,
Analog y Monitor, Analog ID Analog y Monitor, Analog z Monitor, Analog ID Analog y Monitor, Analog ID
Digital Input 12 13 13
Mfg Mode, Board ID (3), Enable, Margin (2), Mfg Mode, Board ID (3), Enable, Margin (2), Mfg Mode, Board ID (3), Enable, Margin (2),
Thermal (2), Reset In, Voltage Selection, PCH Thermal (2), Reset In, Low Power, Voltage Thermal (2), Reset In, Low Power Mode,
Reset Selection, PCH Reset Voltage Selection, PCH Reset
Digital Output 28 24 26
APoL Enable (8), DPoL Enable (13), APoL Enable (10), DPoL Enable (9), IO PIF APoL Enable (8), DPoL Enable (14), IO PIF
Alert/Warning, Power Good, Reset Out (3), Enable, Warning, Power Good, Reset Out, Enable, Warning, Power Good, Reset Out
Mux Select, Fault Output Comparator
PWM Trim 8 11 8
APoLs (8) APoLs (11) APoLs (8)
External Reference 2 (VREF-, VREF+)
I2C Communication 2 (I2C Data, I2C Clock)
Power 14 (VDD, VSS, AVDD, AVSS, VCAP/VDDCORE)
Programming 3 (MCLR*, PGD, PGC)
I/O Definitions
Pin Pin Name Variation 1 Variation 1 Variation 2 Variation 2 Variation 3 Variation 3 5V
Description I/O Function Description I/O Function Description I/O Function Tolerant
1 COFS/RG15 DPoL 7/11 Enable Digital Output Manufacturing Mode Digital Input DPoL 7/11 Enable Digital Output Y
2 VDD 3V3 VDD Power 3V3 VDD Power 3V3 VDD Power
3 AN29/RE5 DPoL 19 Monitor Analog Input APoL 11 Monitor Analog Input DPoL 19 Monitor Analog Input
4 AN30/RE6 Analog x Monitor Analog Input Analog y Monitor Analog Input Analog y Monitor Analog Input
5 AN31/RE7 Manufacturing Mode Digital Input DPoL 15 Monitor Analog Input DPoL 20 Monitor Analog Input
6 AN16/T2CK/T7CK/RC1 DPoL 8 Monitor Analog Input DPoL 8 Monitor Analog Input DPoL 8 Monitor Analog Input
10 SCK2/CN8/RG6 Board ID 0 Digital Input Board ID 0 Digital Input Board ID 0 Digital Input Y
11 SDI2/CN9/RG7 Board ID 1 Digital Input Board ID 1 Digital Input Board ID 1 Digital Input Y
12 SDO2/CN10/RG8 Board ID 2 Digital Input Board ID 2 Digital Input Board ID 2 Digital Input Y
13 MCLR* CMD Reset/Vpp Programming CMD Reset/Vpp Programming CMD Reset/Vpp Programming Y
14 SS2/CN11/RG9 Alert/Warning Digital Output Alert/Warning Digital Output Alert/Warning Digital Output Y
15 VSS Logic Ground Power Logic Ground Power Logic Ground Power
17 TMS/RA0 Enable/Board Seated Digital Input Enable/Board Seated Digital Input Enable/Board Seated Digital Input Y
18 AN20/INT1/RA12 DPoL 12 Monitor Analog Input DPoL 12 Monitor Analog Input DPoL 12 Monitor Analog Input
19 AN21/INT2/RA13 DPoL 13 Monitor Analog Input DPoL 13 Monitor Analog Input DPoL 13 Monitor Analog Input
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TRKA-10D815R
20 AN5/CN7/RB5 APoL 5 Monitor Analog Input APoL 5 Vout Monitor Analog Input APoL 5 Monitor Analog Input
23 AN2/SS1/CN4/RB2 APoL 2 Monitor Analog Input APoL 2 Vout Monitor Analog Input APoL 2 Monitor Analog Input
24 PGEC3/AN1/CN3/RB1 APoL 1 Monitor Analog Input APoL 1 Vout Monitor Analog Input APoL 1 Monitor Analog Input
25 PGED3/AN0/CN2/RB0 Vin Monitor Analog Input Vin Monitor Analog Input Vin Monitor Analog Input
26 PGEC1/AN6/OCFA/RB6 APoL 6 Monitor Analog Input APoL 6 Vout Monitor Analog Input APoL 6 Monitor Analog Input
27 PGED1/AN7/RB7 APoL 7 Monitor Analog Input APoL 7 Vout Monitor Analog Input APoL 7 Monitor Analog Input
28 VREF-/RA9 Analog Ground External Ref Analog Ground External Ref Analog Ground External Ref
3V0 External 3V0 External 3V0 External
29 VREF+/RA10 Reference External Ref Reference External Ref Reference External Ref
30 AVDD Filtered VDD Power Filtered VDD Power Filtered VDD Power
31 AVSS Analog Ground Power Analog Ground Power Analog Ground Power
32 AN8/RB8 APoL 8 Monitor Analog Input APoL 8 Vout Monitor Analog Input APoL 8 Monitor Analog Input
33 AN9/RB9 DPoL 1 Monitor Analog Input DPoL 1 Vout Monitor Analog Input DPoL 1 Monitor Analog Input
38 TCK/RA1 APoL 1 Enable Digital Output APoL 1 Enable Digital Output APoL 1 Enable Digital Output Y
39 RF13 Margin Low Digital Input Margin Low Digital Input Margin Low Digital Input Y
40 RF12 Margin High Digital Input Margin High Digital Input Margin High Digital Input Y
41 AN12/RB12 DPoL 4 Monitor Analog Input DPoL 4 Monitor Analog Input DPoL 4 Monitor Analog Input
44 AN15/OCFB/CN12/RB15 DPoL 7 Monitor Analog Input DPoL 7 Monitor Analog Input DPoL 7 Monitor Analog Input
47 IC7/CN20/RD14 Thermal Trip Digital Input Thermal Trip Digital Input Thermal Trip Digital Input Y
48 IC8/CN21/RD15 Power Good Digital Output Power Good Digital Output Power Good Digital Output Y
49 CN17/RF4 DPoL 18 Enable Digital Output DPoL 13 Enable Digital Output DPoL 18 Enable Digital Output Y
50 CN18/RF5 DPoL 19 Enable Digital Output APoL 7/9 Enable Digital Output DPoL 19 Enable Digital Output Y
51 RF3 DPoL 17 Enable Digital Output APoL10 Enable B Digital Output DPoL 17 Enable Digital Output Y
52 RF2 DPoL 14/16 Enable Digital Output APoL 11 Enable Digital Output DPoL 14 Enable Digital Output Y
53 RF8 Fault Output Digital Output DPoL 9 Enable Digital Output Low Power Mode Digital Input Y
54 RF7 PCH Reset In Digital Input DPoL 10 Enable Digital Output PCH Reset In Digital Input Y
55 SCK1/RF6/INT0 Therm Mux Sel 0 Digital Output DPoL 11/12 Enable Digital Output AVS Voltage Selection Digital Input Y
56 SDA1/RG3 I2C Data I2C Comm I2C Data I2C Comm I2C Data I2C Comm Y
57 SCL1/RG2 I2C Clock I2C Comm I2C Clock I2C Comm I2C Clock I2C Comm Y
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58 SCL2/RA2 APoL 2 Enable Digital Output APoL 2 Enable Digital Output APoL 2 Enable Digital Output Y
59 SDA2/RA3 APoL 3 Enable Digital Output APoL 3 Enable Digital Output APoL 3 Enable Digital Output Y
60 RA4 APoL 4 Enable Digital Output APoL 4 Enable Digital Output APoL 4 Enable Digital Output Y
61 RA5 APoL 5 Enable Digital Output APoL 5 Enable Digital Output APoL 5 Enable Digital Output Y
63 RC12 Reset B Out Digital Output APoL 10 Trim PWM Trim DPoL 20 Enable Digital Output
64 RC15 Reset C Out Digital Output APoL 9 Trim PWM Trim Manufacturing Mode Digital Input
66 INT3/RA14 Reset In Digital Input Reset In Digital Input Reset In Digital Input Y
67 INT4/RA15 Reset A Out Digital Output Reset A Out Digital Output Reset A Out Digital Output Y
68 IC1/RD8 APoL 8 Enable Digital Output APoL 8 Enable Digital Output APoL 8 Enable Digital Output Y
69 IC2/RD9 DPoL 1 Enable Digital Output PCH Reset In Digital Input DPoL 12 Enable Digital Output Y
70 IC3/RD10 DPoL 2 Enable Digital Output AVS Voltage Selection Digital Input DPoL 15 Enable Digital Output Y
71 IC4/RD11 DPoL 3 Enable Digital Output Analog y Comp Out Digital Output DPoL 16 Enable Digital Output Y
72 OC1/RD0 APoL 1 Trim PWM Trim APoL 1 Trim PWM Trim APoL 1 Trim PWM Trim Y
73 PGED2/CN1/RC13 Program Data Programming Program Data Programming Program Data Programming
74 PGEC2/CN0/RC14 Program Clock Programming Program Clock Programming Program Clock Programming
79 IC5/RD12 DPoL 4 Enable Digital Output APoL 11 Trim PWM Trim DPoL 4 Enable Digital Output Y
AVS Voltage Y
80 IC6/CN19/RD13 Selection Digital Input IO PIF Enable Digital Output IO PIF Enable Digital Output
81 OC5/CN13/RD4 APoL 5 Trim PWM Trim APoL 5 Trim PWM Trim APoL 5 Trim PWM Trim Y
Core Decoupling Core Decoupling Core Decoupling
85 VCAP/VDDCORE Capacitor Power Capacitor Power Capacitor Power
87 RF0 DPoL 8/12 Enable Digital Output VR Hot Digital Input DPoL 8 Enable Digital Output Y
88 RF1 DPoL 13/15 Enable Digital Output DPoL 8 Enable Digital Output DPoL 13 Enable Digital Output Y
89 RG1 APoL 6 Enable Digital Output APoL 6 Enable Digital Output APoL 6 Enable Digital Output Y
90 RG0 APoL 7 Enable Digital Output DPoL 15 Enable Digital Output APoL 7 Enable Digital Output Y
91 AN22/CN22/RA6 DPoL 14 Monitor Analog Input APoL 9 Monitor Analog Input DPoL 14 Monitor Analog Input
92 AN23/CN23/RA7 DPoL 15 Monitor Analog Input APoL 10 Monitor Analog Input DPoL 15 Monitor Analog Input
93 AN24/RE0 DPoL 16 Monitor Analog Input Analog z Monitor Analog Input DPoL 16 Monitor Analog Input
94 AN25/RE1 DPoL 17 Monitor Analog Input Low Power Shutdown Digital Input DPoL 17 Monitor Analog Input
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95 RG14 DPoL 6/10 Enable Digital Output DPoL 5 Enable Digital Output DPoL 6/10 Enable Digital Output Y
96 RG12 VR Hot Digital Input DPoL 6 Enable Digital Output VR Hot Digital Input Y
97 RG13 DPoL 5/9 Enable Digital Output DPoL 7 Enable Digital Output DPoL 5/9 Enable Digital Output Y
98 AN26/RE2 DPoL 18 Monitor Analog Input DPoL 14 Monitor Analog Input DPoL 18 Monitor Analog Input
99 AN27/RE3 Analog y Monitor Analog Input Analog x Monitor Analog Input Analog x Monitor Analog Input
100 AN28/RE4 Analog ID Analog Input Analog ID Analog Input Analog ID Analog Input
The voltage on 5V tolerant digital input pins can exceed VDD as indicated in the Absolute Maximum Ratings section. 5V tolerant digital output pins can
be configured with the open-drain feature which allows the generation of outputs higher than VDD by using external pull-up resistors. The maximum
open-drain voltage allowed is the same as the maximum VIH specification defined in the Electrical Specifications.
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TRKA-10D815R
Signal Definitions
Signal Type Definition
Alert/Warning Digital Output If this pin is configured for the Alert function, then this output
is asserted when an I2C error occurs.
If this pin is configured for the Warning function, then this
output is asserted when any of the monitored output
voltages are less than their configured warning lower limit or
greater than their configured warning upper limit.
Alternate Voltage Set point Digital Input When asserted the alternate voltage limits will be used for
Control (Voltage Selection) converters configured for dual set points. Any analog POL
converters configured for dual set points will be trimmed to
the alternate set point.
When de-asserted the normal voltage set points and limits
will be used.
Analog Board ID Analog Input See Board ID below.
Analog x Monitor Analog Input Analog x monitor (must be scaled using attenuating
resistors if voltage exceeds reference voltage).
Analog y Monitor Analog Input Analog y monitor (must be scaled using attenuating
Analog z Monitor Analog Input Analog z monitor (must be scaled using attenuating
APoL Enable Digital Output Enable signal for the eight analog PoL converters. Asserted
during sequence up and de-asserted during sequence
down.
APoL Trim PWM Output PWM output for actively trimming the analog PoLs to their
desired set points. See Using the PWM Trim Outputs
below.
The trim PWMs for APoLs 1-8 are hardware based. The
PWM output duty cycle will remain fixed even when the
controller is performing long operations (such as flash
memory erases and writes).
The PWM outputs for APoLs 9-11 in Variation 2 are

implemented using timers. The PWM output is suspended
during long operations (such as flash memory erases and
writes). During these intervals the output is tri-stated, so the
trim circuit should have a pull-up to set the trim voltage to as
close to the desired voltage as possible to reduce glitches
on the PoL output.
APoL Vout Monitor Analog Input Analog PoL output voltage monitor (must be scaled using
attenuating resistors if voltage exceeds reference voltage).
AVDD Power Positive supply (filtered VDD) for analog modules. See
Powering the Sequencer below.
AVSS Power Analog ground reference. See Powering the Sequencer
below.
Board ID (0-2) Digital Input These three digital inputs along with the Analog Board ID
define a board identification number for controlling which
board specific configuration data is loaded.
DPoL Enable Digital Output Enable signal for the digital PoL or VRM converters. Note
that some of the enables are shared. Asserted during
sequence up and de-asserted during sequence down.
If the corresponding analog input is configured as a
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TRKA-10D815R
comparator then this enable signal is used as the
comparator output instead of enabling/disabling the
converter during sequence up/down.
DPoL Monitor Analog Input Digital PoL, VRM, or other voltage monitor (must be scaled
using attenuating resistors if voltage exceeds reference
voltage).
Enable/Board Seated Digital Input When asserted the board is sequenced up if the input
voltage is valid. When de-asserted the board is sequenced
down. This function can be overridden as defined in the
separate interface document,
TRKA_10D815R_PROTOCOL.
Fault Output Digital Output Asserted when a fault is detected. Latches until fault is
cleared with I2C command, enable is toggled, or input
power is cycled.
I2C Clock I2C Synchronous serial clock input/output for I2C
communication. Since this is a slave device, the master
drives the clock. Clock stretching may occur if necessary
according to the I2C specification.
I2C Data I2C Synchronous serial bi-directional data line for I2C
communication.
Low Power Mode Digital Input When this input is asserted, the enable signals are de-
asserted for the outputs that are not part of the configurable
low-power mode mask and those outputs are no longer
monitored. When this signal becomes asserted, the board
is power cycled.
Manufacturing Mode (Margin Digital Input Enable signal for the hardware margin signals. When
Enable) asserted the margin high/low inputs will cause the analog
PoLs to be margined to their configured high/low margin
values.
Margin High Digital Input See Manufacturing mode above.
Margin Low Digital Input See Manufacturing mode above.
MCLR* Programming Master Clear (Reset) input. This pin is an active-low Reset
to the device.
Mux Select Digital Output Control line to external thermal trip and VR Hot multiplexers
for selecting and checking each of the thermal trip and VR
Hot signals.
PCH Reset Digital Input When this signal is asserted, the following sequence
occurs:
1. change power good output signal to high
impedance,
2. assert Reset A output,
3. power down the board (i.e., de-assert power good
and de-sequence enables),
4. assert Warning output,
5. change power good output back to a driven signal
6. delay for 500ms
7. de-assert Warning output
8. delay for 500ms
9. de-assert Reset A output
PGC Programming Clock input pin for programming communication.
PGD Programming Data I/O pin for programming communication.
Power Good Digital Output Asserted after the configured power good delay after all of
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TRKA-10D815R
the outputs have been sequenced up and are operating
within their configured power good limits. De-asserted prior
to sequencing down due to a fault or commanded to do so.
Reset In Digital Input When asserted, causes Reset A-C to assert.
Reset Out (A-C) Digital Output Asserted when Reset In is asserted. De-asserted when any
outputs in configured reset masks are outside of power
good limits.
Thermal Trip Digital Input Output of external thermal trip multiplexer. When asserted,
the configured thermal trip action occurs if the thermal trip
input for the particular multiplexer setting has been enabled.
VCAP/VDDCORE Power Core decoupling capacitor. See Powering the Sequencer
below.
VDD Power Positive supply (3.3V) for peripheral logic and I/O pins. See
Powering the Sequencer below.
Vin Monitor Analog Input System input voltage monitor (must be scaled using
attenuating resistors if voltage exceeds reference voltage).
VR Hot Digital Input Output of external VR Hot multiplexer. When asserted, the
configured VR Hot action occurs if the VR Hot input for the
particular multiplexer setting has been enabled.
VREF- External Reference Analog voltage reference (low) input.
VREF+ External Reference Analog voltage reference (high) input.
VSS Power Ground reference for logic and I/O pins. See Powering the
Sequencer below.
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TRKA-10D815R
Powering the Sequencer
VDD Core
C8
2.2 uF
10v
X5R
Microchip P/N
D1 MCP1702T-3302I/MB
BAT54
+12Vin or Equivalent
In Out VDD
R1
20 Ohm
1206
C1
C2 3V3 Output LDO C4 C5 C6 C7
1000uF
1uF 1uF 1uF 1uF 1uF
+12Vin Return 25V
16v GND 16v 16v 16v 16v VSS
X5R R2
X5R X5R X5R X5R
4.64 Ohm
AVDD
C3
2.2 uF
10v
X5R
AVSS
R3
1 Ohm
Figure 2
VDD Interface
Figure 2 is a schematic of the typical VDD interface to the sequencer IC. A Microchip LDO, P/N MCP1702T-
3302I/MB, is used to produce the 3.3V VDD supply to the DSP. This device is in a SOT89 package and in most
applications will be sufficient in size to handle the power dissipation when powering the circuit from a 12V
source. Capacitors C4, C5, C6, and C7 are the decoupling capacitors for the DSP and they should be located
directly across each pair of VDD and VSS pins on the DSP IC. The device has a VDD core pin which is used to
decouple the internally generated core voltage. Capacitor C8 is the decoupling capacitor for the VDD core.
This decoupling capacitor should be a low ESR ceramic capacitor and can be as large as 10uF. Capacitor C3 is
the decoupling capacitor for the analog VDD (AVDD) and it should be located directly across the AVDD and AVSS
pins on the DSP IC. Resistor R2 in combination with C3 provides a filter for the analog VDD. Resistor R3 is
intended to separate AVSS from VSS. Capacitor C2 is the input decoupling capacitor for the LDO and it should
be connected directly across the LDOs input and ground pins. Capacitor C1 is used as a hold up capacitor. Its
purpose is to hold up the supply voltage to the LDO and maintain a stable VDD for the DSP for a short period
after the +12Vin source is removed. This would be desired if a short communication stream is required during
power down or if storing system data to EE memory is required during power down. The Schottky diode D1
prevents C1 from being discharged after +12Vin is removed. Resistor R1 is used to protect D1 during the inrush
event associated with the application of the +12Vin. The single pulse peak current rating for a typical BAT54
diode is approximately 600mA. If the rise time of the +12V source is slow enough to limit the peak charging
current into C1 it is possible to eliminate R1. Assuming a 40mA current draw by the DSP C1 will provide
approximately 188 us of hold up time per uF of capacitance.
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TRKA-10D815R
Using the PWM Trim Outputs
+Sense
+Vin
Ry Zf
TRIM Zi -
Rx +Vout
Rz E/A PWM
Reference
Figure 3A.
+Sense
+Vin
Zf
Zi -
+Vout
E/A PWM
TRIM
Rx Ry
Reference
Figure 3B.
+Sense
+Vin
Zf
Zi -
+Vout
E/A PWM
Reference
+
uController
TRIM
or Equivalent
Figure 3C.
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The drawings in figure 3 show the three most common trim methods used in PoL converters. In all of these
schemes a power conversion stage contains a PWM device that receives a control voltage from an error
amplifier. The error amplifier (E/A) compares a scaled version of the output voltage to a reference. The output
voltage of the converter module is simply the reciprocal of the scaling factor multiplied by the reference value.
The output voltage can be adjusted by changing this scaling factor (Figure 3A) or by modifying the reference
(Figures 3B, C).
The most common trim method is shown in figure 3A. The popularity of this method stems from the fact that
most highly integrated PWM control ICs have an internal reference that is not accessible and cannot be
controlled externally. In this scheme the output is scaled by adding a resistor from the trim pin to ground. This
modifies the feedback divider and moves the output voltage to a higher value. The output can also be modified
by superimposing an offset voltage on the feedback divider by connecting a voltage source to the trim pin
through a resistor. Either of these two approaches will move the output voltage to a new value. The common
characteristic of modules with this trim scheme is that a lower value trim resistor to ground will cause a higher
output voltage or a larger voltage superimposed on the trim pin will cause Vout to decrease.
Some PoL converters incorporate the trim scheme shown in figure 3B. With this method the feedback ratio is
kept constant and the reference value is modified to move the output voltage. The common characteristic of
modules with this trim scheme is that a lower value trim resistor to ground will cause a lower output voltage and
a larger voltage superimposed on the trim pin will cause Vout to increase.
The method shown in figure 3C is occasionally used. This is similar to the method in figure 3B except the
modification of the reference is mapped through a device such as a microcontroller. This is the least common of
the 3 methods and requires the vendors data sheet to determine the trim characteristic because the micro
controller can map the reference in many different ways.
VTrim Ripple PoL Vout

or
VTrim Average VDD
Margin PWM PoL Trim Pin

Ca
Ra Rb
3V3
Ca
0 Margin PWM PoL Trim Pin
Ra Rb
3V3
VTrim Average
0
VTrim Ripple
Figure 4A Figure 4B
The power sequencer has the ability to do independent closed loop trim and closed loop margining of the output
voltage for each PoL controlled by the device. Each PoLs output voltage is monitored and by an analog to
digital converter (ADC) in a continuous loop. In firmware the most recent measured output voltage is compared
against the desired value and the PoLs output is adjusted by delivering a trim value to the corresponding PoLs
trim pin. This trim voltage is created from a digital PWM output and an external low pass filter. Each digital
PWM is labeled <PoL n Margin PWM> where n indicates a specific converter which corresponds to the
monitoring channel labeled with the same n value. The external low pass filter creates a DC value from the
PWM signal which is then delivered to each PoL converter through a range limiting resistor.
Figure 4 shows the typical circuits used to interface the sequencers Margin PWM signals to PoL converters. In
each of the circuits shown Ra and Ca construct a low pass filter while Rb is used to limit the trim range. The
effective trim voltage is equal to the Margin PWM duty cycle multiplied by VDD and is controllable in 1024 steps
from 0 to VDD. The effective trim resistor value is equal to Ra + Rb. Ra and Ca are chosen to reduce the trim
voltage ripple. Typical values for Ra and Ca are 1K for Ra and 0.22uF to 1uF for Ca. Rb is used to limit the
control range and should be selected based on the desired control range and the trim equation for the PoL.
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TRKA-10D815R
This trim equation is usually available from the PoL manufactures data sheet. The sequencer learns the trim
direction by making a minor adjustment to the Margin PWM and then determining the direction that Vout moves
based on this stimulus. Once the trim direction is known it knows whether increment or decrement the TRIM
PWM value until the desired Vout is achieved. The accuracy of the active trim is a function of the ADC accuracy
which is mostly controlled by accuracy of the applied reference to the sequencers Vref pins.
Either circuit in Figure 4 will work with any of the trim methods shown in Figure 3. When interfacing to PoL
modules that use the trim method in Figure 3A the circuit in Figure 4B is the optimum interface configuration. By
connecting the filter capacitor Ca to the PoLs Vout or to a positive voltage reference the effective of filtering the
Margin PWM signal remains intact. With this method there will not be a discharged capacitor connected to
ground that could cause the PoLs output to overshoot during power up as this capacitor becomes charged. In
the case that the circuit in figure 4A is used with the trim configuration in Figure 3B the sequencer will pre-
charge the capacitor before enabling the PoL converter and then decrement the Margin PWM to achieve the
desired Vout. This requires additional start up time during system initialization. When interfacing to PoL
converters of the type shown in Figure 3B the interface circuit in figure 4A is optimum.
Monitoring Via ADC Channels

The imbedded ADC channels are converted as 10 or 12 bit results with full scale equal to a chosen reference.
The device is intended to be powered from a 3V3 source and can be configured to use this source as the ADC
reference or to use an externally provided reference. Closed loop margining and set point adjustments always
use the entire 10 or 12 bit result to trim the output voltages to specified values. Monitored voltages are reported
via I2C communication using PMBus data formats as defined in the separate communication manual. The
voltage range reported is determined by the entered set points. Any monitored output that is greater than the
ADC reference or that can be margined above this reference should have a voltage divider to limit the maximum
input to the corresponding ADC channel to a value equal or less than the ADC reference. Monitored voltages
below the chosen ADC reference do not require this voltage divider. A four sample moving average is used to
filter the ADC results. In most cases this will eliminate the need for external filtering.
The input voltage (Vin) monitoring channel requires a voltage divider so that Vin maximum is scaled to a value
less than the maximum value of the ADC reference.
Connecting the Control and Monitor Signals

The three primary control interface signals to the attached PoL converters are an enable signal, a voltage
monitoring signal, and trim control signal. The enable signals are labeled <APoL x Enable>. The Monitoring
signals are labeled <APoL x Monitor>. The trim signals are labeled <APoL x Trim>. Each APoL converter is
required to share the corresponding enable, monitor, and trim signals. The installed firmware assumes that the
connections are made this way when controlling system.
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TRKA-10D815R
Communication with the Device
Serial communication is achieved via an I2C bus. The communication protocol is derived from the PMBus
command set and is defined in a separate communications manual. The communications manual (TRKA-
10D815R Protocol) also defines the protocol for device programming via embedded boot loader software.
The parameters and voltage readings for each PoL converter or analog input can be accessed using PMBus
page mode. Figure 5 shows the page assignments for the three variations of this part
Page 0
Not Used
Hard Coded
I2C Address
Page 1-8
APoL1-8
Set Point Control
Scaling
Margin Limits
I2C Engine PGD/Warning Limits
Voltage Reads
&
I2C Bus
Page Page 9-27
Switch DPoL1-19
Scaling
PGD/Warning Limits
Voltage Reads
Page 28-29
Analog x-y
Scaling
PGD/Warning Limits
Voltage Reads
Figure 5a
I2C Communication Page Assignment Variation 1
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TRKA-10D815R
Page 0
Not Used
Hard Coded
I2C Address
Page 1-11
APoL1-11
Set Point Control
Scaling
Margin Limits
I2C Engine PGD/Warning Limits
Voltage Reads
&
I2C Bus
Page Page 12-26
Switch DPoL1-15
Scaling
PGD/Warning Limits
Voltage Reads
Page 27-29
Analog x-z
Scaling
PGD/Warning Limits
Voltage Reads
Figure 5b
Figure 5c
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TRKA-10D815R
Absolute Maximum Ratings
Ambient temperature under bias ........................................................................................................... -40C to +125C
Storage temperature .............................................................................................................................. -65C to +150C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS ...................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V..................................................... -0.3V to +5.6V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V....................................................... -0.3V to 3.6V
Voltage on VDDCORE with respect to VSS ................................................................................................ 2.25V to 2.75V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ............................................................................................................................. 250 mA
Maximum output current sunk by any I/O pin ...........................................................................................................4 mA
Maximum output current sourced by any I/O pin ......................................................................................................4 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Electrical Specifications
Parameter Symbol Min Typ Max Units Notes
Input Voltage Range VDD 3.0 3.30 3.6 VDC
Typical is at 3.3V, 25C, 20 MIPS.
Input Current IDD 46 55 mA
Max is at 3.3V, 85C, 20 MIPS
Logic Low Input Level VIL VSS 0.2*VDD VDC
VDD Non 5V tolerant pins
Logic High Input Level VIH 0.7*VDD VDC
5.5 5V tolerant pins
Logic Low Output Level VOL 0.4 VDC VDD = 3.3V
Logic High Output Level VOH 2.4 VDC VDD = 3.3V, IOH = -3.0mA
VDD Rise Rate SVDD 0.03 V/mS 0 to 3.0V in 100mS
Capacitance I/O Pin to
CIO 50 pF
GND
I2C Bus Capacitance CB 400 pF SCl and SDA
PWM Series Resistor RPWM 1 kW External Series Resistor
Margin PWM Frequency FPWM 10 kHz
Reference Input Vref AVSS + 1.7 AVDD VDC
Program Flash Memory E/W
EP 10,000
Cell Endurance cycles
16
TRKA-10D815R
Mechanical Outline
Bel 100-pin 12x12x1mm TQFP Sequencer

Figure 6A
100-Lead Plastic Thin-Quad Flatpack, 12x12x1mm Body

Units Millimeters
Dimension Units Min Nom Max
Number of Leads N 100
Lead Pitch e 0.40 BSC
Leads per side n1 25
Overall Height A - - 1.20
Molded Package Thickness A2 0.95 1.00 1.05
Standoff A1 0.05 - 0.15
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle f 0 3.5 7
Overall Width E 14.00 BSC
Overall Length D 14.00 BSC
Molded Package Width E1 12.00 BSC
Molded Package Length D1 12.00 BSC
Lead Thickness c 0.09 - 0.20
Lead Width b 0.13 0.18 0.23
Mold Draft Angle Top a 11 12 13
Mold Draft Angle Bottom b 11 12 13
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Champers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Figure 6B
17
TRKA- 10D815R
Revision History
Date Revision Changes Detail Approval
2010-5-6 A First preliminary draft. S. Moore
Assigned part number. Added Signal Definition section. Reformat
2010-5-10 B S. Moore
document.
Added references to interface protocol document.
2010-5-18 C S. Moore
Corrected number of pin reference in Powering the Sequencer section.
Corrected signal description for pin 99 (should be Analog y Monitor, not
2010-7-12 D S. Moore
Analog x Monitor).
Changed part number from TRKF-10D815R to TRKA-10D815R.
2010-7-19 E S. Moore
Added Program Flash Memory Cell Endurance specification.
2010-8-18 F Changed function of pin 80. S. Moore
2013-7-18 G Added details about additional variations of this part. S. Moore
Corrected typographical error in IO Pin Definitions table column
2913-7-26 H S. Moore
header.
2013-7-29 I Corrected description of pin 99, variation 3 in I/O Definitions table. S. Moore
2014-2-10 J Added information about 5V tolerant pins. S. Moore
2014-4-14 K Added new Fault Output to Variation 1 (pin 53). S. Moore
Errata
Refer to TRKA-10D815R Errata document for additional information specific to each code release.
RoHS Compliance
Complies with the European Directive 2002/95/EC, calling for the elimination of lead and
other hazardous substances from electronic products.
2014 Bel Fuse Inc. Specifications subject to change without notice.
18
CORPORATE FAR EAST EUROPE
Bel Fuse Inc. Bel Fuse Ltd. Bel Fuse Europe Ltd.
206 Van Vorst Street 8F/ 8 Luk Hop Street Preston Technology Management Centre
Jersey City, NJ 07302 San Po Kong Marsh Lane, Suite G7, Preston
Tel 201-432-0463 Kowloon, Hong Kong Lancashire, PR1 8UD, U.K.
Fax 201-432-9542 Tel 852-2328-5515 Tel 44-1772-556601
www.belfuse.com Fax 852-2352-3706 Fax 44-1772-888366
www.belfuse.com www.belfuse.com

TRKA 10D815R Datasheet K

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TRKA 10D815R Datasheet K

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Power System Sequencer

Variation 1 Variation 2 Variation 3

Figure 1 provides a block diagram of the device.

The PWM outputs for APoLs 9-11 in Variation 2 are

VTrim Ripple PoL Vout

Margin PWM PoL Trim Pin

Monitoring Via ADC Channels

Connecting the Control and Monitor Signals

Bel 100-pin 12x12x1mm TQFP Sequencer

100-Lead Plastic Thin-Quad Flatpack, 12x12x1mm Body

2014 Bel Fuse Inc. Specifications subject to change without notice.

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