TRKX 10DC4ER Datasheet D

Power System Sequencer
TRKF-10DC4ER, TRKA-10DC4ER
February 10, 2014 Bel Power Inc., a subsidiary of Bel Fuse Inc.
On Board Power System Controller RoHS Compliant Rev. D
Features
Digital Signal Processor (DSP) Based with Bel Firmware
Provides Power Up and Power Down Sequencing Logic
Stand Alone or Command Based Feature Set
Fault Detection and Reporting
100-Pin 12mm x 12mm TQFP package
I2C, SMBus, or PMBus compatible serial interface options
Configurable through serial interface, Customizable through software
3V3 logic levels
Voltage Margining via Closed Loop Trim
Analog Input Monitoring
Comparator function
Programmed parameters saved in non-volatile memory
Intelligent configuration capability
Power-down data log for identifying fault conditions
Boot loader for in-system upgrading
Applications
Data Storage Servers
Networking
Telecommunications
Description
This on board power system controller provides a cost effective high performance solution for controlling,
monitoring, and sequencing multiple Point of Load (POL) converters and VRMs on a system board. The
sequencer uses a digital signal processor (DSP) engine and Bels firmware to implement a portfolio of board
level control features typically required in a multiple voltage configuration. The solution can control and monitor
PoL converters and VRMs. The 100 pin TRKF-10DC4ER is derived from Bels 64 pin TRKF-64D82ER platform
with expanded I/O and functionality.
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 Tel 201-432-0463 Fax 201-432-9542 www.belfuse.com
1
Optional Feature Sets
SDA
I2C EE^2 Data Logging
Input Inrush Control
SCL Communication
and Vin Monitor
A Command Interface
Digital B
Commands C/Optional SS for SPI
Vout ADC Input
Vin
Vin
Digital Output Enable
PoL 1 of n Vout Vout 1of n
Trim PWM Trim
Rfilter Rlimit
GND
Cfilter
Control Grouping 1 of n
Figure 1
Functional Block Diagram
2
I/O Definitions
1 RG15 Analog z Comp Out/Enable (see Note 2) 51 RF3 VRM D Enable
2 VDD 3V3 VDD 52 RF2 VRM C Enable
3 PWM3H/RE5 I2C_ALERT 53 SDO1/RF8 VID 4
4 PWM4L/RE6 PoL 12 PWM Trim 54 SDI1/RF7 VID 3
5 PWM4H/RE7 Manufacturing Mode 55 SCK1/RF6 VID 2
6 AN16 VRM 1 Vout Monitor 56 SDA1/RG3 I2C Data
7 AN17 VRM 2 Vout Monitor 57 SCL1/RG2 I2C Clock
8 AN18 VRM 3 Vout Monitor 58 RA2 PoL 2 Enable
9 AN19 VRM 4 Vout Monitor 59 RA3 PoL 3 Enable
10 SCK2/CN8/RG6 Board ID 0 60 RA4 PoL 4 Enable
11 SDI2/CN9/RG7 Board ID 1 61 RA5 PoL 5 Enable
12 SDO2/CN10/RG8 Board ID 2 62 VDD 3V3 VDD
13 MCLR CMD Reset/Vpp 63 RC12 Reset B Out
14 SS2/CN11/RG9 Un-linked Enable Output (Note 3) 64 RC15 Reset C Out
15 VSS Logic Ground 65 VSS Logic Ground
16 VDD 3V3 VDD 66 RA14 Reset In
17 TMS/RA0 Enable/Board Seated 67 RA15 Reset A Out
18 AN20/RE8 Low Power Shutdown 68 RD8 PoL 8 Enable
19 AN21/RE9 Board ID Analog (Note 4) 69 RD9 PoL 9 Enable
20 AN5/CN7/RB5 PoL 5 Vout Monitor 70 RD10 PoL 10 Enable
21 AN4/CN6/RB4 PoL 4 Vout Monitor 71 RD11 PoL 11 Enable
22 AN3/CN4/RB2 PoL 3 Vout Monitor 72 OC1/RD0 PoL 1 PWM Trim
23 AN2/SS1/CN4/RB2 PoL 2 Vout Monitor 73 PGD2 Program Data
24 AN1/RB1 PoL 1 Vout Monitor 74 PGC2 Program Clock
25 AN0/RBO Vin Monitor 75 VSS Logic Ground
26 PGC1/AN6/RB6 PoL 6 Vout Monitor 76 OC2/RD1 PoL 2 PWM Trim
27 PGD1/AN7/RB7 PoL 7 Vout Monitor 77 OC3/RD2 PoL 3 PWM Trim
28 VREF- Analog Ground 78 OC4/RD3 PoL 4 PWM Trim
29 VREF+ 3V00 External Reference 79 RD12 PoL 12 Enable
30 AVDD FILTERED VDD (Analog VDD) 80 CN19/RD13 IO PIF Enable/OV Trip
31 AVSS Analog Ground 81 OC5/CN13/RD4 PoL 5 PWM Trim
32 AN8/RB8 PoL 8 Vout Monitor 82 OC6/CN14/RD5 PoL 6 PWM Trim
33 AN9/RB9 PoL 9 Vout Monitor 83 OC7/CN15/RD6 PoL 7 PWM Trim
34 AN10/RB10 PoL 10 Vout Monitor 84 0C8/CN16/RD7 PoL 8 PWM Trim
35 AN11/RB11 PoL 11 Vout Monitor 85 VDD_CORE Core Decoupling Capacitor
36 VSS Logic Ground 86 VDD 3V3 VDD
37 VDD 3V3 VDD 87 RF0 VRM A Enable
38 RA1 Pol 1 Enable 88 RF1 VRM B Enable
39 RF13 VID 6 89 RG1 VID MUX 1
40 RF12 VID 5 90 RG0 VID MUX 0
41 AN12/RB12 Pol 12 Monitor 91 AN22/CN22/RA6 PoL 6 Enable
42 AN13/RB13 Analog x Monitor 92 AN23/CN23/RA7 PoL 7 Enable
43 AN14/RB14 Analog y Monitor 93 PWM1L/RE0 PoL 9 PWM Trim
44 AN15/RB15 Analog z Monitor 94 PWM1H/RE3 Margin High
45 VSS Logic Ground 95 RG14 Analog y Comp Out/Enable (see Note 2)
46 VDD 3V3 VDD 96 RG12 VR Hot (See Note 1)
47 CN20/RD14 Thermal Trip (see Note 1) 97 RG13 Analog x Comp Out/Enable (see Note 2)
48 CN21/RD15 Power Good 98 PWM2L/RE2 PoL 10 PWM Trim
49 CN17/RF4 VID 0 99 PWM2H/RE3 Margin Low
50 CN18/RF5 VID 1 100 PWM3L/RE4 PoL 11 PWM Trim
Note 1 Thermal Trip and VR_Hot Signals for A,B,C,D mapped to same MUX as VID's
Note 2 These signals triggered by defined voltage levels on corresponding Analog Monitor or used like POL enable
Note 3 Controlled in a selected power up sequence but not tied to a specific output
Note 4 Use ADC to allow ID of additional boards with resistor divider
Figure 2
I/O Definitions
3
I/O Grouping
13 MCLR CMD Reset/Vpp 6 AN16 VRM 1 Vout Monitor 24 AN1/RB1 PoL 1 Vout Monitor
A 73 PGD2 Program Data 7 AN17 VRM 2 Vout Monitor 23 AN2/SS1/CN4/RB2 PoL 2 Vout Monitor
74 PGC2 Program Clock 8 AN18 VRM 3 Vout Monitor 22 AN3/CN4/RB2 PoL 3 Vout Monitor
9 AN19 VRM 4 Vout Monitor 21 AN4/CN6/RB4 PoL 4 Vout Monitor
85 VDD_CORE Core Decoupling Capacitor 20 AN5/CN7/RB5 PoL 5 Vout Monitor
29 VREF+ 3V00 External Reference
G1 87 RF0 VRM A Enable 26 PGC1/AN6/RB6 PoL 6 Vout Monitor
30 AVDD FILTERED VDD (Analog VDD) 88 RF1 VRM B Enable 27 PGD1/AN7/RB7 PoL 7 Vout Monitor
86 VDD 3V3 VDD 52 RF2 VRM C Enable 32 AN8/RB8 PoL 8 Vout Monitor
2 VDD 3V3 VDD 51 RF3 VRM D Enable 33 AN9/RB9 PoL 9 Vout Monitor
16 VDD 3V3 VDD 34 AN10/RB10 PoL 10 Vout Monitor
37 VDD 3V3 VDD 89 RG1 VID MUX 1 35 AN11/RB11 PoL 11 Vout Monitor
46 VDD 3V3 VDD 90 RG0 VID MUX 0 41 AN12/RB12 PoL 12 Vout Monitor
B 62 VDD 3V3 VDD 49 CN17/RF4 VID 0
65 VSS Logic Ground 50 CN18/RF5 VID 1 72 OC1/RD0 PoL 1 PWM Trim
45 VSS Logic Ground 55 SCK1/RF6 VID 2 76 OC2/RD1 PoL 2 PWM Trim
36 VSS Logic Ground G2 54 SDI1/RF7 VID 3 77 OC3/RD2 PoL 3 PWM Trim
15 VSS Logic Ground 53 SDO1/RF8 VID 4 78 OC4/RD3 PoL 4 PWM Trim
75 VSS Logic Ground 40 RF12 VID 5 81 OC5/CN13/RD4 PoL 5 PWM Trim
28 VREF- Analog Ground 39 RF13 VID 6 82 OC6/CN14/RD5 PoL 6 PWM Trim
31 AVSS Analog Ground 96 RG12 VR Hot (See Note 1) J 83 OC7/CN15/RD6 PoL 7 PWM Trim
47 CN20/RD14 Thermal Trip (see Note 1) 84 0C8/CN16/RD7 PoL 8 PWM Trim
10 SCK2/CN8/RG6 Board ID 0 93 PWM1L/RE0 PoL 9 PWM Trim
11 SDI2/CN9/RG7 Board ID 1 42 AN13/RB13 Analog x Monitor 98 PWM2L/RE2 PoL 10 PWM Trim
C 12 SDO2/CN10/RG8 Board ID 2 43 AN14/RB14 Analog y Monitor 100 PWM3L/RE4 PoL 11 PWM Trim
19 AN21/RE9 Board ID Analog (Note 5) 44 AN15/RB15 Analog z Monitor 4 PWM4L/RE6 PoL 12 PWM Trim
H
56 SDA1/RG3 I2C Data 97 RG13 Analog x Comp Out/Enable (see Note 2) 38 RA1 PoL 1 Enable
D 57 SCL1/RG2 I2C Clock 95 RG14 Analog y Comp Out/Enable (see Note 2) 58 RA2 PoL 2 Enable
3 PWM3H/RE5 I2C_ALERT 1 RG15 Analog z Comp Out/Enable (see Note 2) 59 RA3 PoL 3 Enable
60 RA4 PoL 4 Enable
99 PWM2H/RE3 Margin Low (Note 4) 25 AN0/RBO Vin Monitor 61 RA5 PoL 5 Enable
94 PWM1H/RE3 Margin High (Note 4) 91 AN22/CN22/RA6 PoL 6 Enable
5 PWM4H/RE7 Manufacturing Mode (Note 4)
I 80 CN19/RD13 IO PIF Enable/OV Trip 92 AN23/CN23/RA7 PoL 7 Enable
48 CN21/RD15 Power Good 14 SS2/CN11/R Un-linked Enable Output (Note 3) 68 RD8 PoL 8 Enable
66 RA14 Reset In 69 RD9 PoL 9 Enable
F 67 RA15 Reset A Out 70 RD10 PoL 10 Enable
63 RC12 Reset B Out 71 RD11 PoL 11 Enable
64 RC15 Reset C Out 79 RD12 PoL 12 Enable
17 TMS/RA0 Enable/Board Seated
18 AN20/RE8 Low Power Shutdown
Comments
A These signals are required for the part to be ICSP and ICD.
B All power related pins
C Board ID pins to define various configurations.
D I2C interface.
E Spare pins for assignment
F Misc CMD I/O for on/off, and fault reporting
G1 VRM outputs and enables. Should be about to sequence these and define them to be tied to the MUX'd info. If not used with VRM, they are sequencable/monitored voltages
G2 MUX'd signals for use with VRMs. VID bits double as ID bits if necessary to support more board configs without 4 VRMs.
H Sequencable analog monitors. The Comp Out/Enable signal is dual purpose to either act as a comparator output or work like a sequencable/monitored voltage.
I Vin Monitor should be sequencable and tied to IO PIF Enable/OV Trip.
J PoL control works like TRKF-64D82ER device
Figure 3
I/O Grouping
5V Tolerant Pins
The following pins are 5V tolerant: 1, 10, 11, 12, 13, 14, 17, 38, 39, 40, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
58, 59, 60, 61, 66, 67, 68, 69, 70, 71, 72, 76, 77, 78, 79, 80, 81, 82, 83, 84, 87, 88, 89, 90, 95, 96, and 97.
The voltage on 5V tolerant digital input pins can exceed VDD as indicated in the Absolute Maximum Ratings
section. 5V tolerant digital output pins can be configured with the open-drain feature which allows the
generation of outputs higher than VDD by using external pull-up resistors. The maximum open-drain voltage
allowed is the same as the maximum VIH specification defined in the Electrical Specifications.
4
Powering the Sequencer
VDD Core
C8
2.2 uF
10v
X5R
Microchip P/N
D1 MCP1702T-3302I/MB
BAT54
+12Vin or Equivalent
In Out VDD
R1
20 Ohm
1206
C1
C2 3V3 Output LDO C4 C5 C6 C7
1000uF
1uF 1uF 1uF 1uF 1uF
+12Vin Return 25V
16v GND 16v 16v 16v 16v VSS
X5R R2
X5R X5R X5R X5R
4.64 Ohm
AVDD
C3
2.2 uF
10v
X5R
AVSS
R3
1 Ohm
FIGURE 4
VDD Interface
Figure 4 is a schematic of the typical VDD interface to the sequencer IC. A Microchip LDO, P/N MCP1702T-
3302I/MB, is used to produce the 3.3V VDD supply to the DSP. This device is in a SOT89 package and in most
applications will be sufficient in size to handle the power dissipation when powering the circuit from a 12V
source. Capacitors C4, C5, C6, and C7 are the decoupling capacitors for the DSP and they should be located
directly across each pair of VDD and VSS pins on the DSP IC. The 64 pin device has a VDD core pin which is
used to decouple the internally generated core voltage. Capacitor C8 is the decoupling capacitor for the VDD
core which is not required with the 44 pin device. This decoupling capacitor should be a low ESR ceramic
capacitor and can be as large as 10uF. Capacitor C3 is the decoupling capacitor for the analog VDD (AVDD) and
it should be located directly across the AVDD and AVSS pins on the DSP IC. Resistor R2 in combination with C3
provides a filter for the analog VDD. Resistor R3 is intended to separate AVSS from VSS. Capacitor C2 is the
input decoupling capacitor for the LDO and it should be connected directly across the LDOs input and ground
pins. Capacitor C1 is used as a hold up capacitor. Its purpose is to hold up the supply voltage to the LDO and
maintain a stable VDD for the DSP for a short period after the +12Vin source is removed. This would be desired if
a short communication stream is required during power down or if storing system data to EE memory is required
during power down. The Schottky diode D1 prevents C1 from being discharged after +12Vin is removed.
Resistor R1 is used to protect D1 during the inrush event associated with the application of the +12Vin. The
single pulse peak current rating for a typical BAT54 diode is approximately 600mA. If the rise time of the +12V
source is slow enough to limit the peak charging current into C1 it is possible to eliminate R1. Assuming a
40mA current draw by the DSP C1 will provide approximately 188 uS of hold up time per uF of capacitance.
5
Using the PWM Trim Outputs
+Sense
+Vin
Ry Zf
TRIM Zi -
Rx +Vout
Rz E/A PWM
Reference
Figure 5A.
+Sense
+Vin
Zf
Zi -
+Vout
E/A PWM
TRIM
Rx Ry
Reference
Figure 5B.
+Sense
+Vin
Zf
Zi -
+Vout
E/A PWM
Reference
+
uController
TRIM
or Equivalent
Figure 5C.
6
The drawings in figure 5 show the three most common trim methods used in PoL converters. In all of these
schemes a power conversion stage contains a PWM device that receives a control voltage from an error
amplifier. The error amplifier (E/A) compares a scaled version of the output voltage to a reference. The output
voltage of the converter module is simply the reciprocal of the scaling factor multiplied by the reference value.
The output voltage can be adjusted by changing this scaling factor (Figure 5A) or by modifying the reference
(Figures 5B, C).
The most common trim method is shown in figure 5A. The popularity of this method stems from the fact that
most highly integrated PWM control ICs have an internal reference that is not accessible and cannot be
controlled externally. In this scheme the output is scaled by adding a resistor from the trim pin to ground. This
modifies the feedback divider and moves the output voltage to a higher value. The output can also be modified
by superimposing an offset voltage on the feedback divider by connecting a voltage source to the trim pin
through a resistor. Either of these two approaches will move the output voltage to a new value. The common
characteristic of modules with this trim scheme is that a lower value trim resistor to ground will cause a higher
output voltage or a larger voltage superimposed on the trim pin will cause Vout to decrease.
Some PoL converters incorporate the trim scheme shown in figure 5B. With this method the feedback ratio is
kept constant and the reference value is modified to move the output voltage. The common characteristic of
modules with this trim scheme is that a lower value trim resistor to ground will cause a lower output voltage and
a larger voltage superimposed on the trim pin will cause Vout to increase.
The method shown in figure 5C is occasionally used. This is similar to the method in figure 5B except the
modification of the reference is mapped through a device such as a microcontroller. This is the least common
of the 3 methods and requires the vendors data sheet to determine the trim characteristic because the micro
controller can map the reference in many different ways.
VTrim Ripple PoL Vout

or
VTrim Average VDD
Margin PWM PoL Trim Pin

Ca
Ra Rb
3V3
Ca
0 Margin PWM PoL Trim Pin
Ra Rb
3V3
VTrim Average
0
VTrim Ripple
Figure 6A Figure 6B
The power sequencer has the ability to do independent closed loop trim and closed loop margining of the output
voltage for each PoL controlled by the device. Each PoLs output voltage is monitored and by an analog to
digital converter (ADC) in a continuous loop. In firmware the most recent measured output voltage is compared
against the desired value and the PoLs output is adjusted by delivering a trim value to the corresponding PoLs
trim pin. This trim voltage is created from a digital PWM output and an external low pass filter. Each digital
PWM is labeled <PoL n Margin PWM> where n indicates a specific converter which corresponds to the
monitoring channel labeled with the same n value. The external low pass filter creates a DC value from the
PWM signal which is then delivered to each PoL converter through a range limiting resistor.
Figure 6 shows the typical circuits used to interface the sequencers Margin PWM signals to PoL converters. In
each of the circuits shown Ra and Ca construct a low pass filter while Rb is used to limit the trim range. The
effective trim voltage is equal to the Margin PWM duty cycle multiplied by VDD and is controllable in 1024 steps
7
from 0 to VDD. The effective trim resistor value is equal to Ra + Rb. Ra and Ca are chosen to reduce the trim
voltage ripple. Typical values for Ra and Ca are 1K for Ra and 0.22uF to 1uF for Ca. Rb is used to limit the
control range and should be selected based on the desired control range and the trim equation for the PoL.
This trim equation is usually available from the PoL manufactures data sheet. The sequencer learns the trim
direction by making a minor adjustment to the Margin PWM and then determining the direction that Vout moves
based on this stimulus. Once the trim direction is known it knows whether increment or decrement the TRIM
PWM value until the desired Vout is achieved. The accuracy of the active trim is a function of the ADC accuracy
which is mostly controlled by accuracy of the applied reference to the sequencers Vref pins.
Either circuit in Figure 6 will work with any of the trim methods shown in Figure 5. When interfacing to PoL
modules that use the trim method in Figure 5A the circuit in Figure 6B is the optimum interface configuration. By
connecting the filter capacitor Ca to the PoLs Vout or to a positive voltage reference the effective of filtering the
Margin PWM signal remains intact. With this method there will not be a discharged capacitor connected to
ground that could cause the PoLs output to overshoot during power up as this capacitor becomes charged. In
the case that the circuit in figure 6A is used with the trim configuration in Figure 5B the sequencer will pre-
charge the capacitor before enabling the PoL converter and then decrement the Margin PWM to achieve the
desired Vout. This requires additional start up time during system initialization. When interfacing to PoL
converters of the type shown in Figure 5B the interface circuit in figure 6A is optimum.
Monitoring Via ADC Channels
The imbedded ADC channels are converted as 10 bit results with full scale equal to a chosen reference. The
device is intended to be powered from a 3V3 source and can be configured to use this source as the ADC
reference or to use an externally provided reference. Closed loop margining and set point adjustments always
use the entire 10 bit result to trim the output voltages to loaded values. Monitored voltages are reported via I2C
communication using PMBus data formats as defined in the separate communication manual. The voltage
range reported is determined by the entered set points. Any monitored output that is greater than the ADC
reference or that can be margined above this reference should have a voltage divider to limit the maximum input
to the corresponding ADC channel to a value equal or less than the ADC reference. Monitored voltages below
the chosen ADC reference do not require this voltage divider. A four sample moving average is used to filter the
ADC results. In most cases this will eliminate the need for external filtering.
The input voltage (Vin) monitoring channel requires a voltage divider so that Vin maximum is scaled to a value
less than the maximum value of the ADC reference.
Connecting the Control and Monitoring

The three primary control interface signals to the attached PoL converters are an enable signal, a voltage
monitoring signal, and trim control signal. The enable signals are labeled <PoL n Enable>. The Monitoring
signals are labeled <PoL Monitor n>. The trim signals are labeled <PoL n Margin PWM>. Each nth PoL
converter is required to share the corresponding enable, monitor, and trim signals. For example the first PoL
converter attached to the controller is PoL 1. PoL 1 should use <PoL 1 Enable>, <PoL Monitor 1>, and PoL 1
Margin PWM, etc... The installed firmware assumes that the connections are made this way when controlling
system.
Communicating with the Device

Serial communication is achieved via an I2C bus. The communication protocol is derived from the PMBus
command set and is defined in a separate communications manual. The communications manual also defines
the protocol for device programming via embedded boot loader software.
8
** If VRM n (n=A, B, C, or D) is not used, then Analog n (n=A, B, C, or D) will be used.
9
Absolute Maximum Ratings

Ambient temperature under bias.............................................................................................................. .-40C to +85C
Storage temperature .............................................................................................................................. -65C to +150C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS ...................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V..................................................... -0.3V to +5.6V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V.......................................... -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS ................................................................................................ 2.25V to 2.75V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ................................................................................................... ..........................250 mA
Maximum output current sunk by any I/O pin............................................................................................................4 mA
Maximum output current sourced by any I/O pin ......................................................................................................4 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ...................................... ...........................................................................200 mA
Electrical Specifications
Parameter Symbol Min Typ Max Units Notes
Input Voltage Range VDD 3.0 3.30 3.6 VDC
Input Current IDD 58 mA +85C
Logic Low Input Level VIL VSS 0.2*VDD VDC
VDD Non 5V tolerant pins
Logic High Input Level VIH 0.7*VDD VDC
5.5 5V tolerant pins
Logic Low Output Level VOL 0.4 VDC VDD = 3.3V
Logic High Output Level VOH 2.4 VDC VDD = 3.3V, IOH = -3.0mA
VDD Rise Rate SVDD 0.05 V/uS 0 to 3.3V in 100mS
Capacitance I/O Pin to GND CIO 50 pF
I2C Bus Capacitance CB 400 pF SCl and SDA
PWM Series Resistor RPWM 1 K External Series Resistor
Margin PWM Frequency FPWM 10 KHz
Reference Input Vref AVSS + 1.7 AVDD VDC
Program Flash Memory Cell 100 E/W TRKF-10DC4ER
EP
Endurance 10,000 cycles TKRA-10DC4ER
10
Mechanical Outline
Figure 8A
100-Lead Plastic Thin-Quad Flatpack, 12 x 12 x 1 mm Body
Units Inches Millimeters*
Dimension Limits Min. Nom. Max. Min. Nom. Max.
Number of Pins N 100 100
Pitch p 0.0157 0.40 BSC
Leasds per Side n1 25 25
Overall Height A 0.047 1.20
Molded Package Thickness A2 0.037 0.039 0.041 0.95 1.00 1.05
Standoff A1 0.002 0.006 0.05 0.15
Foot Length L 0.018 0.024 0.030 0.45 0.60 0.75
Footprint F 0.039 REF 1.00 REF
Foot Angle G 0 3.5 7 0 3.5 7
Overall Width E 0.551 14.00 BSC
Overall Length D 0.551 14.00 BSC
Molded Package Width E1 0.472 12.00 BSC
Molded Package Length D1 0.472. 12.00 BSC
Lead Thickness c 0.004 0.008 0.09 0.20
Lead Width B 0.005 0.007 0.009 0.13 0.18 0.23
Molded Draft Angle Top H 11 12 13 11 12 13
Molded Draft Angle Bottom J 11 12 13 11 12 13
* Controlling Parameter
Notes:
1. Dimensions D1 and E1 do not include mold flash or protrusions (not to exceed .010" (0.254mm) per side).
2. Chamfers at corners are optional; size may vary.
3. REF: Reference Dimension, usually without tolerance , for information purposes only.
4. Dimensioning and tolerancing per ASME Y14.5m. BSC = Basic Dimension
Figure 8B
11
Revision History
Date Revision Changes Detail Approval
2007-5-7 A First release.
Reformatted document.
2010-7-21 B Added Program Flash Memory Cell Endurance specification. S. Moore
Added TRKA-10DC4ER.
Corrected figure with page information in Communicating with the
2010-7-26 C S. Moore
Device section.
2014-2-10 D Added information about 5V tolerant pins. S. Moore
Errata
Refer to TRKx-10DC4ER Errata document for additional information specific to each code release.
RoHS Compliance
Complies with the European Directive 2002/95/EC, calling for the elimination of lead and
other hazardous substances from electronic products.
2014 Bel Fuse Inc. Specifications subject to change without notice.
12
CORPORATE FAR EAST EUROPE
Bel Fuse Inc. Bel Fuse Ltd. Bel Fuse Europe Ltd.
206 Van Vorst Street 8F/ 8 Luk Hop Street Preston Technology Management Centre
Jersey City, NJ 07302 San Po Kong Marsh Lane, Suite G7, Preston
Tel 201-432-0463 Kowloon, Hong Kong Lancashire, PR1 8UD, U.K.
Fax 201-432-9542 Tel 852-2328-5515 Tel 44-1772-556601
www.belfuse.com Fax 852-2352-3706 Fax 44-1772-888366
www.belfuse.com www.belfuse.com

TRKX 10DC4ER Datasheet D

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TRKX 10DC4ER Datasheet D

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Power System Sequencer

Vout ADC Input

Using the PWM Trim Outputs

VTrim Ripple PoL Vout

Margin PWM PoL Trim Pin

Monitoring Via ADC Channels

Connecting the Control and Monitoring

Communicating with the Device

** If VRM n (n=A, B, C, or D) is not used, then Analog n (n=A, B, C, or D) will be used.

Absolute Maximum Ratings

2014 Bel Fuse Inc. Specifications subject to change without notice.

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