Hi-Rel Modular Two-Speed Synchro/Resolver To Digital Converter

We Provide Chinas High Reliability Products to the Global Market.
Hi-Rel Modular Two-Speed Synchro/Resolver to Digital Converter
(MTS Series)
1 Features (Figure1, Table1)
A Complete Two-Speed System
1:64, 1:32, 1:16, 1:8, 1:20, 1:36 (Set by Users)
Three-State Latched Output
Up to 20-bit Resolution
Size: 79.4*66.7*18.5 mm3 (Type A)
Up to 5 Arc Second Accuracy
79.4*66.7*11.3 mm3 (Type B);
Weight: 190 g(Type A), 103 g (Type B)
Figure 1 Appearance for MTS Series
Table 1 Ordering Information
Synchro Resolver
MTS19R36-418
MTS36S-412
(MTS36R-418)
MTS16S-412 MTS36R-467
2 Target Applications
Radar Measuring and Control; Navigations; Satellite Tracking; Simulation Technology; Artillery Fire Control
Systems; Industrial Machine Tooling Control; Other high accuracy measurements.
3 General Description
The MTS series of two-speed synchro/resolver to digital converters are modular structured single circuit,
including coarse and fine function generation circuits and a processing circuit which is necessary for a
two-speed system.
According to operation modes, the MTS single modular two-speed converters can be classified into two
categories:
(1) Combined Two-Speed Converter
Data-sheet subject to change without notice

Prices and Technical Supports Directly Guide: sales@ielectronics.com.cn
(2) Continuous Two-Speed Converter
The products stated speed ratios of the combination of coarse and fine can be any value between 1:2
and 1:64 The input signals of the coarse and fine channels are three-wire synchro or four-wire resolver
signals. The converters output natural parallel binary code and the resolution can be up to 20 bits with
three-state latches.
4 Technical Characteristics(Table 2 Table 3)

Table 2 Rated Condition and Recommended operating condition
Power Supply Voltage Vs: 17 V
Absolute Maximum Ratings 5 V Power Supply Voltage VL: 7 V
Storage Temperature Range-55+105
Power Supply Voltage +Vs: 15 V 0.75 V
Power Supply Voltage -Vs: -15 V 0.75 V
5 V Power Supply Voltage VL: 5 V 0.25 V
Recommended operating condition Reference Voltage Effective Value V *: 2~115 V
Ref
Signal Voltage Effective Value VI*: 2~90 V

Reference Frequency f*: 50 ~10 kHz
Operating Temperature Range TA: -55~+105
Table 3 Electrical Characteristics

MTS Series
Enterprise Military Standard
Characteristics Conditions
O/HW30925-2006
Min Max
Speed ratio 18 17
Speed ratio 120 18
Resolution
Speed ratio 136 19
Speed ratio 164 20
Speed ratio 18 40
Accuracy Speed ratio 120 20
0360 Speed ratio 136 10
Speed ratio 164 5
Fine Channel Tracking Rate/rev/s 400Hz 36
Frequency /Hz 50 10 000
Exciting Voltage Range (EV)/V 2 115
Signal Voltage Range(EV)/V 2 90
Power Dissipation/W 15 V, +5 V 2.5

5 Theory of Operation (Figure 2, 3 and 4)
(1) Combined Two-Speed Converter
The function digram of the combined two-speed converter is shown in Figure 2. For two-speed converter, its
coarse and fine channels operation theory are the same as the one of single-speed converter. But it is combined
with two single-speed converters and a programmer error-correcting logic circuit. The coarse channel converts
10~12 bits analog angle to digital angle and the fine channel converts 14 bits analog angle to digital angle. The
results from the two channels are then sent to a logic circuit for error processing and correction respectively. After
that, it outputs a 20-bit parallel binary digital value that is subsequently converted to a digital angle through a
latch buffer.
Figure 2 Combined Two-Speed Converter Function Diagram
(2) Continuous Two-Speed Converter

The continuous two-speed converter has error signal generator circuits for both coarse and fine channels. The
two circuits are controlled by up-down counters. According to the coarse axial error, the cross detector selects
one signal out of the two coarse and fine error signals for integration and the result is supposed to control the
VCO, making the counter working and three-state latched output. Its function diagram is shown in Figure 3.
This series of product consists of the following parts:

1 Interface circuit;
2 Data processing circuit;
3 Function generator circuit;

4 Cross detection circuit;
5 False zero point elimination circuit;
6 Synchronous reference circuit;

7 20-bit counter.
The coarse and fine signals are connected to the analog inputs of the continuous synchro/resolver to digital
converter respectively (original for coarse channel and 36 bits for fine channel), and are converted to latched
output of angular binary code (up to 20 bits).
Figure 3 Continuous Two-Speed Converter Function Diagram
(3) Data Transfer Methods and Timing

The output of the MTS series can be up to 20 bits and is three-state controlled through EnableLo, EnableMi and
EnableHi , which makes convenient connection between the two-speed converters and the data bus. The

EnableLo, EnableMi and EnableHi are all active low. The EnableLo controls the 8 least significant bits, the

EnableMi controls the 8 middle significant bits and the EnableHi controls the remaining most significant bits.
The way of reading the converters valid data is as follows:


Set the Inhibit to a logic 0; latch the converters valid data; wait for 490 ns. Now the data from different bits

can be input by controlling the EnableLo, EnableMi and EnableHi . The following is the timing diagram of the
converter connecting to a 8-bit bus.
Figure 4 8-bit Bus Transfer Timing Diagram
To ensure high accuracy conversion of the two-speed converter, please note:

(1) The amplitude variation of the input signals for both coarse and fine channels should be within 10% of the
nominal value.
(2) The frequency of the input signals and reference signals for both coarse and fine channels should be within
the specified operating frequency range.

(3) When using combined two-speed converter (Type A):
(a) The phase shift between input signals and reference signals for coarse channels should be less than 10
degrees.
(b) The phase shift between input signals and reference signals for fine channels should be less than 10
degrees.
(4) The wave distortion of the input signals and reference signals for both coarse and fine channels should be less
than 10%.
(5) The voltage variation of +5 V, 15 V power supplies should be less than 5%.

6 M TBF Curve(Figure 5)
Figure 5 MTBF Temperature Curve
Note: GJB/Z 299B-98Ground Benign
7 Pin Configuration(Figure 6, Table 4)
Figure 6 Pins (Top View)

Table 4 Pin Configuration
Pin NO. Symbol Function Pin NO. Symbol Function
1 A s4 Fine channel signal input 35 D8 Data output bit 8

4 As 2 Fine channel signal input 38 D11 Data output bit 11
8 RLo Excitation input low 39 D12 Data output bit 12
9 RHi Excitation input high 40 D13 Data output bit 13
10 T2 Signal and reference phase shift 41 D14 Data output bit 14
11 T1 Signal and regulation
reference phase shift 42 D15 Data output bit 15
regulation
13 Bs 3 Coarse channel signal input 43 D16 Data output bit 16
16 Bs 4 Coarse channel signal input 46 D19 Data output low bit 19
24 +15V L15V Power supply 47 D20 Data output low bit 20
25 -15V 15V Power supply 48 Inhibit Inhibitpulled-up internally
26 GND Ground 49 CB Busy output
27 L5V L5V Power supply 50 Vel Velocity output
28 MSBD1 Data output high bit 1 51 Bit Bit signal output
29 D2 Data output high bit 2 52 Enable Hi High 3 bits Enable
30 D3 Data output bit 3 53 Enable Mi Middle 8 bits enable
D4
31 Data output bit 4
D5
D6 54 Enable Lo Low 8 bits enable
D7
Notes:
1 As1, As2, As3 and As 4 are fine channel inputs. For three-wire synchro, As4 is unused.
2 Bs1, Bs 2, Bs3 and Bs 4 are coarse channel inputs. For three-wire synchro, Bs 4 is unused.
3 RHi and RLo are reference signal inputs.

4 Inhibit is the inhibit signal, which has been connected to 5 V power supply via an internal pull-up

resistor. When the Inhibit is set to logic 0, the converter is in a disable state and, after 490 ns, it outputs
valid data; while it is set to logic 1, the converter resumes the tracking state and now it outputs invalid data.

5 EnableLo, EnableMi and EnableHi are three-state latch control pins, which determine the output data
state. When they are in logic 1 state, the data output is in a high-impedance state. Conversely, when they
are in logic 0 state, the converter outputs valid data after 200 ns. The state of the output data will not affect

the internal loop operation. The EnableLo controls the 8 least significant bits, the EnableMi controls the 8

middle significant bits and the EnableHi controls the other most significant bits.
6 T1 and T2 , shown in Figure 7, are the regulatory network between fine channel signals and references
(unused for continuous two-speed converter since it has internal phase self-adapting circuit).
Select proper R and C to make the phase shift less than 10 degrees. During debug, the R.C network can be
regulated according to the lead and lag relations of the phase shift. Short T1 and T2 together if there is no
need to regulate the phase shift.

Figure 7 Phase Shift Regulation Network
7 Vel: Fine channel velocity signal.

8 D1~D20 are the combinational digital angle outputs, where D20 is the least significant valid bit.
8 Bit Weight Table(Table 5)

Table 5 Bit Weight Table
Bit Number Weight in Bit Weight in Bit Weight in degrees
1(MSB) 180.000 0 8 1.106 3 10 0.01140 s
2 90.000 0 9 0.703 1 16 0.005520 s
3 45.000 0 10 0.351 6 17 0.0027510 s
4 22.500 0 11 0.175 8 18 0.001385 s
5 11.250 0 12 0.087 9 19 6.88X10-42.5 s
6 5.625 0 13 0.043 9 20 3.44X10-41.25 s
7 2.812 5 14 0.022 0
9 Connecting the Converter

15V, +5V and ground are connected to the corresponding pins of the converter and the polarity of
the power supply must be correct, or it will damage the device. It is suggested that a parallel
combination of a 0.1 F and a 6.8F bypass capacitor is placed from each of the three supply pins to G
ND.
Signals and stimulus sources are connected to S 1S 2S 3S 4 and RHiRLo pins with the maximum
acceptable error of 5%.
The phase of the signal must match the one of the stimulus source. Their phases are as follows:
RHiRLo: VRef sint
For synchro:
S 1S 3ES1S3=ERLoRHisinsint
S 3S 2ES3S2=ERLoRHisin+1200sint

S 2S 3ES1S3=ERLoRHisin+2400sint
For resolver:
S 1S 3ES1S3=ERLoRHisinsint
S 2S 4ES2S4=ERLoRHicossint
Note: The input signals of RHiRLoS 1S 2S 3 and S 4 are not allowed to be connected to other pins, or
the device may be damaged. Other pins should be connected according to pin configuration. It is
suggested by the manufacturer that when non-nominal synchro or resolver is needed, ask them to make
it according to the specified parameters.
10 Outline Dimensions and Instructions(Unit:mm)(Figure 8)
Figure 8 Outline Dimensions

11 Part Number Ex planation (Figure 9)
Figure 9 Part Number Explanation

Note: Non-nominal signal voltage and Non-nominal reference voltage (Z) are given as follows:
( For example: -5/3 stands for that the reference voltage is 5V and the signal voltage is 3V.)
Notes:
Make sure that the polarity of the power supply is correct.
Operating at the condition that exceeds the maximum ratings may cause damages to devices.
During product assembly, keep the bottom of product close to the circuit board so as to avoid damages of
pins. Add antihunting protection when it is necessary.

Customers should specify the detailed electrical properties according to their own standard when ordering.


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We Provide Chinas High Reliability Products to the Global Market.

Hi-Rel Modular Two-Speed Synchro/Resolver to Digital Converter

1 Features (Figure1, Table1)

A Complete Two-Speed System

1:64, 1:32, 1:16, 1:8, 1:20, 1:36 (Set by Users)

Three-State Latched Output

Figure 1 Appearance for MTS Series

Table 1 Ordering Information

Data-sheet subject to change without notice

4 Technical Characteristics(Table 2 Table 3)

Signal Voltage Effective Value VI*: 2~90 V

Table 3 Electrical Characteristics

Data-sheet subject to change without notice

Figure 2 Combined Two-Speed Converter Function Diagram

(2) Continuous Two-Speed Converter

This series of product consists of the following parts:

2 Data processing circuit;

3 Function generator circuit;

6 Synchronous reference circuit;

Figure 3 Continuous Two-Speed Converter Function Diagram

(3) Data Transfer Methods and Timing

The way of reading the converters valid data is as follows:

Data-sheet subject to change without notice

converter connecting to a 8-bit bus.

Figure 4 8-bit Bus Transfer Timing Diagram

To ensure high accuracy conversion of the two-speed converter, please note:

the specified operating frequency range.

Data-sheet subject to change without notice

Figure 5 MTBF Temperature Curve

Note: GJB/Z 299B-98Ground Benign

7 Pin Configuration(Figure 6, Table 4)

Figure 6 Pins (Top View)

Pin NO. Symbol Function Pin NO. Symbol Function

1 A s4 Fine channel signal input 35 D8 Data output bit 8

Data-sheet subject to change without notice

Figure 7 Phase Shift Regulation Network

7 Vel: Fine channel velocity signal.

8 Bit Weight Table(Table 5)

9 Connecting the Converter

acceptable error of 5%.

RHiRLo: VRef sint

Data-sheet subject to change without notice

it according to the specified parameters.

10 Outline Dimensions and Instructions(Unit:mm)(Figure 8)

Figure 8 Outline Dimensions

Data-sheet subject to change without notice

Figure 9 Part Number Explanation

pins. Add antihunting protection when it is necessary.

Data-sheet subject to change without notice

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