DRC fixing in ICC

Note:

Use IcInteractive to analyze the routing DRCs after Route or Retoute stage. Without
analyzing and understanding the DRCs violations dont try to fix them

If total number of routing violation are 1000 or less, then try my techniques to clean upt
the DRCs, otherwise try to find out the main reason for the more DRCs and fix that to
reduce the total violations in Route and ReRoute stages.

If you think that there are no options bring down the violations below 1000
automatically, try medium effort for timing_driven_effort. That may help to reduce the
congestion, but it will affect the timing.

Go through the solvent training on ICC GUI

o https://solvnet.synopsys.com/retrieve/021870.html?
otSearchResultSrc=advSearch&otSearchResultNumber=7&otPageNum=1

Most important ones are

Part 1 - IC Compiler Gui Cockpit Overview - Show basic GUI operations of windows, menu
bar, hot keys, command console, GUI customization, object display, object querying, object
selection, cross view links, visual mode analysis
Part 3 - IC Compiler Gui Cockpit - Editing - Basic editing features

Part 4 - IC Compiler Gui Cockpit - Error Browser - Error browser for LVS/DRC verification
run output
Analyzing the initial violations
Open MW ReRoute data in ICC using IcInteractive to check the DRC violations. Start
working on the Reroute data. It is better to fix the DRC violations before the ECO steps. This
step will tell whether we can clean up the routing DRCs are not.

Use the verify_zrt_rotue to reload the DRC violations after proper settings.

Settings to load the DRC violations in the GUI using IcInteractive

#----------------------------------------------------------------------
if { [string range $compatibility_version 2 8] >= 2009.06 } {
set_host_options -max_cores 4
}

set_ignored_layers -max_routing_layer M8
suppress_message APL-006
set_lib_cell_spacing_label -names {left_gap_rule right_gap_rule} -right_lib_cells * -left_lib_cells *
set_spacing_label_rule -labels {left_gap_rule right_gap_rule} {1 1}

# Enable Zroute mode

set_route_mode_options -zroute true

source -verbose -echo /proj/tahiti-pd2-

nobackup/mhulten/tiles/dca_t/NL3p0_fp24/TB_RUN1/TileBuilder/supra/technology/tsmc_ip/28hp/IcRoute.ant
enna_rules.tcl

set_route_zrt_common_options -max_layer_mode allow_pin_connection

if { [string range $compatibility_version 2 8] > 2010.03 || ([string range $compatibility_version 2 8] == 2010.03
&& [string range $compatibility_version 16 16] >= 2) } {
set_route_zrt_detail_options -drc_convergence_effort_level high
set_route_zrt_common_options -routing_rule_effort_level medium
set_route_zrt_common_options -route_soft_rule_effort_level medium
}
# set to 5 to work in the general case
set_route_zrt_common_options -number_of_vias_over_max_layer 5
set_route_zrt_detail_options -antenna true

set_route_zrt_common_options -connect_within_pins { \
{m1 via_wire_standard_cell_pins} \
{m2 via_wire_standard_cell_pins} \
{m3 via_wire_standard_cell_pins} \
{m4 via_wire_standard_cell_pins} \
{m5 via_wire_standard_cell_pins} \
{m6 via_wire_standard_cell_pins} \
{m7 via_wire_standard_cell_pins} \
{m8 via_wire_standard_cell_pins} \
{m9 via_wire_standard_cell_pins} \
{m10 via_wire_standard_cell_pins} \
{m11 via_wire_standard_cell_pins} \
{m12 via_wire_standard_cell_pins} \
 {m13 via_wire_standard_cell_pins} \
{m14 via_wire_standard_cell_pins} \
{m15 via_wire_standard_cell_pins} \
}
set_route_zrt_common_options -read_user_metal_blockage_layer true

source -echo -verbose /proj/tahiti-pd2-

nobackup/mhulten/tiles/dca_t/NL3p0_fp24/TB_RUN1/TileBuilder/supra/technology/tsmc_ip/28hp/IcRoute.defi
ne_zrt_redundant_via.tcl

verify_zrt_route
#----------------------------------------------------------------------

For example after the after the verify_zrt_route log file shows
DRC-SUMMARY:
@@@@@@@ TOTAL VIOLATIONS = 818
Diff net spacing : 278
End of line spacing : 184
Same net spacing : 2
Diff net via-cut spacing : 4
Less than minimum area : 38
Less than minimum edge length : 3
Same net fat extension spacing : 1
Fat wire via keepout enclosure : 19
Connection not within pin : 1
Short : 101
Edge-line via spacing : 1
Soft spacing (user) : 186
Image of routing all DRCs looks as follows

Image of only shorts looks as follows

Fixing the Routing DRCs in ICC
From above two images it is clear that shorts are bunched together. There are some isolated
violations (as per the first image). These isolated DRCs can be cleaned up by running additional
routing loops non-timing driven & turning of the redundant VIA optimization

# Step 1
set_route_zrt_detail_options -timing_driven false
set_route_zrt_common_options -concurrent_redundant_via_mode off
set_route_zrt_common_options -post_detail_route_redundant_via_insertion off
route_zrt_detail -initial_drc_from_input true -incremental true

This step brought down the total violations as follows

DRC-SUMMARY:
@@@@@@@ TOTAL VIOLATIONS = 581
Diff net spacing : 232
End of line spacing : 119
Same net spacing : 1
Diff net via-cut spacing : 2
Less than minimum area : 20
Less than minimum edge length : 3
Enclosed via spacing : 3
Diff net fat extension spacing : 3
Fat wire via keepout enclosure : 12
Short : 93
Edge-line via spacing : 1
Soft spacing (user) : 92
All violations image after step1 fix:

Only shorts image after Step 1 DRC fix

Shorts fixing
Now it is time to fix the shorts. Best way fix shorts is to remove shorted NETs ( exclude the
Clocks, Power & Ground from shorts for deletion) and re-route them will bring down violations
drastically.

Here is the small script that identifies the shorted nets and filter out the only signal nets.
Removing those nets and rerouting those nets can decrease the shorts. Make sure to turn off
crosstalk option to converge on Routing DRCs

set_route_zrt_track_options -crosstalk_driven false

set_si_options -delta_delay false -min_delta_delay false

set all_shorted_nets [filter_collection [get_attribute -class drc_error [get_drc_errors -type

{Short}] nets] "net_type==Signal"]
set num_short_nets [sizeof_collection $all_shorted_nets]
echo "Number of Shorts $num_short_nets\n"
echo "Note: All shorted nets are deleted except Clock, Power & Ground nets and rerouted
for DRC clean up\n"
remove_route_by_type -signal_detail_route -nets $all_shorted_nets
route_zrt_group -nets [get_nets $all_shorted_nets]

After once round of shorts fixing, total DRCs came down to 525 from 581. Shorts are reduced to
61 from 93.

One set of incremental DRC fixing also further reduced total violations to 390 and shorts are
down to 46.
route_zrt_detail -initial_drc_from_input true -incremental true

DRC-SUMMARY:
@@@@@@@ TOTAL VIOLATIONS = 390
Diff net spacing : 160
End of line spacing : 71
Same net spacing : 1
Less than minimum area : 22
Less than minimum edge length : 1
Same net fat extension spacing : 1
Fat wire via keepout enclosure : 2
Short : 46
Edge-line via spacing : 3
Soft spacing (user) : 50
Soft spacing : 33
Here are the images violations after one routing of shorts fixing followed by incremental DRC
fixing

All violations

Only shorts
Since there are still short, it is better to run one more round of shorts fixing along with
incremental DRC fixing.

Keep the database saved after each DRC fixing step (may dumpout DEF & verilog). If the
violations are increased with any step, go back to the previous version of data (CEL) to try
different techniques.

To save the data

save_mw_cel as drc_fix1

To close the current cell and open the new cel:

close_mw_cel

open_mw_cel drc_fix1

Last technique to clean up the few remaining shorts is to trace the routing of cells near the shorts,
and move out some cells from shorts area. Before moving the cells make sure the filler cells are
removed and also set proper snap options to make sure moved cells are automatic legalized.
Final steps
Additional Redundant via insertion is run if the DFM % is very less after fixing DRC violations.
Command is without any options

insert_zrt_redundant_vias

It is good to have DRC clean at this point. Even if there are 100 violations, users can continue to
ECO steps.

Manual removal violating segments and running route_zrt_eco also done to fix some
violations.

Final ECO run stage, NDR rules can be removed to fix last few violations.

As a summary, running couple of short NETs removal and re-routing along with incremental
routing clean up most of the violations. These steps can be added to tune file of IcEcoRoute
Tune file supposed to contain
report_host_options

verify_zrt_route

# Do a final cleanup of DRC violation

# Step 1 : Incremental routing
set_route_zrt_detail_options -timing_driven false
set_route_zrt_common_options -concurrent_redundant_via_mode off
set_route_zrt_common_options -post_detail_route_redundant_via_insertion
off
route_zrt_detail -initial_drc_from_input true -incremental true

# Step 2 : Short nets removal and re-routing

set_route_zrt_track_options -crosstalk_driven false
set_si_options -delta_delay false -min_delta_delay false

set all_shorted_nets [filter_collection [get_attribute -class drc_error

[get_drc_errors -type {Short}] nets] "net_type==Signal"]
set num_short_nets [sizeof_collection $all_shorted_nets]
echo "Number of Shorts $num_short_nets\n"
echo "Note: All shorted nets are deleted except Clock, Power & Ground
nets and rerouted for DRC clean up\n"
remove_route_by_type -signal_detail_route -nets $all_shorted_nets
route_zrt_group -nets [get_nets $all_shorted_nets]

# Step 3: Incremental routing

route_zrt_detail -initial_drc_from_input true -incremental true

# Step 4: Short NETS removal and re-routing

set all_shorted_nets [filter_collection [get_attribute -class drc_error
[get_drc_errors -type {Short}] nets] "net_type==Signal"]
set num_short_nets [sizeof_collection $all_shorted_nets]
echo "Number of Shorts $num_short_nets\n"
echo "Note: All shorted nets are deleted except Clock, Power & Ground
nets and rerouted for DRC clean up\n"
remove_route_by_type -signal_detail_route -nets $all_shorted_nets
route_zrt_group -nets [get_nets $all_shorted_nets]

# Step 5: Incremental routing

route_zrt_detail -initial_drc_from_input true -incremental true
Analyzing the DRC violations
Use the Tilebuilder terminal to invoke the IcInteractve for loading the routed DEF to the ICC
Gui

Usage

IcInteractive data/ReRoute.def.gz

Load the remaining routing options before the doing verify DRC verify_zrt_route to load the
routing DRCs

Get these commands from IcRoute or IcReRoute

#----------------------------------------------------------------------
if { [string range $compatibility_version 2 8] >= 2009.06 } {
set_host_options -max_cores 4
}

set_ignored_layers -max_routing_layer M8
suppress_message APL-006
set_lib_cell_spacing_label -names {left_gap_rule right_gap_rule} -right_lib_cells * -left_lib_cells *
set_spacing_label_rule -labels {left_gap_rule right_gap_rule} {1 1}

# Enable Zroute mode

set_route_mode_options -zroute true

source -verbose -echo /proj/tahiti-pd2-

nobackup/mhulten/tiles/dca_t/NL3p0_fp24/TB_RUN1/TileBuilder/supra/technology/tsmc_ip/28hp/IcRoute.ant
enna_rules.tcl

set_route_zrt_common_options -max_layer_mode allow_pin_connection

if { [string range $compatibility_version 2 8] > 2010.03 || ([string range $compatibility_version 2 8] == 2010.03
&& [string range $compatibility_version 16 16] >= 2) } {
set_route_zrt_detail_options -drc_convergence_effort_level high
set_route_zrt_common_options -routing_rule_effort_level medium
set_route_zrt_common_options -route_soft_rule_effort_level medium
}
# set to 5 to work in the general case
set_route_zrt_common_options -number_of_vias_over_max_layer 5
set_route_zrt_detail_options -antenna true
 set_route_zrt_common_options -connect_within_pins { \
{m1 via_wire_standard_cell_pins} \
{m2 via_wire_standard_cell_pins} \
{m3 via_wire_standard_cell_pins} \
{m4 via_wire_standard_cell_pins} \
{m5 via_wire_standard_cell_pins} \
{m6 via_wire_standard_cell_pins} \
{m7 via_wire_standard_cell_pins} \
{m8 via_wire_standard_cell_pins} \
{m9 via_wire_standard_cell_pins} \
{m10 via_wire_standard_cell_pins} \
{m11 via_wire_standard_cell_pins} \
{m12 via_wire_standard_cell_pins} \
{m13 via_wire_standard_cell_pins} \
{m14 via_wire_standard_cell_pins} \
{m15 via_wire_standard_cell_pins} \
}
set_route_zrt_common_options -read_user_metal_blockage_layer true

source -echo -verbose /proj/tahiti-pd2-

nobackup/mhulten/tiles/dca_t/NL3p0_fp24/TB_RUN1/TileBuilder/supra/technology/tsmc_ip/28hp/IcRoute.defi
ne_zrt_redundant_via.tcl

verify_zrt_route
#-------------------------------------------------------------------------------------------------------------
Note: Command line option or tile param will be added soon to load these commands
automatically

IcInteractive automatically brings up the GUI. After the verify_zrt_route, you load the DRC
errors to the layout and analyze them.
Error browser
You can find the Error browser under the verification tab of layout window (or use the short cut
Ctrl+Shift+E).

Check the Detail Route and click OK, it brings up the Error browser
Click on the Detail Route to display all the detail route violations. You click on different
violation types to display only those violations
Click on the + to pulldown that Error category that displays the Errors of that type by Layer.
Options Show All and Follow Off to display all violations and not to zoom to one violation.
One DRC violation can be zoomed by changing these options Show-> All, Follow -> Zoom
and click on the violation that you want to zoom.

Toolbars
For GUI analysis, you need to have proper toolbars enabled. Toolbars are enabled or disabled
from the View pulldown menu of layout window.

Make sure to enable all the toolbars shown in the following image, that helps you to debug the
layout better
Changing the patterns of the metal layers
Sometimes user want to change the metal colors and patterns. Click the error to zoom to the
Error location. Then in the settings tab, click on the Layers

Hide -> to turn off all the routing layers

Show -> to show all the routing layers

To display only particular layers, click Hide and click on the required layers. Then do the righ
button click, it brings up the color pallet. Form the color pallet, user can select the color and
pattern for that particular layer.