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Starting With RedHawk Static

VERSION: V2.2-AL-RH101-28JUL2010
Agenda

Static Analysis Theory


RedHawk Static IR/EM Analysis Flow
Analysis of Results
Conclusions

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Static Voltage Drop Background

Vdd Pad Ipad

R
Iavg Iavg

Cload Cload

Vss Pad
Instance Instance

On-chip power/ground network mesh of resistors


Instances DC current sources

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Static Voltage Drop on P/G Network

Average current is calculated for each instance


Vstatic is computed at every node (Ohm's law ...)
Wire / via electromigration (EM) is post-processed from static
current density
Vstatic
Vdd Pad Ipad

R
Iavg Iavg

Vss Pad

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Gate-level Static Power and DC Current

Pavg = Pleakage + Pinternal + Pswitching

Gate Active Average Power is


function of input slew, output load
(.lib power tables)
linearly proportional to frequency
and toggle rate

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REDHAWK STATIC IR/EM
ANALYSIS FLOW

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Data Preparation

Data Preparation

Design Import
Copying the training
Power Calculation
tarball
Creating GSR and run
Power Grid Extraction command file
PG Weakness Analysis Setting up the
environment
Package Parasitics
Reviewing the user inputs
Static IR/EM Analysis

Result Exploration

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Static Analysis Flow and Required Data

Apache tech lef def/gds lib spef/dspf STA


(slew/clocks)

Optional improves accuracy


# Import data
import gsr GENERIC.gsr
setup design
User control file (GSR):
setup analysis_mode static
VDD_NETS {
VDD 1.2 # Calculate power
inst_129973/VDD_INT 1.2 perform pwrcalc
}
TOGGLE_RATE 0.2
# Power/Ground grid extraction
perform extraction -power -ground

# Static IR analysis
perform analysis -static

Reports Voltage drop


and other maps

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Recommended Directory Structure

Cell placement + power grid

Tech section and all macros used in design

For power calculation

Location of ideal pwr/gnd sources

Signal nets parasitics (optional)

Apache technology file


Instance Slew/Frequency + Clocks
(optional for static)

Run directories

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Tech File Viewer

Verify that the technology file


parameters were correctly specified

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Identification of Voltage Sources

Describes the source for the power and ground nets


- Can be specified through PAD_FILES keyword in GSR
- Can also import the pads using Import pad command
Inside the voltage source file, we can specify the sources in
different ways
- Pad instance ( *PAD section )
> <pad_cell_name_1> [<pin_name>| <pin_name> <layer_name>]
- Pad master cell ( *PCELL section)
> <master cell name>
<x source loc> <y source loc> <layer> <P/G pad type>
- Pin location list ( *PLOC section )
> <Net name> <x coord> <y coord> <layer> <POWER | GROUND>
- Pad location with package (* PLOC_PSS )
- Pad master cell used along with package (*PAD_PSS )
RedHawk will automatically identify the PINS from DEF if you
use GSR keyword 'ADD_PLOC_FROM_TOP_DEF 1 .
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Identification of Voltage Sources (Contd)

*PCELL
DVDD12
DVSS
PASLZ55 VDD
PADLZ55 VSS

*PAD
VDD_PAD1
VSS_PAD45
PVDD1DGZ
17.5 242.0 METAL6 POWER

*PLOC
DVDD1 4905 878.85 METAL4 POWER
DVSS1 4880 938.85 METAL4 GROUND
DVDD2 4905 998.85 METAL4 POWER

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STA Timing Information From Primetime

Recommended for Static analysis- provides accurate


transition times and instance frequency
Required for Dynamic provides switching windows
Uses Apaches PT TCL script to dump data from PT
Procedure:
- Load design, constraints and Link
- Set appropriate case analysis (same as normal timing sign off)

pt_shell> source pt2timing.tcl


pt_shell> getSTA *

Output STA file is <design>.timing

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STA File Usage

Power Static Analysis Dynamic Analysis


Calculation
Clock Domain
Instance Slew

Instance
Frequency
Instance
Timing
Window

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Toggle Rate

CLK

SIGNAL 1 2 3 4 5

A Toggle is 01 or 10 transition
Toggle rate=(no. of transitions)/(no. of cycles)
Toggle rate CLK=2
Toggle rate SIGNAL=0.5

GSR keyword:
TOGGLE_RATE 0.5 2

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Global System Requirement File
(aka. user controls)
Apache tech lef def/gds lib spef/dspf STA
(slew/clocks)

# GSR keywords

VDD_NETS {
VDD 1.7
VDD 1.2 # RedHawk interactive commands
inst_129973/VDD_INT 1.2 import gsr GENERIC.gsr
setup design
}

TOGGLE_RATE 0.2
DEF_FILES {
file_16.def top
}

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Setting Up The Training Testcase

cp R <original_path>/GENERIC_tutorial.tar.gz .

tar xvzf GENERIC_tutorial.tar.gz

Follow the instructions in the README to run the static run.

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Step 1: Creating GSR and Run Script

cd GENERIC_tutorial/static_run

Review the GSR and Command File

source setup.csh : This will set APACHEROOT, PATH and


LM_LICENSE_FILE.

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GSR File Overview

TECH_FILE ads.tech

LIB_FILES {
LIB_FILES {
<path to lib file>
OR <design>.libs
<path to lib directory> (all *.lib files in dir)
}
<path to custom lib file> custom
}

LEF_FILES { LEF_FILES {
<lef file path>/name1.lef << tech definition OR <design>.lefs
<lef file path>/name2.lef }
}

DEF_FILES {
<def file path>/name1.def OR DEF_FILES {
<def file path>/name2.def TOP < last one to be TOP DEF<design>.defs
} }

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GSR File Overview (Contd)

PAD_FILES {
pad file path name/name1.pad
}

GDS_CELLS {
cell_name1 <path to dir where files for cellname1
reside>
cell_name2 <path to dir where files for cellname2
reside>
}

GSC_FILE <path and name of GSC file>

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GSR File Overview (Contd)

# Net switching activity


TOGGLE_RATE <value>

# Block specific toggle information Order of toggle selection


BLOCK_TOGGLE_RATE {
<block_name> <value>
VCD_FILE
...
}
INSTANCE_TOGGLE_RATE /
INSTANCE_TOGGLE_RATE_FILE
# Obtain toggle from VCD
VCD_FILE {
BLOCK_TOGGLE_RATE /
...
BLOCK_TOGGLE_RATE_FILE
}
TOGGLE_RATE
# Instance specific toggle
INSTANCE_TOGGLE_RATE {
<name of instance> <toggle rate>
}

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GSR File Overview (Contd)

# Design timing information


STA_FILE {
FREQ_OF_MISSING_INSTANCES <value in Hz>
<name of design> <design timing data>
} From running TCL program

# Dominant frequency of design The frequency value that


FREQUENCY <value in Hz> captures most of the power in
the design
# Input transition time
INPUT_TRANSITION <value in s>

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GSR File Overview (Contd)

# Power specification
BLOCK_POWER_FOR_SCALING {
FULLCHIP <design_name/block/instance>
<total power>
Full chip or block or cell
CELLTYPE <cell name> <power> power can be specified
<block name> <instance name> <power>
}
Honour user provided
INSTANCE_POWER_FILE { instance specific power
<name of file>
}

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Static Run Command File

# Import data
import gsr GENERIC.gsr
setup design
setup analysis_mode static

# Calculate power
perform pwrcalc

# Power/Ground grid extraction


perform extraction -power ground

# Lumped resistance (in Ohms)


# for package, wirebond and pads
setup package -power -r 0.005 l 2.5 c 5
setup package -ground -r 0.005 l 2.5 c 5
setup wirebond -power -r 0.01 l 2.2 c 1.42
setup wirebond -ground -r 0.05 l 1.7 c 0.2
setup pad -power -r 0.001
setup pad -ground -r 0.001

# Static IR analysis
perform analysis -static

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Step 2: Importing the Design

Data Preparation # Import data


import gsr GENERIC.gsr
Design Import setup design
setup analysis_mode static
Power Calculation
# Calculate power
perform pwrcalc

Power Grid Extraction # Power/Ground grid extraction


perform extraction -power -ground

PG Weakness Analysis # Lumped resistance (in Ohms)


# for package, wirebond and pads
setup package -power -r 0.005 l 2.5 c 5
Package Parasitics setup package -ground -r 0.005 l 2.5 c 5
setup wirebond -power -r 0.01 l 2.2 c 1.42
setup wirebond -ground -r 0.05 l 1.7 c 0.2
setup pad -power -r 0.001
Static IR/EM Analysis setup pad -ground -r 0.001

# Static IR analysis
Result Exploration perform analysis -static

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Starting RedHawk and Setting Up
the Design

Start RedHawk
Execute commands:
import gsr GENERIC.gsr
setup design
Zoom in/out/scroll
- Drag Right mouse button (Zoom
in)
Layer dialog box
- Turn on/off Layer/Instance
- Fill/Outline

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Design Information

TCL query: print statistics


Name of top cell: GENERIC
Size of chip: 0 0 4920.62
5000.36

Number of power nets: 2


Number of ground nets: 1
Number of P/G pads: 80

Number of instances: 255197


Number of memory/ip: 7
Number of sub blocks: 0
Number of clock inst: 6060
Number of decaps: 221105

Number of nodes: 1424789


Number of resistors: 1693247

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Some GUI Features

Viewing nets one by one


Get more information on the object
Click instance/wire/via
TCL query
select add [get instofcell switch]

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Some GUI Features
Net Selection Options
Constant VDD Domain Virtual VDD_INT Domain

config viewnet name all mode off config viewnet name all mode off
config viewnet name VDD mode on config viewnet name inst_129973/VDD_INT mode on

Same can be done with View -> Nets Menu

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GUI Menu Overview

Static Analysis Steps


- Power calculation and
Extraction options
Static IR/EM analysis
options

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GUI Menu Overview (Contd)

Result viewing
options

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Layer Options
Select layer options

Layer
Selectability

Select or Deselect metal Select Mode: Fill or


layers and via Outline
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Set Color Range
Select color range options for
different Maps

This window appearance will change based on the option you are currently viewing
You can export the color configuration using export guiconf <outputFileName> command.
This file can be imported later in other RedHawk sessions using import guiconf
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Log Message Viewer

Select
Results Log Message Viewer
Click on Setup Design Tab
Error tagging on files read-in
- Red Error during import
- Orange Warnings
- Green No issues seen

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Log Message Viewer (Contd)

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Common LEF/DEF Issues

Power pins in LEF


- Both power and ground pins must be defined
- Must contain geometries
- USE POWER and USE GROUND specified?
Power pins in DEF
- Block level DEF must have logical definition
- Top level DEF need not have pins defined, unless
'ADD_PLOC_FROM_TOP_DEF 1' is set in GSR
- Example
- VDD + NET VDD + USE POWER + DIRECTION INOUT
+ LAYER MET6 + RECT ( 0 0 ) ( 100 100 ) + PLACED N ( 12340 23450
)

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Common LEF/DEF Issues (Contd)

Power/Ground nets in DEF


- Power and ground nets in SPECIAL NETS and/or NETS section must
have USE POWER and USE GROUND attributes

P/G nets must establish logical connectivity


- - VDD ( I1 VDD ) (I1/MUX1 VDD ) ( RAM1 VDD) + MET1 ....
- - VDD ( * VDD ) + MET1 ....

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PG-arc Issues

ERROR(ITG-016): Missing PG-arc definitions for cell

- To support cells with multiple Vdd and multiple Vss pins, you need to
specify the P/G arcs to define the current path between each VDD node to
the associated GND node pair.

- Example of pgarc defined in custom lib file for a cell


cell ram_mvdd {
pgarc {
VDD VSS
VDD2 VSS2
VDDL VSS
}
}

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PG-arc Issues (Contd)

Specify the custom.lib under the LIB_FILES section of the GSR


LIB_FILES {
<lib_filename> CUSTOM
...
}
If you are unsure as to which cells need to be specified in a custom library,
then run the design through setup design and look at the data in the file
adsRpt/apache.refCell.noPGArc

RedHawk detects cells with multiple ground pins that have no custom LIB
file and reports them in the report adsRpt/apache.refCell.noPGArc, along
with all power and ground pins for each cell.
Example:
#<cell_name> <vdd_pin_names> <gnd_pin_names>
<SC_ANALOG> <VDD1A VDD2A> <VSS1A VSS2A>

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Data Integrity Checks After Setup Design

Cells w/o LEF (will not hook up to


adsRpt/apache.refCell.noLefLib
power grid)

Cells w/o .lib (no power) adsRpt/apache.refCell.noLib

Cells without power tables adsRpt/apache.refCell.noPwr

Missing nets in SPEF adsRpt/apache.rc0Net

Missing instances in STA file adsRpt/apache.tw0

adsRpt/*.no* will show all data integrity check related reports

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Step 3: Power Calculation

Data Preparation # Import data


import gsr GENERIC.gsr
setup design

Design Import # Calculate power


perform pwrcalc
Power Calculation
setup analysis_mode static

# Power/Ground grid extraction


Power Grid Extraction perform extraction -power -ground

# Lumped resistance (in Ohms)


PG Weakness Analysis # for package, wirebond and pads
setup package -power -r 0.005 l 2.5 c 5
setup package -ground -r 0.005 l 2.5 c 5
Package Parasitics setup wirebond -power -r 0.01 l 2.2 c 1.42
setup wirebond -ground -r 0.05 l 1.7 c 0.2
setup pad -power -r 0.001
setup pad -ground -r 0.001
Static IR/EM Analysis
# Static IR analysis
perform analysis -static
Result Exploration
* In GUI : Static -> Power -> Calculate Power
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Power Calculation

Calculates power of cells and blocks in the design and total


power of the design
Can also import power from 3rd party tools
Power DB created has the name: adsPower
Can be imported for subsequent static and dynamic analysis
if the design netlist and parameters do not change
Important: Check for cell with missing .lib or power models
during run or in RedHawk log file
- adsRpt/apache.refCell.noLib
- adsRpt/apache.refCell.noPwr

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Power Calculation (Contd)

Examine Power Density (PD) map


and Instance Power (IPM) map
Click on instance to query the power

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Viewing Power Maps

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Other Power Related Maps

Instance Power map

Toggle Density Map

Toggle map of
instances

Clock Instance Power map

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Power Analysis Reports

Select
Results Log Message Viewer
Then select Power tab
Examine power summary

adsRpt/power_summary.rpt - Summary of power consumption


Domain
Frequency
Clock, non-clock
tcl command: report power o power.rpt
gives instance level power, frequency, toggle, location, cell name

* Same report as in Log Message Viewer

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Power Calculation Issues/Checks

Does the Total Power number make sense?

Clock network power and Clock power reasonable?


- Clock network power is power of clock tree/mesh, typically ~ 20-30%
of total
- Clock power is network power + clock pin power, typically ~ 30-40% of
total

Power per clock frequency domain reasonable?


- Determined by clock roots or Primetime STA file
- Incorrect clock roots or PT case analysis?

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Step 4: Network Extraction

Data Preparation # Import data


import gsr GENERIC.gsr
setup design

Design Import setup analysis_mode static

# Calculate power
Power Calculation perform pwrcalc

# Power/Ground grid extraction


Power Grid Extraction perform extraction -power -ground

# Lumped resistance (in Ohms)


PG Weakness Analysis # for package, wirebond and pads
setup package -power -r 0.005 l 2.5 c 5
setup package -ground -r 0.005 l 2.5 c 5
Package Parasitics setup wirebond -power -r 0.01 l 2.2 c 1.42
setup wirebond -ground -r 0.05 l 1.7 c 0.2
setup pad -power -r 0.001
setup pad -ground -r 0.001
Static IR/EM Analysis
# Static IR analysis
perform analysis -static
Result Exploration
* In GUI: Static -> Network Extraction
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Extraction

Execute:
perform extraction
-power ground

Click on Show Power Pad


button to see location of
voltage sources

Bring up View Layers Dialog


box. Choose some metals/via
layers

Click on wires/vias to query


resistance

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PG Network Extraction Issues

Is Power or Ground net connected to ideal source?


- Net VDD not driven by any pad, pcell or ploc

Any disconnected PinInst, wire or vias?


- Check adsRpt/<design>_VDD.*.unconnect
- Check adsRpt/<design>_VSS.*.unconnect
- Check adsRpt/<design>.*.unconnect

Any shorts between nets?


- Watch out for CON-109, CON-110 and CON-111 errors
- These can result from either physical shorts or from lack of logical
connectivity between DEFs and LEFs

Look for power and/or ground pins that are incorrectly placed either
wrong polarity or not placed on a wire

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PG Weakness Analysis

Data Preparation

Design Import Early analysis capability for power


grid robustness
Power Calculation PG Resistance Analysis
Missing Vias
Power Grid Extraction Analyzing Shorts
Disconnected wires / Vias
PG Weakness Analysis
Disconnected instances
Package Parasitics Perform Resistance Calculation
Can be performed as early as the
Static IR/EM Analysis
floor-plan stage
Result Exploration

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PG Resistance Maps

Weakly connected region

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Resistance Maps
VDD Resistance VSS Resistance

Asymmetry between power and ground resistance


Helps identifying weak regions

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List of PG Weakness

Text Report :
perform gridcheck o apache.gridcheck

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Missing Vias

Text Report: adsRpt/apache.missingVias

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Analyzing Shorts

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Disconnected Wires / Vias

zoom

Text Reports:
adsRpt/GENERIC_VDD.Via.unconnect
adsRpt/GENERIC_VDD.Wire.unconnect
adsRpt/GENERIC_VSS.Via.unconnect
adsRpt/GENERIC_VSS.Wire.unconnect

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Disconnected Instances

Text Reports:
adsRpt/GENERIC_VDD.PinInst.unconnect
adsRpt/GENERIC_VDD.Pin.unconnect
adsRpt/GENERIC_VSS.PinInst.unconnect
adsRpt/GENERIC_VSS.Pin.unconnect

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Explore perform res_calc command

perform res_calc
This command will calculate effective PG grid resistance from all pads
to selected instances or locations.
perform res_calc will give the absolute resistance value where as
perform gridcheck will give the normalized resistance.
perform res_calc [-instance <name>] [-inst_file <file>] [-cell <name>] [-
worst_point] [-box <llx lly urx ury>] [-gnd <name>] [-pwr <name>] [-
layer <name>] [-limit <num>] [-o <file>] [-append] [-verbose]
The default, without any option it will give the resistance report for
worst instances as indicated by quick estimation.
-instance <name>: This option will list the resistance report for the
worst nodes of the specified instance. The report will have one node
per domain.

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Explore perform res_calc command

-inst_file <file>: This option is same as the -instance option ,only


difference is that user can give a list of instance in a file and give the file
name with the option for getting resistance report for worst nodes of
each instance(s) in the specified file. The report will have one node per
domain for each instance.
-cell<name>: This option will give the resistance report of the worst
nodes of all instance(s) for the specified cell master. The report will have
one node per domain for each instance.
-worst_point: This option give the resistance report for the worst
locations in the design as indicated by quick estimation. By default, the
report will have maximum 500 nodes per domain.
-box <llx lly urx ury> : This option will give resistance report of the nodes
within the box specified. By default, the report will have maximum 500
nodes per domain.

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60
Explore perform res_calc command

-limit <num>: Using this option user can specify the maximum limit for
the resistance report. Default limit is 500.
-gnd/-pwr/-layer <name>: This option can be used to report the
resistance values for specific pwr/gnd nets or specific layers. By default,
the report will have maximum 500 nodes per domain.
-o <file>: This option will save the report to specified output file
(default:adsRpt/<design_name>.res_calc).
-append: This option will append results to the output file.
-verbose: This option will print resistance report to message window.

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61
res_calc Result

The first column shows the absolute resistance of P/G pads from the selected
points, the second and third column give the (x,y) co-ordinates of the
instance ,the fourth ,fifth and sixth columns give the Layer name ,Net name
and instance name respectively.

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Step 5: Package and Pad Constraints
# Import data
Data Preparation import gsr GENERIC.gsr
setup design

Design Import setup analysis_mode static

# Calculate power
Power Calculation perform pwrcalc

# Power/Ground grid extraction


Power Grid Extraction perform extraction -power -ground

# Lumped resistance (in Ohms)


PG Weakness Analysis # for package, wirebond and pads
setup package -power -r 0.005 l 2.5 c 5
setup package -ground -r 0.005 l 2.5 c 5
Package Parasitics setup wirebond -power -r 0.01 l 2.2 c 1.42
setup wirebond -ground -r 0.05 l 1.7 c 0.2
setup pad -power -r 0.001
Static IR/EM Analysis setup pad -ground -r 0.001

# Static IR analysis
Result Exploration perform analysis -static

GUI: Static -> Pad, Wirebond / Bump and Package Constraint


Distributed Package model in spice / S-parameter format also supported

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Static Analysis

# Import data
Data Preparation import gsr GENERIC.gsr
setup design

Design Import setup analysis_mode static

# Calculate power
Power Calculation perform pwrcalc

# Power/Ground grid extraction


Power Grid Extraction perform extraction -power -ground

# Lumped resistance (in Ohms)


# for package, wirebond and pads
PG Weakness Analysis setup package -power -r 0.005 l 2.5 c 5
setup package -ground -r 0.005 l 2.5 c 5
setup wirebond -power -r 0.01 l 2.2 c 1.42
Package Parasitics setup wirebond -ground -r 0.05 l 1.7 c 0.2
setup pad -power -r 0.001
setup pad -ground -r 0.001

Static IR/EM Analysis # Static IR analysis


perform analysis -static
Result Exploration
*GUI: Static -> Static IR-drop & EM Analysis
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Result Exploration and Debugging

Data Preparation

Design Import
Result summary
Power Calculation Log message viewer
Power Grid Extraction Result Maps
PG Weakness Analysis
EM violations

Package Parasitics
Text Results

Static IR/EM Analysis

Result Exploration

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Examine Summary of Results

Total power of cells hooked


to the network

IR drop summary

Worst EM

Text report pointers

* Log/error/warnings/command history stored under adsRpt


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Examine Summary of Results (Contd)

Summarizes variation in
current load for all switches

Can identify the in-effective


switches from this report

Switches supplying high


current also cause high
voltage drop

/adsRpt/Static/switch_static.rpt

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CPU/Memory Usage
Select Results Log Message Viewer
Then select CPU/Memory usage tab

Both Power and Ground Nets solved simultaneously

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Viewing Voltage Drop Map Wires
View > Voltage Drop Maps > Wire&Via

VDD +
VDD_INT

VSS

Use View -> Nets Menu for selecting individual nets

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Debugging Voltage Drop

VDD Hot-spot

Drop is due to inadequate number of pads at the corner and at the top

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Viewing Voltage Drop Map Instances

View > Voltage Drop Maps > Instance

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Violations Browsing

Purpose: Enables browsing of IR,EM violations


View report
- Results List of Worst IR Instances for Static Simulation
- Results List of Worst EM for Static Simulation
- Results List of Worst IR for Wire & Via for Static Simulation
- Results List of Highest Power Instances for Static Simulation

Select violation
interest

Zoom to selected
instance

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Example EM Issues

VDD

VSS
less false EM violations due to accurate
prediction of current direction

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Debugging EM Violations
GUI> zoom rect 1500 4480 1600 4500
Highlight only METAL5 and METAL6, then click on the EM map button

EM violation is caused due to narrowing


of METAL5

The EM limit for METAL6 is very high


compared to METAL5, hence there is no
violation

METAL6 METAL5

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Pad Voltage Map

Helps in analyzing distribution and number of pads !

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Static Analysis Reports

In adsRpt/Static/

GENERIC.inst.worst
GENERIC.inst Instance voltage drop
GENERIC.inst.arc
GENERIC.ir.worst
GENERIC.ir(Use tcl command: Wire voltage drop
report ir -routing o
adsRpt/Static/GENERIC.ir)
GENERIC.em.worst List of EM violations

DC current through each voltage


pad.current
source

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How to get Help!!!
Apache Online Customer Support Center
http://support.apache-da.com
Email: support@apache-da.com

06/02/10, 77 2010 Apache Design Solutions


THANK YOU !!!

06/02/10, 78 2010 Apache Design Solutions