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EFFICIENT INTEGER DCT ARCHITECTURES FOR HEVC 2014

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EfficientIntegerDCTArchitecturesforHEVC2014 Phone

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In this paper, we present area and powerefficient architectures for the

implementationofintegerdiscretecosinetransform(DCT)ofdifferentlengthsto
be used in High Efficiency Video Coding (HEVC). We show that an efficient Subject

constantmatrixmultiplicationschemecanbeusedtoderiveparallelarchitectures Re: Efficient Integer DCT Architectures for HEVC 2014

for 1D integer DCT of different lengths. We also show that the proposed
structurecouldbereusableforDCToflengths4,8,16,and32withathroughput Message

of32DCTcoefficientspercycleirrespectiveofthetransformsize.Moreover,the
proposed architecture could be pruned to reduce the complexity of implementation substantially with only a marginal affect on the
codingperformance.Weproposepowerefficientstructuresforfoldedandfullparallelimplementationsof2DDCT.Fromthesynthesis
result,itisfoundthattheproposedarchitectureinvolvesnearly14%lessareadelayproduct(ADP)and19%lessenergypersample
(EPS)comparedtothedirectimplementationofthereferencealgorithm,onaverage,forintegerDCToflengths4,8,16,and32.Also,
an additional 19% saving in ADP and 20% saving in EPS can be achieved by the proposed pruning algorithm with nearly the same
throughputrate.Theproposedarchitectureisfoundtosupportultrahighdefinition76804320at60frames/svideo,whichisoneofthe
applicationsofHEVC.

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