EE 321 Analog Electronics, Fall 2013

Homework #11 solution

4.43. For each of the circuits in Fig. P4.43, find the labeled node voltages. For
all transistors, kn W
L
= 0.4 mA/V2 , Vt = 1 V, = 0.

(a) Figure P3.43a

Since vDS = vGS + V , (V = 5 V) we are in the triode region. Insert expression for vDS
to get
" #
W (vGS Vt )2 kn W
iD = kn (vGS Vt ) (vGS Vt ) = (vGS Vt )2
L 2 2 L

which gives

s  1
W
V1 = vGS = 2iD kn Vt
L
r
10 106
= 2 1
0.4 103
= 1.22 V

(b) Figure P3.43b

Same as (a), except larger current, so we get

1
 r
2 100 106
V2 = 1
0.4 103
= 1.71 V

(c) Figure P3.43c

Same as (a), except larger current still, so we get

r
2 1 103
V3 = 1
0.4 103
= 3.24 V

(d) Figure P3.43d

In this case we are in the saturation region because vDS > vGS Vt ,

kn W
iD = (vGS Vt )2
2 L

2
 s  1
W
V4 =vGS = 2iD kn
+ Vt
L
r
2 10 106
= +1
0.4 103
=1.22 V

(e) Figure P3.43e

Same as previous case except larger current.

r
2 103
V5 =vGS = +1
0.4 103
=3.24 V

(f) Figure P3.43f

Saturation mode, so

kn W
iD = (vGS Vt )2
2 L
and

3
 V vGS
iD =
R

kn W  2
vGS + Vt2 2vGS Vt

V vGS = R
2 L

2
V vGS = AvGS + AVt2 2AvGS Vt

2
AvGS + vGS (1 2AVt ) + AVt2 V = 0

2
AvGS + BvGS + C = 0

B B 2 4AC
vGS =
2A
where

R W
A= k = 20 V1 B = 1 2AVt = 1 2 20 1 = 39
2 nL

C = AVt2 V = 20 12 5 = 15 V

so that

39 392 4 20 15
vGS =
2 20

vGS = 1.43 V or vGS = 0.53 V

Only one of these solutions is correct. We assume non-zero current and thus conducting
mode, which is only true for vGS > Vt . Therefore the correct solution is

vGS = 1.43 V

(g) Figure P3.43g

4
 This is the same problem except a different resistance. In this case we have

R W
A= kn = 0.2 V1 B = 1 2AVt = 1 2 0.2 1 = 0.6
2 L

C = AVt2 V = 0.2 12 5 = 4.8 V

B B 2 4AC
vGS =
2A

vGS = 3.62 V or vGS = 6.6 V

The first potential solution is the correct one as we assumed vGS > Vt .

(h) Figure P3.43h

In this case we have

vDS + iD RD = 2V V8 = iD R V = vGS

since vDS = vGS + V > vGS Vt , it is operating in the saturation region

kn W
iD = (vGS Vt )2
2 L

5
 Inserting the expression for iD in terms of vGS above,

V vGS
iD =
R
we get

V vGS k W
= n (vGS Vt )2
R 2 L
This is identical to the expression in problem (f) above, so the solution is the same,
vGS = 1.43 V, and

V8 = vGS = 1.43 V

4.44. For each of the circuits shown in Fig P4.44, find the labeled node voltages.
The NMOS transistors have Vt = 1 V, and kn W L
= 2 mA/V2 . Assume = 0.

(a) For Figure P4.44a

We have vDS1 = 2V V1 , and vGS1 = V V1 , where V = 5 V. Thus, transistor 1 is
operating in saturation. Also notice that V2 = iD R V . If we assume that transistor
2 is also operating in saturation then vGS1 = vGS2 . And since vGS2 = V2 , we have

kn W
vGS1 = iD R V = R (vGS1 Vt )2 V
2 L

Choose A = R k2n W
L
, we get

6
 2
vGS1 = AvGS1 + AVt2 2AvGS1 Vt V

2
AvGS1 + AVt2 2AvGS1 Vt + vGS1 V = 0

or

2
AvGS1 + BvGS + C = 0

where

kn W 1 103 1
A=R = 2 103 = 1
2 L 2 V

B = 1 2AVt = 1 2 = 1 C = AVt2 V = 4 V

B B 2 4AC 1 1+44
vGS1 = =
2A 2

vGS1 = 2.56 V or vGS1 = 1.56 V

The second cannot be a solution, because we assumed vGS1 > Vt to be conducting. In

the first case we get

V1 = V vGS1 = 5 2.56 = 2.44 V

which puts the second transistor in saturation mode, so that assumption is OK. Thus,

V2 = vGS2 = vGS1 = 2.56 V

(b) For Figure P4.44b

Both transistors are operationg in saturation, and are identical. We have

vDS1 = vDS2 = vDS = vGS1 = vGS2 = vGS

Thus,

2vGS + 2iD R = V

(V = 10 V). We also have

kn W
iD = (vGS Vt )2
2 L
7
Thus

V 2vGS k W
= iD = n (vGS Vt )2
2R 2 L

kn W
Choosing A = 2 L
, we get

V 2vGS 2
= AvGS + AVt2 2AvGS Vt
2R

2 vGS V
AvGS + AVt2 2AvGS Vt + =0
R 2R

2
AvGS + BvGS + C = 0

where

kn W A 1
A= = 1 103 2 B = 2AVt + = 1 103 1
2 L V R

V
C = AVt2 = 4 103 A
2R

B B 2 4AC 1 103 1 106 + 4 103 4 103
vGS = =
2A 2 103

vGS = 2.56 V or vGS = 1.56 V

The first solution is the correct one because we assumed vGS > Vt . In that case,

kn W
iD = (vGS Vt )2 = 1 103 (2.56 1)2 = 2.43 103 A
2 L
and

V3 =V iD R = 10 2.43 = 7.57 V
V4 =V3 vGS = 7.57 2.56 = 5.01 V
V5 =V4 vGS = 5.01 2.56 = 2.45 V

V5 should also be V5 = 0+iD R = 2.43 V, which is close to within a few rounding errors.

8
4.45. For the PMOS transistor in the circuit shown in Fig. P4.45, kp = 8 A/V2 ,
W
= 25, and |Vtp | = 1 V. For I = 100 A, find the voltages VSD and VSG for
L
VSG
R = 0, 10 k, 30 k, and 100 k. For what value of R is VSD = VSG ? VSD = ?
2
VSG
VSD = ?
10

We are being asked about both saturation and triode mode operation. Choose Vt = 1 V.
First we determine the operating mode of the device. That depends on the relative values
of VSD and VSG . When VSD < VSG Vt , or VSG VSD > Vt , then we are operating in triode
mode. Otherwise saturation mode. But VSG VSD = IR, so the cirterium is IR > Vt for
triode mode. Here is a table
R (k) 0 10 30 100
I (A) 100
Vt (V) 1
IR (V) 0 1 3 10
Mode Saturation Saturation Triode Triode
For the two saturation mode cases we have

kp W
iD = (vSG Vt )
2 L
which gives us
s r
2iD L 2 100 106
vSG = + Vt = +1 = 2V
W kp 25 8 106
And vSD = vSG IR. For R = 0 we get vSD = vSG = 2 V, whereas for R = 10 k we get
vSD = 2 100 106 10 103 = 1 V.
For the triode region we have
2
 
W vSD
iD = k (vSG Vt ) vSD
L p 2

9
In this case we can substitute VSD = VSG IR and get
" #
2
W (VSG IR)
iD = kp (VSG Vt ) (VSG IR)
L 2
2
I 2 R2 VSG IR
 
iD L 2 VSG
= VSG VSG IR VSG Vt + Vt IR +
W kp 2 2 2
2
I 2 R2
 
VSG IR iD L
+ VSG IR Vt + + Vt IR =0
2 2 2 W kp
2
I 2 R2
 
VSG IR iD L
+ VSG Vt + Vt IR =0
2 2 2 W kp
Making

1 IR I 2 R2 iD L
A= B = Vt C = Vt IR
2 2 2 W kp
We can solve the quadratic equation as

B B 2 4AC
VSG =
2A
R (k) 30 100
1 1
A 2 2
B (V) -2.5 -6
2
C (V ) -2 -40.5
VSG (V) 5.7/-0.7 11.2/-7.2
VSD (V) 2.7 1.25
Only the positive solutions are physical and those are the answer. As a final check we should
verify that these voltage do indeed correspond to triode region operation. That is the case
if VSD VSG < Vt . That is indeed the case.
Next we are asked the values of R for which there is a particular reltionshiop between
VSD and VSG . First, for the case where VSD = VSG , that can only be the case when R = 0.
Secondly, the value for which VSD = VSG 2
. We already found that is the case for R = 10 k.
Third, for vSD = v10
SG
, we must be operating in the triode mode.
2
 
W vSD
iD = k (vSG Vt ) vSD
L p 2
and inserting vSD = v10SG
(and iD = I),

2
 
W vSG vSG
I = kp (vSG Vt )
L 10 200
 2 2

W vSG vSG Vt vSG
= kp
L 10 10 200
 
W 19 2 1
= kp v vSG Vt
L 200 SG 10

10
 19 2 1 IL
vSG Vt vSG =0
200 10 W kp

19 Vt IL 100 106
A= B= = 0.1 V C= = = 0.5 V2
100 10 W kp 25 8 106

B B 2 4AC
vSG = = 2.880 or 1.827
2A
The second solution is not valid, so we continue with the first solution,

vSG vSD vSG v10

SG
9vSG 9 2.880
R= = = = = 25.92 k
I I 10I 10 100 106
4.53. The expression for the incremental voltage gain Av given in Eq (4.4) can
be written as

2 (VDD VDS )
Av =
VOV
where VDS is the bias voltage at the drain (called VOQ in the text). This expres-
sion indicates that for given values of VDD and VOV , the gain magnitude can be
increased by biasing the transistor at a lower VDS . This, however, reduces the
allowable output signal swing in the negative direction. Assuming linear opera-
tion around the bias point, show that the largest possible negative output signal
peak vo that is achievable while the transistor remains saturated is
VDS VOV
v
o =
1 + A1v
For VDD = 5 V and VOV = 0.5 V, provide a table of values for Av , v o , and the
W
corresponding v i for VDS = 1 V, 1.5 V, 2 V, and 2.5 V. If kn L = 1 mA/V2 , find
ID and RD for the design for which VDS = 1 V.
Here is an illustration of the problem in which we are to determine vo :
iD

ID
VGS

vO

vDS
VDS

11
We are looking for the point, as we travel up the straight line, where vDSSat = vGS Vt ,
which is the edge of the saturation region. Then vo = VDS vDSSat . Lets model linearly
vds
vDS = VDS + vds vGS = VGS +
Av
At the maximum excursion we can write
vo
vDSSat = VDS vo vGSSat = VGS
Av
Now we just set vDSSat = vGSSat Vt and solve for vo .
vo vo
VDS vo = VGS Vt = VOV
Av Av
VDS VOV
vo =
1 A1v
This is not the same expression as is given in the book. Nevertheless, I will continue with
this expression, and tabulate for VDD = 5 V, and VOV = 0.5 V

VDS (V) Av vo (V) vi (V)

1 16 0.47 0.029
1.5 14 0.93 0.066
2 12 1.38 0.12
2.5 10 1.82 0.18

4.54. Figure P4.54 shows a CS amplifier in which the load resistor RD has been
replaced with another NMOS transistor Q2 connected as a two-terminal device.
Note that because vDG of Q2 is zero, it will be operating in saturation at all
times, even when vI = 0 and iD2 = iD1 = 0. Noe also that the two transistors
conduct equal drain currents. Using iD1 = iD2 , show that for the range of vI
over which Q1 is operating in saturation, that is for

Vt1 vI vO + Vt1
the output voltage will be given by
s s
(W/L)1 (W/L)1
vo = VDD Vt + Vt vI
(W/L)2 (W/L)2
where we have assumed Vt1 = Vt2 = Vt . Thus the circuit functions as a lin-
ear amplifier, even for large input signals. For (W/L)1 = (50 m/0.5 m) and
(W/L)2 = (5 m/0.5 m), find the voltage gain.

12
For Q2 we have
1 W2
iD = kn (VDD vo Vt )2
2 L2
and for Q1 we have

vo2
 
W1
iD = k (vI Vt ) vo
L1 n 2
We want to find vo , so we eliminate iD between the two equations.

vo2
 
1 W2 2 W1
(VDD vo Vt ) = (vI Vt ) vo
2 L2 L1 2
This is a quadratic equation in vo . Solving it is straightforward but tedious. You will get two
solutions of which one is not physical and the other one is the one shown.
The voltage gain is the factor in front of vI , so
s s
W1 /L1 50/0.5
Av = = = 3.2
W2 /L2 5/0.5

13