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2nd Examination
November 9, 2007
A0
A1
A2
A3 AND
Vout A4
A5
A6
A7
a) For the combinational circuit above (i) annotate transistor sizes that would result in
the circuit delivering as much current as a unit sized inverter (assume the unit sized
inverters Wp:Wn ratio of 2:1) . (ii) Provide the input capacitance of input signal D
(does not differ from that of input A, B, C or E). (iii) What is the value of the
intrinsic load capacitance?
b) Find (i) the worse case rise and fall times of this combinational logic circuit. (ii) Also
find the fastest rise and fall times. (Hint: For both questions b(i) and b(ii) you can first
determine the combination of inputs that results in the critical path (worse case delay)
and shortest path (best case delay)).
c) Provide the average propagation delay of each case in (b).
d) The 8-input CMOS AND gate must be designed to provide as much current as a unit
sized inverter (Wp:Wn ratio of 2:1). (i) Determine the A0s input capacitance. (ii) The
inverter of this AND gate is 10 times the unit sized inverter, determine the
intrinsic/internal loading of this gate.
e) Calculate the best path delay D of this gate. Equations of interest are:
1
CL
D NF N P, with F GBH , G g i , B bi , H , P pi N is the
C g1
number of stages.
f) It is impractical to design a gate with more than for devices in series. Please design an
equivalent 8-input AND gate that eliminates the long chain of series devices. (This
could use any logic style of your choice i.e. transmission gate, pass transistor logic,
pseudo-nMOS etc).
g) Provide the propagation delay of your proposed gate.
h) The delays of questions 1(d) through (g) have no units. What information would we
need to get the units of seconds?
Problem 2: Inverter Stages [40 points]
4
Initial Driver
400
VDD
Vin
Vout
CL