COMSATS Institute of Information Technology

Kamra Road, Attock

Department of Electrical Engineering

Course Title: Digital System Design

Course Code: EEE-344

Class: BEE-VI

Course Instructor: Mr. Wasiq Ali

Lab Instructor: Engr. Shahzad

LAB #05: Multiplier

(Gate Level and Data Flow Models)
Group Members:

Sr.No. Name Registration No.

1 Maaz Ahmad CIIT/FA14-BEE-003/ATK

2 Talha Nadeem CIIT/FA14-BEE-007/ATK

Objective: Implementation of two bit multiplier on FPGA Spartan 6 board.
Multiplier:
A logic circuit that multiplies two or more inputs and yields results. Output is always
summation of bits of inputs like if one input is 3 bit and second is 4 bit, overall result will
consists of 7 bits.

Procedure:
First of all, open Xilinx ISE and make new project.
Select device XC6SLX16 and add Verilog module file.
Write code to implement two bit multiplier and run it.
Make RTL file and save it.
Create Verilog fixture file and add all the input schemes with 100ns delay.
Observe wave diagram and verify your theoretical results and save it.
Open user constraints and assign I/Os to have result for two bit multiplier and save
it.
Re-run the code and generate bit file.
Connect the hardware and open configure target device.
First auto-connect the cable in the window of iMPACT software and then add your
Xilinx device.
Program it and test your results practically and match it with wave diagrams
results.
Repeat this experiment for two bit multiplier using data flow modeling.

Conclusion:
In this experiment we learnt about the syntax of multiplier and observed the behavior
of comparator practically on Spartan 6 FPGA kit.
Task1: Two Bit Multiplier (Gate Level) RTL Image:

Code:
module Two_Multiplier_Module(
input[1:0] a,b,
output [3:0] mul);
wire y;
assign mul[0]= a[0] & b[0];
assign
{y,mul[1]}=((a[0]&b[1])+(a[1]&b[0]));
assign {mul[3],mul[2]}=(y+(a[1]&b[1]));
endmodule

Verilog input and Waveorm Output

a b mul
01 01 0001
10 10 0100
00 00 0000
11 11 1001

Wave Diagram:
Task2: Two Bit Multiplier (Data Flow) RTL Image:

Code:
module TWO_MUL_Module(input
[1:0] a,b, output [3:0] mul);
assign mul=a*b;
endmodule

Verilog input and Waveorm Output

a b mul
01 01 0001
10 10 0100
00 00 0000
11 11 1001