Performance Evaluation of 8-Channel ADC
ATCA Card for Direct Sampling of 1.3 GHz
Samer Bou Habib
AbstractNowadays LLRF control systems for linear accel-
erators incorporate complex and expensive high-precision field
detection receivers with multichannel down-converters and low
noise LO generation systems. Increasing requirements for field
detection precision at most advanced machines reveal limitations
of classical LLRF system receivers. Recently developed technol-
ogy made it possible to design data acquisition cards allowing
for direct sampling of cavity field without a need for down-
converters. This paper describes the design and measurements
of an eight-channel ATCA card developed for the evaluation of
direct sampling techniques for 1.3 GHz signals at the FLASH
and European XFEL accelerators. Two versions of the board
were tested, each holding a different set of analog-to-digital
converters. One was equipped with 400 MSPS, 14-bit ADCs
with an analog bandwidth of 1.4 GHz while the other held
500 MSPS, 12-bit ADCs with a bandwidth of 2.3 GHz. The
boards were tested in the laboratory and with "accelerator-
like" signals and revealed very good results. The paper shows
results of the measured sampling parameters, as well as results of
different non-IQ sampling schemes with various bandwidths and
reaction times for acquiring the amplitude and phase of the
analyzed signals and determining the precision of the analysis.
Drift measurements for determining the long-term stability are
also presented. Achieved results satisfy precision requirements
for machines like The European XFEL main LINAC and ILC
accelerators.
Index TermsLLRF, direct sampling, field detection, fast
ADC, ATCA
I. I NTRODUCTION
The modern superconducting linear accelerators such as the
FLASH[1] and XFEL[2] at the DESY facility in Hamburg
provide very high performance electron beams for various
users and experiments. In order to acquire best performance
parameters of the electron beam, very high requirements
are imposed on the beam and RF field stability and as a
consequence on the control and synchronization systems of
these accelerators. The main requirements are the stability
of up to 0.01 degree in phase and 0.02% in amplitude [3].
The system responsible for ensuring such precision is the
Low Level Radio-Frequency system (LLRF) [4]. It is based
mainly on the precision of the RF field measurements of the
1.3 GHz signals at which the superconducting cavities work.
The current methodology is based on the process of down-
conversion i.e. to convert the high frequency signals to a lower,
Intermediate Frequency (IF) which is then sampled by analog-
to-digital converters using a specialized clock signal frequency
[5]. The sampled data is then used for implementing various
S. Bou Habib is with the Insitute of Electronic Systems, Warsaw University
of Technology, Warsaw, Poland (email: S.BouHabib@elka.pw.edu.pl)
algorithms and digital processing for different feed-backs and
feed-forwards to maintain the required stability. Other sub-
systems of the whole accelerator control including Klystrom-
Lifetime Management (KLM) [6] , High-Order Modes mea-
surements [7] and other systems also use the methodology of
down-conversion to acquire information about high frequency
signals.
Recent technology has allowed the possibility of using new
very high speed (>400 MSPS) and bandwidth (>1.3 GHz)
ADCs for direct-sampling of the RF signals without the use
of down-converters with a high resolution (> 12bits). Systems
based on such an approach carry many advantages compared to
the older methodology in terms of size, cost, system delay and
complexity i.e. no complex high-performance LO generation
is required and the smaller faster system contains much less
sensitive analog RF circuits. It was demonstrated that such
very fast ADCs can be implemented in the control and syn-
chronization systems for direct acquisition of RF signals[8].
In the LLRF and other control systems of the XFEL accel-
erator [9] more than a 100 RF channels have to be sampled
in each station for controlling 32 superconducting cavities in
4 cryomodules. This requires a very flexible, scalable and
redundant standard. It was decided to use the xTCA [10]
format in the accelerator for fulfilling these requirements.
Simultaneously, development of a multichannel RF receiver
was launched to test the feasibility of direct-sampling. The test
board was designed as an eight-channel ATCA card for inves-
tigation of the new approach performance and parameters[11].
II. U NDERSAMPLING AS A S IGNAL P ROCESSING
T ECHNIQUE
Although the used ultra-fast ADCs sample with very high
speeds, the frequency of the sampled RF analog signals
exceeds several times the samples-per-second rate. Thus, in
order to measure signals in bandwidths from higher Nyquist
bands, undersampling[12] is used as the technique allowing
the derivation of amplitude, phase and even shape of the input
signals. The technique shows the sampled signals in a shifted
position in the frequency domain i.e. in the first Nyquist band,
but preserving all required parameters.
Moreover, for precise and efficient amplitude and phase
measurement as well as synchronization with input RF signals,
the non-IQ sampling scheme was used [13] .The precise clock
values can be determined by the formula below
f0
fs = , k = 0, 1, 2, ... (1)
k+ mn

Figure 1. Shifting of spectrum using undersampling
where f0 represents the RF frequency, and m and n the
phase difference between two adjacent samples as given by
the formula
m FPGA, Memory and Interfaces
= 2 (2)
n
The methodology allows flexibility in the choice of the sam-
pling frequency, which has significant effect on the quality of
the measurement parameters. Various schemes were tested and
the results will be shown in this paper.
III. S YSTEM C ONCEPT AND D ESIGN
The project involved mainly the design of an eight channel
ATCA board for testing two different very high-speed ADCs.
Such a receiver would be sufficient for direct-sampling tests
involving data processing from eight cavities, i.e. one cry-
omodule in the linear accelerators. The board can be upgraded
with various mezzanine cards for additional data processing
and different ADC front-ends. It was foreseen that the receiver
can be used as a stand-alone system with no need for the
ATCA crate. The main system conception is illustrated in
figure 2.
Eight 1.3 GHz signals from the cavities are fed though
matching circuits to the eight high-speed ADCs. To ensure
proper processing, the converters are synchronized with re-
spect to one another and the input signals. This is done
using a 1.3GHz RF signal from the accelerator Master Os-
cillator unit as a reference for the on-board PLL for syn-
thesis and distribution of very low jitter clock signals to
the converters. The sampled data from all ADCs is then
received simultaneously by a powerful FPGA where detection
algorithms are implemented to derive the required amplitude
and phase information. Moreover, the FPGA is used as the
board controller, i.e. to configure all peripheral devices and
manage communication with external devices. A processor
daughter board can be added for very high processing power
and additional communication with the ATCA-LLRF system.
Additionally, the board holds diagnostic circuits for monitoring
the board operation and temperature. Data acquisition can be
implemented in the available SRAM memory blocks. One of
the assembled boards is shown on figure 3.
The main circuits on the board are:
Fast ADC Circuits
The board allows testing two pin-compatible high
speed ADCs, a 12-bit 500 MSPS version with 2.3
GHz of analog bandwidth and a 14-bit 400 MSPS
chip with 1.4 GHz bandwidth. In order to achieve
maximum performance the RF input signals are dif-
ferentiated and carefully matched to the input of the
ADC. Additional mezzanines can be used to bypass
the input circuits, in order to provide additional gain,
filtration, DC-coupling or matching at different input
frequencies.
Timing and synchronization
A very low noise PLL synthesizer is used for gener-
ation of synchronous clocking signals for the ADCs
with sub 200fs jitter.1 The PLL has a sufficient
amount of internal frequency dividers to obtain vari-
ous frequencies used for different sampling schemes.
Powerful XilinX Virtex5 SXT/LXT FPGA devices
are mounted on the boards respectively. Both devices
can handle the very big amount of date from the
eight ADCs simultaneously in addition to all config-
uration, control, data acquisition and communication
with both peripheral and external devices. The SXT
version used on one of the boards is characterized
with additional DSP power and on-chip memory for
more complicated data processing.
Diagnostics
The main means of diagnostics on the board are
device motoring of the power supply and PLL units
and a temperature sensor for safety of operation and
monitoring changes with respect to temperature.
Figure 3. Fast ADC ATCA Printed Circuit Board
IV. T ESTS AND M EASUREMENTS
In order to ensure highest performance and feasibility for
the high energy machines, all the measurements were made
1 Measured in a very wide bandwidth of 10Hz to 1 MHz
 Figure 2. System general conception

in the DESY laboratories using very sophisticated hardware. raw format in the FPGA of the currently tested board. The
Reference, clock and RF input signals we provided by modules test setup was connected to a PC where data was transferred
used in the actual accelerator systems or ones almost identical. for data processing and precise analysis using Matlab software.
The signals were generated by a FLASH Master Oscillator unit Four major types of measurements were performed:
or a tunable synthesizer, both which provide ultra-low phase Standard ADC sampling parameters;
noise and drifts. This method guarantees the same parameters amplitude and phase detection;
of the designed circuits when used in the accelerator facility channel cross-talk;
and allows the proper characterization of the designed hard- phase drifts.
ware eliminating most inaccuracies coming from the external Description of the measurements as well as results and analysis
signals. One of the measurement setups is shown in figure 4. is described in the following parts.
A. ADC Sampling Parameters
The ADC sampling measurements were performed using
signal processing algorithms applied to the acquisited raw data.
The measurements were performed to evaluate the parameters
of the ADCs, i.e.:
Signal-to-Noise ratio (SNR) or more precisely the Signal-
to-Noise and Distortion ratio (SINAD);
ENOB resulting from the measured SINAD;
SNR/SINAD in a limited bandwidth;
clock jitter calculated from SNR.
Some of the obtained results for the 12-bit ADC board are
shown in table I.
sampling ENOB
SNR for
fre- SNR / clk jitter for
ENOB 1MHz
quency SINAD [fs] 1MHz
BW
[MHz] BW
416 4.41E+01 7.65E-13 7.03E+00 6.73E+01 1.09E+01
455 4.43E+01 7.44E-13 7.07E+00 6.79E+01 1.10E+01
487.5 4.78E+01 4.97E-13 7.65E+00 7.17E+01 1.16E+01
500 4.76E+01 5.08E-13 7.62E+00 7.16E+01 1.16E+01
365.625 5.01E+01 3.84E-13 8.02E+00 7.27E+01 1.18E+01
365.625 5.28E+01 2.79E-13 8.48E+00 7.55E+01 1.22E+01
365.625 5.30E+01 2.74E-13 8.51E+00 7.56E+01 1.23E+01
Table I
PARAMETERS FOR ADC

Figure 4. Laboratory measurement setup

An FFT of the gathered samples for the 12-bit ADC board
Each measurement involved saving all sampled data in a is shown in figure 5.
 Fs m/n 10MHz BW 1MHz BW 100KHz BW

phase [degrees rms]

phase [degrees rms]

phase [degrees rms]

amp. [rms]

amp. [rms]

amp. [rms]
[MHz]

6.26E- 6.94E- 2.27E- 3.03E- 7.01E- 1.72E-

416 1/8
04 02 04 02 05 02
6.58E- 6.40E- 1.87E- 2.37E- 6.49E- 1.05E-
455 6/7
04 02 04 02 05 02
3.65E- 4.78E- 1.14E- 2.08E- 3.85E- 9.61E-
487.5 2/3
04 02 04 02 05 03
6.15E- 7.61E- 1.93E- 3.26E- 6.71E- 1.70E-
500 3/5
04 02 04 02 05 02
2.86E- 9.60E- 1.06E- 6.89E- 4.56E- 3.44E-
365.625 5/9
04 02 04 02 05 02
Table II
P HASE AND AMPLITUDE STABILITY ( PRECISION )
Figure 5. FFT from 32K samples for a channel of the 12-bit ADC board
working at 487.5MSPS

demodulation sampling scheme are shown in figure 7 and

An FFT of the gathered samples for the 12-bit ADC board figure 8.
is shown in figure 6.

Figure 7. Amplitude precision from demodulation (0.0114% [rms], 1MHz

Figure 6. FFT from 64K samples for a channel of the 14-bit ADC board
working at 365.625MSPS
B. Amplitude and Phase Detection
The precision of amplitude and phase measurements is the
most important parameter to be evaluated. Thus, a series of
experiments was conducted using various clock signals for
testing different sampling schemes effects on the precision
of the measurements as well as different loop bandwidths2 .
Some of the obtained results are shown in table II. The values
in the table refer to the precision of amplitude and phase
detection.
The amplitude and phase precision of the 12-bit ADC
working at a frequency of 487.5 MHz in the 2/3 non-IQ
2 The loop bandwidth is proportional to the time of sampling i.e. the amount
of sampled used for demodulation and calculation of the I and Q values and
from them the amplitude and phase.
BW)
The amplitude and phase precision of the 14-bit ADC
working at a frequency of 365.625 MHz in the 5/9 non-IQ
demodulation sampling scheme are shown in figure 7 and
figure 8.
The precision obtained from the different demodulation
schemes show very good and promising results. The measured
parameters prove this technique is fit for various applications
in the accelerator control systems.
C. Channel Cross-talk
For very high precision measurement and signal analysis,
it is necessary to minimize cross-talk between channels since
even small values of transferred power would alter the mea-
surement. Thus, in this case some measurements were made
between various channels in order to find the worst case. This
case was fount to be 76 dB from the first to the second channel.
Figure 8. Phase precision from demodulation (0.0208 [rms], 1MHz BW)
Figure 9. Amplitude precision from demodulation (0.0106% [rms], 1MHz
BW)
D. Phase Drifts with Temperature
Many of the accelerator control subsystems, are very sen-
sitive to drifts of the measured signals phase. For this reason,
measurement of the drifts between two channels with respect
to temperature and time were conducted. The first measure-
ment was done without any temperature control while the other
was put in a temperature stabilized environment.
1) No Temperature Control: The temperature drifts, of both
amplitude and phase, were done inside a closed laboratory,
with only ATCA crate fans. The experiment was interfered by
an accidental change in temperature for around 200 minutes
which can be seen in figure 11 and 12.
It can be observed that both amplitude and phase drifts are
very small without temperature change, while when the tem-
perature varied a much more significant change is observed.
Moreover, the phase drifts tend to be much bigger and more
significant than the amplitude ones.
Figure 10. Phase precision from demodulation (0.0689 [rms], 1MHz BW)
Figure 11. Amplitude difference change w.r.t. temperature and time (no
stabilization)
2) Temperature Control: In order to verify and characterize
more precisely the effect of temperature on amplitude and
phase drifts, another experiment was conducted with temper-
ature control of the whole setup. The signal sources ( input
and clock references) were put in a stabilized thermal chamber
without any temperature change. The ATCA board was placed
in a similar chamber with a predefined temperature-change
profile. The profile consisted of five intervals. The first, third3
and fifth consisted of a stable temperature, while the second
and fourth of a slow rise and fall respectively. This can be
seen in figure 13 and figure 14.
It was observed again that the phase drifts with temperature
are much more significant that the amplitude drifts. The values
are 0.8 degrees per degree Kelvin versus 0,0125 relative
amplitude per degree Kelvin. It was later derived that the
greater value of the phase drifts comes from the analog front-
end and for drift-sensitive applications the analog circuits have
to be replaced.
3 The third interval can be seen to have unstable temperature variations, yet
these are a result of the temperature readout and not the actual temperature
in the chamber

Figure 12. Phase difference change w.r.t. temperature and time (no stabi-
lization) at 1.3GHz
Figure 13. Amplitude difference change w.r.t. temperature and time (with
temperature control)
Yet in both cases, it can be observed that in a stable
temperature environment, both amplitude and phase drifts
are extremely low, thus leading to the deduction that along
with temperature stabilization, the drifts can be eliminated
efficiently.
V. S UMMARY
The concept, design and measurements of the eight channel
ATCA receiver is described in the paper. The board holds
modern very fast ADCs used for direct sampling of RF signals
as a test-bench for fast ADC applications in the DESY linear
accelerators control systems. The measurements proved the
feasibility of the technique. The obtained results from the
extensive studies prove that the parameters are sufficient for
many control systems such as the XFEL main LINAC and the
ILC LLRF units as well as different fast systems involving
characterization of high frequency signals, where precision
of RF detection is obligatory along with very short system
reaction times.
The successful tests have led to many projects involving
this technique among the many control subsystems of the
accelerators. Thus, a new design using the mTCA.4 standard
is launched for the required applications.
ACKNOWLEDGMENT
Research supported by FP7 EuCARD http://cern.ch/eucard
Figure 14. Phase difference change w.r.t. temperature and time (with
temperature control) at 1.3GHz
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