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Description of operation 6
Contents:
SWT3000
PU3f
FOM
SSI FO
VF CLE
LIA VF
IFC-1
DLE
IFC-2 LID-1 X.21/G703.1/G703.6
LID-2 X.21/G703.1/G703.6
ALRS
SV-1
SV-2
The PU3 module can be expanded optionally by a submodule DLE for digital transmission paths
accommodating two digital line interfaces LID-1 and LID-2. These are used for transmitting the pro-
tection commands over a digital network (SDH/PDH). The LID can be connected also via a FOM
module and a FOBox to a multiplexer system.
If the PU3 and the IFC modules are integrated in the PowerLink unit the frequencies are for-
warded to the CSP module via the SSI.
PowerLink
CSP
Service PC
iSWT3000
PU3f
SSI
LIA
IFC-1 LAN
LID-1 X.21/G703.1/G703.6
IFC-2 DLE
LID-2 X.21/G703.1/G703.6
PS
Option
Figure 2: Block diagram of the SWT 3000 unit integrated in the PowerLink.
At the receive end the incoming commands are received in the VF range resp. digital depending
on the operating mode, converted into binary protection commands and forwarded to the IFC-D/P
module for command output.
Apart from coding and decoding of protection commands the PU3f also performs various moni-
toring functions. For example, the receive and transmit levels are fed via measuring points to the
PU3f where they are compared with the permissible values. If these levels are not reached the
PU3f activates an alarm. In the normal situation, i.e. if there is no protection command to be trans-
mitted the guard signal is sent to the distant station.
Loss of a wanted signal (command or guard tone) triggers an alarm at the receive end and
causes the relay outputs of the device to block. This alarm state can only be cancelled by receiving
the guard signal again.
When the unit is started a self-test is carried out. A watchdog also monitors the functionability of
the internal digital signal processor (DSP). In the event of malfunctions the transmitter output and
the relay outputs of the unit are blocked. An overview of the functional units of the PU3f is shown in
the following diagram.
PU3f SSI
LIA CSP
PU3 D FOM
ISV DSP
VF
A CLE
IFC-D/P
Controller
ALRS
CSP
LID-1 X.21/G703.1/G703.6
DLE
X.21/G703.1/G703.6
LID-2
optional
The internal power supply generates the voltages needed on the module that are not fed exter-
nally:
z Power supply voltages for the analog line interface
z Switched 12 V supply voltage for the relays on the IFC modules.
The 12 V operating voltage for the IFC modules can be switched from the controller and allows
selective disabling of the output relays. The operating voltages on the module are monitored. Loss
of a voltage generates a reset and alarm on the module.
Controller
The controller is the central element of the PU3. It directs communication with the analog line in-
terface, the digital line unit, the service interface for the service PC, the LAN or the alarm interface.
Equipment variants and user data can be loaded via the service interface or via the LAN interface.
The possible equipment variants for the DSP are administered by the SysWin service program.
The controller carries out the entire administration of memory space. The following memory chips
are available:
z EEPROM for user data
z SRAM for event memory and working memory
z FPROM for program memory
The controller also implements the data exchange in the transmit and receive direction with the in-
terface module IFC-D/P and IFC-S. Data from the IFC module is fed via an input buffer into a regis-
ter where it is read by the controller per interrupt. Data relating to the IFC module is also written by
the controller into this register per interrupt and reaches the IFC module via an output buffer.
If an error is detected in the SWT 3000 a message to this effect is output via an interface to the
alarm module ALRS. The ALRS is, however, only present in the stand-alone version of the
SWT 3000 unit. If the PU3f is in the PowerLink the alarms are forwarded to the CSP and the alarm
is output on the ALRS module of the PowerLink.
The LIA sets up to the connection of the module to the analog protection command transmission
and consists of a digital signal processor (DSP), operational amplifiers and analog switches.
The DSP generates the necessary command frequencies and communicates with the transmis-
sion interfaces. Depending on the equipment variant these are the interfaces to the IF and RF
modules, or to the copper line equipment CLE.
The command frequencies in the VF or IF1 range are also generated by the DSP accordingly.
Analog switches are used for switching over between VF and IF signal path. The switchover proc-
ess is controlled by the PU3 controller. All necessary information is loaded with the equipment vari-
ant via the service program and written into the DSP by the controller via an interface. During op-
eration this interface is used to transmit protection commands and parameters. The controller can
read and write DSP memory cells, and can also transfer commands and trigger various interrupts.
The controller triggers an interrupt in the DSP for the transmission of outgoing protection com-
mands. For the receiving of incoming protection commands the DSP triggers an interrupt in the
controller. The controller continuously monitors the functionability of the DSP by means of a watch-
dog function.
Self-test
The self-test functions are executed in the "self-test" phase after every program restart. In the
event of a fault it enables the fault to be reliably pinpointed at module level. The following tests are
performed in the self-test:
Checking the program and data memory of controller and DSP for functionability
Checking of configuration and parameter data for plausibility
Checking the interface(s) and communication between controller and DSP
Checking the controller-IFC module interface
Checking the interfaces to the CLE (as far as possible)
If a fault is detected in the self-test phase all inputs and outputs of the interface modules are dis-
connected and the corresponding alarms activated (LED, relays). The internal alarm trace can be
interrogated with the service program via the service interface.
Control and display elements are mounted on the module. Some are covered by the front panel:
SIEMENS >
SNR Tx
Rx
PU3 Module
Figure 4: Front panel of a unit with analog line interface CLE and FOM module
z The On/Off switch for the power supply is covered by the front panel in order to pre-
vent the unit being accidentally disconnected.
z The PU3 controller and hence the entire SWT 3000 unit is reset with the Reset but-
ton which is also covered.
z The 2-color LED LIA is needed for displaying the status of the analog line interface
LIA. The following states can be displayed:
z The 2-color LED LID-1 is used for displaying the status of the digital line interface
LID-1. The following states can be displayed:
z The 2-color LED LID-2 is used for displaying the status of the digital line interface
LID-2. The following states can be displayed:
Service interface
An RS232 service interface in the form of a 9-pole Sub-D socket is fitted at the PU3 for connect-
ing a service PC. The pin assignment is shown in the following drawing.
PU Schnittstelle COMx
PC
Verbindungskabel
Frontplatte
(9-pol.) (9-pol.)
RD (2) (2) RD
TD (3) (3) TD
SG (5) (5) SG
DCD (1) (1) DCD
DTR (4) (4) DTR
DSR (6) (6) DSR
RTS (7) (7) RTS
CTS (8) (8) CTS
The service interface is operated as a user interface with the "stand-alone" SWT 3000 unit and as
an internal interface to the CSP when the SWT 3000 is used in the PowerLink system (iSWT). The
selection is made through the device configuration.
The service interface is fed optionally to the Sub-D jack on the front panel or on the backplane.
A Busy detection circuit automatically switches over to the front panel interface if a PC is con-
nected there.
In this operating mode the service interface is connected to the controller of the CSP module
(central signal processing) of the PowerLink unit via the LAN (local area network). The user service
interface is located on the CSP from where the parameters of the PU3f module are also set. The
plug on the front panel of the PU3f is not used and is covered.
The function of interference level evaluation is to record the level of interference signals applied
for a long time and superimposed on the wanted signal. The interference level alarm (SNALR) is
signaled if a fixed level threshold is exceeded. In the "Switching functions" mode the interference
level evaluation is only activated if a single tone is transmitted (guard or command tone). If the
SWT unit is integrated in the ESB 2000i the signals SWT-SNALR and ESB-SNALR are linked in
the central control module ZST.
Protection commands and alarms are provided with time and date and a registration number be-
fore they are entered in the event memory. They are read out by the service PC and this is also
possible from the distant station by means of remote maintenance. The following events are en-
tered:
Incoming protection commands from IFC-D/P,
Outgoing protection commands to the IFC-D/P,
Detected alarms,
Program restart.
Changing date and/or time
Changing the configuration
In case of an overflow the oldest entry in the event memory is overwritten. For more information
about the event memory refer to the service program description in chapter 3!
Clock synchronisation
The system-internal clock can be synchronized by an external clock. The clock synchronisation
input (USYNC) on the module ALRS (terminal a1/c3) is provided for this. The operating point of the
input voltage can be set between 15V (strap x3 (1-2)) and approx. 54V (strap X3 (2-3)) (see also
connection of the ALRS module).
The setting options for the local sync are described in the table below.
Table 5: Setting options for the local clock synchronisation of the iSWT
Adjustment local sync Remarks
USYNC signal (minute or hour) An external impulse is received via the USYNC input every min-
ute resp. hour. The active signal slope rising or falling is syn-
chronising the RTC seconds.
IRIG-B00x (sync only) The IRIG-B message is received via the USYNC input and de-
coded. With each change of the IRIG-B minutes the RTC sec-
onds are synchronised
IRIG-B000 (RTC time adj.) The IRIG-B message is received via the USYNC input and de-
coded. With each change of the IRIG-B minutes the RTC sec-
onds are synchronised. Additional the IRIG-B-time (hour, min-
utes, seconds) is compared with the RTC time of the iSWT. In
case of a difference the IRIG-B values are taken over into the
RTC.
IRIG-B004 (RTC(time&date adj.) The IRIG-B message is received via the USYNC input and de-
coded. With each change of the IRIG-B minutes the RTC sec-
onds are synchronised. Additional the IRIG-B-time & date is
compared with the RTC time & date of the iSWT. In case of a
difference the IRIG-B values are taken over into the RTC.
NTP-Sync Synchronisation of the RTC with the network time protocol. This
function requires additional a SNMP Server V1.32 or higher
In the configuration form for the clock synchronisation additional a non urgent alarm (NUALR) can
be activated in case of USYNC failure (see figure below).
It is also possible to synchronize the clock through one of the devices via the connecting route
(line sync. mode <off>, <Master>, <Slave>). The device that is to perform the synchronization is
designated as the master and the device to be synchronized as the slave d. This means that it
is only necessary to synchronize one device (the master) externally c.
The line synchronization is performed once a day at 24:00 resp. at the time defined with <Line
sync. hour> (available from PowerSys versions P3.2.216). by transmitting the synchronizing tone
(fs). The difference in time between master and slave must not be greater than 30 sec otherwise
clock synchronization is not possible. The maximum difference in the time between master and
slave is thus the signal run time.
Select <Line synch.> <off> for both devices if both devices are provided with external synchroniz-
ing pulses e. In this case synchronization between the devices is not implemented.
c d
ext. sync
fs 18:00
A A
L L
(i)SWT 3000 (i)SWT 3000
R R
S S
A A
L L
(i)SWT 3000 (i)SWT 3000
R R
S S
Transmission concept
On the DLE a data stream is generated at the transmit end from the protection commands, RM,
SC and the internal control information that is sent cyclically in 4 message types. There are split up
again at the receive end into protection commands, RM SC and control information.
The messages have the following priority among one another:
Type 3 Command information = Prio 1
Type 2 Service channel (SC)
Type 1 Remote maintenance (RM)
Type 0 Internal control information
Messages have a constant length of 40 bits and are composed as follows:
Table 6: Message structure for the digital line interfaces
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5
Frame alignment Type code 0 User data User data User data
signal
Frame alignment Type code 1 RM data RM data RM data
signal
Frame alignment Type code 2 SC data SC data SC data
signal
Frame alignment Type code 3 Device address Command informa- Check sum
signal tion
The X.21 interface is structured according to the RS422 standard (ITU-T V.11) and consists of the
data lines TxD and RxD and the clock lines TxC and RxC.
DTE DTE
TxD (A) RxD (A)
The high transmission reliability of the interface is achieved by evaluating the differential voltage
between a twisted wire pair in each case. The electrical levels of the data lines are defined with
0.3 V to -6 V for logic 1 and with +0.3 V to +6 V for logic 0. The signal state is identified by the
voltage between the measuring points (A) and (B).
Terminations of 100 ohms at the receiver inputs not only prevent reflections on the transmission
line, but also contribute to transmission reliability through the resulting pronounced current.
Characteristics:
Number of signal lines: 8 (for each balanced pair for data and clock pulse, for transmit and re-
ceive direction in each case)
Levels: max. voltage of each line to GND (absolute) < 6V, differential voltage be-
tween the lines >2V
Line run: twisted in pairs and shielded, joint shield for all 4 line pairs
Bit rate: 64 kbit/s
Coding in accordance with G703.1 permits simultaneous transmission of the data of a 64kHz and
an 8kHz clock pulse and is carried out according to the following scheme:
1. Division of a 64kbit period into four identical intervals.
2. A binary "1" is coded as a block of four 1100.
3. A binary "0" is coded as a block of four 1010.
4. The binary signal is converted into an AMI-coded signal, with alternating polarity of
consecutive blocks of four. AMI is the abbreviation for Alternate Mark Inversion. The
code is generated from the NRZ code by representing the code elements of the logic
"1" state alternately through pulses with positive or negative voltage.
5. The change of polarity of every eighth block is suppressed for marking the octet
(8kHz clock).
The nominal data rate is 64 kbit/s. The bit rate on the line is 256 kbit/s due to the conversion of
the bits into a block of four.
Characteristics:
Number of signal lines: 4 (one balanced pair for transmit and receive direction)
Level, transmitter end: "Space" 0V+/- 0,1V, "Mark" 1V
Level, receiver end: 0...3dB
Impedance: 120 Ohm
Bit rate: 64 kbit/s (gross bit rate=4*64kBi/s=256kBit/s)
Coding: AMI
Coding in accordance with G.703.6 is also known as HDB3-code (High Density Bipolar of or-
der 3). Longer sequences of zeros, such as can occur with the AMI code are avoided here. If there
are four consecutive binary zeros the fourth character is changed by infringement of the AMI cod-
ing regulation. This means that a maximum of three consecutive binary values of "0" can occur with
the HDB3 code. The polarity of the changed code elements alternates. The HDB3 code is one of
the voltage-free codes.
Characteristics:
a) Balanced line
Number of signal lines: 4 (one balanced pair each for transmit and receive direction)
Level, transmitter end: "Space" 0V+/- 0,1V, "Mark" 1V
Level, receiver end: Loss at 1.024kHz 0...6dB
Impedance: 120 ohm
b) Unbalanced line
Number of signal lines: 4 (one unbalanced line each for transmit and receive direction)
Level, transmitter end: "Space" 0V+/- 0.237V, "Mark" 2.37V
Level, receiver end: Loss at 1.024kHz 0...6dB
Impedance: 75 ohm
Line lengths: short = indoor, long = outdoor
Bit rate: 2Mbit/s
Coding: HDB3
Jumper settings
All necessary jumper settings are shown in the chapter 2 Installation and commissioning. They
are also available in the SWTStraps program which is automatically installed with the PowerSys
service program.
Index:
IFC-D 3
IFC-P 3
A Interference level evaluation 10
iSWT settings
Alarm module 6 clock synchronisation 10
AMI 15 clock synchronisation IRIG-B 11
C L
CLE 3, 6 LED 8
Controller 6 LIA 8
LID-1 8
LID-2 8
D
OK/BGAL 8
LIA 6
Display elements 7
LID 3
DLE 3, 13
Line interface G703.1 15
DSP 6
Line interface G703.6 16
Line interface X.21 14
E line synchronization 12
Event memory 10
M
F Memory chips 6
Monitoring functions 4
Functional units 5
Functions 3
P
Receive end 4
Transmit end 3
PU3 6
G
R
Guard signal 4
Real-time clock 10
H
S
Hardware interfaces 13
Self-test 7
HDB3 16
Service interface 9
Signal processor 6
I
IF1 6
Appendix:
List of figures
Figure 1: Block diagram of the SWT 3000 unit ------------------------------------------------------------------------------- 3
Figure 2: Block diagram of the SWT 3000 unit integrated in the PowerLink. -------------------------------------------- 4
Figure 3: Functional units of the PU3 module -------------------------------------------------------------------------------- 5
Figure 4: Front panel of a unit with analog line interface CLE and FOM module -------------------------------------- 7
Figure 5: in assignment of the RS232 service interface ---------------------------------------------------------------------- 9
Figure 6: Options for the SWT 3000 clock synchronisation ----------------------------------------------------------------10
Figure 7: Activation of NU alarm in case of USYNC failure ---------------------------------------------------------------11
Figure 8: Possibilities for the clock synchronisation ------------------------------------------------------------------------12
Figure 9: Structure of the line interface X.21 --------------------------------------------------------------------------------14
List of tables
Table 1: Significance of the LED LIA displays---------------------------------------------------------------------------------- 8
Table 2: Significance of the LED LID-1 displays------------------------------------------------------------------------------- 8
Table 3: Significance of the LED LID-2 displays------------------------------------------------------------------------------- 8
Table 4: Significance of the LED OK/BGAL displays-------------------------------------------------------------------------- 8
Table 5: Setting options for the local clock synchronisation of the iSWT --------------------------------------------------11
Table 6: Message structure for the digital line interfaces --------------------------------------------------------------------13