Lab5

1. Construct a 30-second down counter with pause function. When the counter
goes to 0, all the LEDs will be lighted up. You can use one push button for reset
and one other for pause/start function.

1.1 Implement a periodic 30-second down counter and demo with the FPGA board.
1.2 Implement Prelab 1.3 and demo with the FPGA board.
1.3 Combine 1.2 and 1.3 to finish the experiment.

Input: clk, rst, in(push button)

Output: [15:0] led, [3:0] ssd_ctl, [7:0] segs
Block Diagram:

2 digits down counter:

Implementation:
30
0 LED frequency divider
(down counter)FSM()(scan_ctl display)
module 1Hz 1Hz down
counter inputFSM output count_enable down counter
input down counter scan_ctl
display LED module
down counter output 0 LED

FSM:
FSM output count_enable down counter
state state push
button (input in) next state ouput:
state
in 1b0 (pause state) 1b1 (count state)

in = 1( push button) 1b1 (next state)/1 (count enable) 1b0 / 0

in = 0 1b0 / 0 1b1 / 1

down counter (2 bits):

2 bits down counter down counter
 borrow decrease
limit = 9
output digit1 digit0 scan_ctl

I/O Pin:
I/O Led[15] Led[14] Led[13] Led[12] Led[11] Led[10] Led[9] Led[8]
Pin L1 P1 N3 P3 U3 W3 V3 V13
I/O Led[7] Led[6] Led[5] Led[4] Led[3] Led[2] Led[1] Led[0]
Pin V14 U14 U15 W18 V19 U19 E19 U16
I/O Segs[7] Segs[6] Segs[5] Segs[4] Segs[3] Segs[2] Segs[1] Segs[0]
Pin W7 W6 U8 V8 U5 V5 U7 V7
I/O Ssd_ctl[3] Ssd_ctl[2] Ssd_ctl[1] Ssd_ctl[0] clk rst in
Pin W4 V4 U4 U2 W5 U17 U18

Discussion:
prelab
led module
finite state machine
verilog code

2. The same function as Exp. 1. Instead of using two push buttons for reset/ pause/
start, try to use just one push button to finish the design. (Hint: You can press the
push button longer to represent the reset)

Input: clk, in(push button)

Output: [15:0] led, [3:0] ssd_ctl, [7:0] segs
Block Diagram:
 Implementation:
push button
reset
module module
reset choose module
[2:0]in_latch clk 0 1 push button in_latch[0]
1 clk 3 trigger( 3 ) push button
[2:0] in_latch 3b111 in_latch = 3b111 rst 1
reset

I/O Pin:
I/O Led[15] Led[14] Led[13] Led[12] Led[11] Led[10] Led[9] Led[8]
Pin L1 P1 N3 P3 U3 W3 V3 V13
I/O Led[7] Led[6] Led[5] Led[4] Led[3] Led[2] Led[1] Led[0]
Pin V14 U14 U15 W18 V19 U19 E19 U16
I/O Segs[7] Segs[6] Segs[5] Segs[4] Segs[3] Segs[2] Segs[1] Segs[0]
Pin W7 W6 U8 V8 U5 V5 U7 V7
I/O Ssd_ctl[3] Ssd_ctl[2] Ssd_ctl[1] Ssd_ctl[0] clk in
Pin W4 V4 U4 U2 W5 U18

Discussion:

push button verilog
code 3
block diagram
input output
lab
lab