160120124327

Implementation of Bandgap
Reference Circuits
ACKNOWLEDGMENT
We would like to extend our heartfelt gratitude to those individuals
and organizations without whom the project would not have been
possible.
Firstly, we would like to thank our guide Mr. G. Shiva Kumar,
Assistant Professor, Department of Electronics and Communication
Engineering who supported us a lot in successfully completing our
project.
We would like to thank the Head of the Department Dr. K.
Manjunatha chari, for encouraging us and giving a due support in our
project work.
We are highly indebted to Mr. Md. Masood Ahmad for his guidance
and willingness to share his vast knowledge, made us understand this
project and its manifestations in great depths and helped us to complete
the assigned tasks.
We would also thank our Institution and my faculty members
without whom this project would have been a distant reality.
Last but not least, we would like to thank our family and friends for
their encouragement and support.
1
Dept. Of ECE , GITAM University, HYDERABAD
Reference Circuits
M Lingadhar Reddy
ABSTRACT
In the design of analog integrated circuits its important to create
reference voltages and currents with well defined values. Bandgap
reference circuits are regularly used to achieve it on-chip. Especially in
analog to digital conversion, where the input voltage is compared to
several reference levels in order to determine the corresponding digital
value, a best application is this bandgap reference voltages. The main
intention in this project work is to understand the performance
limitations as well as the design of a bandgap reference circuit, BGR.
In this project work we studied the different types of bandgap
reference types and bandgap circuits. Then a detailed analysis of Opamp
design was studied. Finally the BGR circuit which is capable of
producing an constant output reference voltage for given supply voltage
was implemented .The tool used is CADENCE for schematic simulation
and all of these circuits are implemented in 90nm CMOS technology.
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INDEX
LIST OF FIGURES...................................................................................v
LIST OF TABLES....................................................................................vi
ABBREVIATIONS...................................................................................vii
1.1.Introduction to bandgap reference circuits.....................................1
1.2 Zener diode references....................................................................3
1.3 Enhancement and depletion reference............................................4
1.4 Bandgap reference approach..........................................................6
1.5 Comparison of the three reference approaches...............................9
CHAPTER 2...........................................................................................10
STUDY OF BGR CIRCUITS....................................................................10
2.1 Introduction.................................................................................11
2.2 Major Bandgap Dependencies......................................................11
2.2.1 Process variations..................................................................11
2.2.2 Power supply..........................................................................11
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2.2.3 Temperature...........................................................................12
2.3 Current summing approach.........................................................12
2.4 Voltage summing approach..........................................................13
2.5 A Simple Three-Terminal IC Bandgap Reference...........................14
2.5.1 Limitations of this circuit.......................................................19
2.6 CMOS Bandgap Reference Circuit................................................20
2.7 Basic bandgap design considerations...........................................22
2.7.1 Traditional Bandgap...............................................................22
2.7.2 Basic Bandgap Considerations...............................................22
2.8 BGR and process parameters relation.........................................24
CHAPTER 3...........................................................................................25
STUDY OF OPAMP................................................................................25
3.1 Introduction.................................................................................26
3.2 Impact of op-amp in cmos bandgap references.............................28
3.3 Basic CMOS Op-Amp...................................................................29
3.3.1 Input differential amplifier......................................................31
3.3.2 Compensation........................................................................31
3.3.3 Bias circuit.............................................................................32
3.4 Characteristic features of op-amp.................................................32
3.4.1 Open loop gain..........................................................................32
3.4.2 Common mode gain................................................................32
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3.4.3 Common mode rejection ratio.................................................32
3.4.4 Slew rate................................................................................33
3.4.5 Input common mode voltage range.........................................33
3.4.6 Unity gain bandwidth.............................................................33
3.5 Design Of Two Stage CMOS Operational Amplifier........................33
3.5.1 Steps in designing a cmos Opamp..........................................33
3.5.2 Some practical thoughts on op amp design............................34
3.6 Design strategy of op-amp............................................................35
3.6.1 Dual input Differential Amplifier............................................36
3.6.2 Bias String.............................................................................36
3.6.3 Output Buffer.........................................................................36
3.6.4 Calculation of w/l values........................................................37
3.7 Bandgap Reference - Opamp with 1V power supply......................43
CHAPTER 4...........................................................................................45
SIMULATION RESULTS.........................................................................45
4.1 Opamp.........................................................................................46
4.1.1 Implemented Opamp..............................................................46
4.1.2 Opamp testing........................................................................47
4.1.3 opamp waveforms...................................................................48
4.1.4 Simulation results..................................................................48
4.2.1 Implemented BGR..................................................................49
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4.2.2 BGR waveforms......................................................................51
CONCLUSION.......................................................................................54
APPENDIX.............................................................................................55
REFERENCES.......................................................................................69
LIST OF FIGURES
Figure 1 Buried Zener diode reference................................................4
Figure 2 Simple voltage reference circuit.............................................6
Figure 3 Variation of reference voltage with temperature.....................7
Figure 4 A simplified circuit of a bandgap voltage reference................8
Figure 5 Schematic of Sum of currents configuration......................13
Figure 6 Schematic of Sum of voltages configuration.......................14
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Figure 7 Conventional bandgap circuit.............................................16
Figure 8 Idealized circuit illustrating two-transistor bandgap cell.....17
Figure 9 Circuit for developing higher output voltages .....................18
Figure 10 Conventional bandgap reference circuit.............................21
Figure 11 Block diagram of Op-Amp.................................................30
Figure 12 Basic two stage cmos operational amplifier topology........36
Figure 13 Opamp genral gain and phase plot....................................38
Figure 14 Implemented 2 stage cmos Opmap....................................47
Figure 15 Testing Opmap with symbol..............................................48
Figure 16 Opamp gain and phase plot..............................................49
Figure 17 Implemented CMOS bandgap reference.............................50
Figure 18 Temperature dependence of the bandgap reference voltage52
Figure 19 Noise spectrum of the proposed bandgap reference...........53
Figure 20 Reference voltage changes with supply voltage increase. . .54
LIST OF TABLES
Table 1 Dimensions of the proposed opamp...........................................48
Table 2 Simulation results of the proposed opamp................................49
Table 3 Dimensions of the proposed BGR..............................................51
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ABBREVIATIONS
BGR bandgap reference circuit
CMOS complementary metal oxide semi conductor
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CTAT complementary to absolute temperature voltage
MOSFET metal oxide semiconductor field effect transistor
NMOSFET negative channel MOSFET
PMOS positive channel metal oxide semi conductor
PPM parts per million
PTAT proportional to absolute temperature voltage
SOI silicon on insulator
TC temperature coefficient
GBW gain band width
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CHAPTER 1
INTRODUCTION
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1 Introduction to bandgap reference circuits
Precision bandgap voltage references are critical building blocks for a
variety of analogue and mixed signal electronic devices such as data
converters, PWM controllers, oscillators, operational amplifiers, linear
regulators and PLLs. undoubtedly the reference voltage accuracy plays a
significant part in determining the performance of all subsequent
circuits, which depend on an accurate and stable reference. For example,
high precision ADCs, which are widely used in instrumentation and
measurement systems, require a high precision voltage reference if the
large number of bits in modern processing systems are to have any
significance. Temperature dependent drift of the reference voltage is
undoubtedly one of the key issues in BGR design. It is known that the
base-emitter voltage of the bipolar transistor is better characterized over
temperature and varies less than the threshold voltage and mobility of
the MOS transistors. Thus, most of the voltage references use the bipolar
transistors pan junction as the basis of reference generation. Other
approaches use the gate-source voltage of sub threshold MOSFETs.
One of the most used topologies of CMOS Bandgap Voltage
References (BGR) is that one with operational amplifier (op-amp), current
source, three resistors and two parasitic bipolar transistors. Besides the
simplicity and good performance achieved by this BGR, this topology can
be easily modified to achieve high-accuracy. In literature, many different
op-amps are employed in this BGR architecture. Since the BGR
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Reference Circuits
performance depends strongly on the performance of the amplifier used,
the op-amp design deserves attention and its architecture must be
careful chosen. Therefore, aiming to achieve the best trade-off between
several op-amps used in BGRs, it is necessary to realize a comparative
analysis.
The performance of designs, which use a linear combination of a
base-emitter voltage and a thermal voltage (BJT), is limited by the
nonlinear dependence of the base emitter voltage. We propose an
alternative implementation which achieves a higher order cancellation for
the base-emitter nonlinearity over a much wider temperature range. A
second op-amp is used to generate a CTAT (Complementary to Absolute
Temperature) current. This current is subsequently used to fine-tune the
curvature correction mechanism so as to achieve a new level of
performance. The proposed topology is sensitive to device mismatch;
therefore resistor trimming is necessary to compensate for mismatch.
The objective of this thesis lies on theoretical understanding of
performance limitations and to design a BGR circuit.
Here, we study the three approaches that are stated in detail. A
number of approaches to realize voltage references in integrated circuits
have been reported. These can be categorized in the following three
approaches.
a) Making the use of a zener diode that breaks down at a known
voltage when reverse biased.
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b) Making use of the difference in the threshold voltage between an
enhancement transistor and a depletion transistor.
c) Cancelling the negative temperature dependence of a pn junction
with positive temperature dependence from a PTAT (proportional to-
absolute temperature) circuit.
1.2 Zener diode references
Approach (a) uses the principle of zener breakdown when reverse
biased. In this section two zener diode approaches are discussed, namely
buried zener diode and buried transistor base emitter method. The
operation is shown in fig .1. This zener breakdown effect occurs at the
die surface, so it is subject to contamination and oxide charge problems.
Surface zener diodes have several problems for on chip implementations
they require breakdown voltages greater than 5V, they are noisy, and
they have poor short and long term voltage drift.
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Figure 1 Buried Zener diode reference [1]
Later a solution using a buried transistor base-emitter junction
was introduced. The buried junction zener diode has stable subsurface
breakdown mechanism that yields good noise performance. Also, surface
contamination and oxide effects do not affect the buried junction. Hence,
this zener diode makes an outstanding voltage reference. Zener diodes
still have several problems, such as line regulation, load regulations, and
a fixed voltage output. The output voltage variation arising from a
specific change in input voltage is defined as Line regulation. Load
regulation is the change in output voltage for specific changes in load-
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current. These problems are solved by using an opamp and a current
source as shown in FIGURE 1.
A current source biases the zener diode, which keeps the zener
current constant in spite of line voltage fluctuations. The opamp buffers
the zener diode, thus minimizing the effect of load current fluctuations.
Inspite of all these solutions, the breakdown voltage of the zener diode is
still larger than the power supplies used in most of the modern circuits.
So, this approach is not popular now a days.
1.3 Enhancement and depletion reference
Just using the threshold voltage of an NMOSFET, they are not
suitable to be used as a reference over a wide temperature range.
Instead, the difference between two threshold voltages can be used to
decrease the temperature sensitive factors. This can be obtained by using
the difference of the threshold voltage of a depletion mode MOSFET (VT <
0) from that of an enhancement MOSFET (VT > 0). The magnitude of the
reference voltage is determined by the sum of the absolute values of the
threshold voltage of the enhancement mode and the depletion mode
MOSFET. As reference voltage results in high temperature sensitivity, for
most reference circuits that are based on the absolute value of a
reference voltage cannot be controlled accurately. However the absolute
value is of little importance as it can be adjusted by laser trimming or
compensated by system design.
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Figure 2 Simple voltage reference circuit [1]
A simple voltage reference circuit using the enhancement and
depletion mode transistors are shown in fig 2.load regulation and line
regulation are not taken into consideration. In the FIGURE.2 M1, M5, M8
are enhancement NMOSFETs, where as M2, M3, M4, M6, M7 are
depletion NMOSFETS. All enhancement and depletion SOI NMOSFETs
operate in the saturation region. M1-M4 form the voltage reference part
and M5-M8 form an output buffer. The reference voltage is generated by
the threshold voltage difference between M1 and M2. M3 and M4 draw
the equal drain bias current. The current through M6 is twice that of
M7. The graph in FIGURE 3 shows the measured variation of the
reference voltage with temperature.
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Figur
e 3 Variation of reference voltage with temperature [1]
1.4 Bandgap reference approach
The voltage difference between two p-n junctions (e.g. diodes),
operated at different current densities, is used to generate a proportional
to absolute temperature (PTAT) current in a first resistor. This current is
used to generate a voltage in a second resistor. This voltage in turn is
added to the voltage of one of the junctions (or a third one, in some
implementations).
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The voltage across a diode operated at constant current, or here
with a PTAT current, is complementary to absolute temperature(CTAT
reduces with increasing temperature), with approx. 2 mV/K. If the ratio
between the first and second resistor is chosen properly, the first order
effects of the temperature dependency of the diode and the PTAT current
will cancel out. The resulting voltage is a constant voltage depending on
the particular technology and circuit design.
Figure 4 Simplified circuit of a bandgap voltage reference [2]
A conventional bandgap reference is a circuit that subtracts the
voltage of a forward-biased diode having a negative temperature
coefficient from a voltage proportional to absolute temperature (PTAT).
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Hence a controlled temperature dependence of the circuit can be
obtained. As a consequence, a temperature compensated voltage close to
the material bandgap of silicon (~1.22 V) results. Voltage references
based on this approach are called bandgap reference circuits. The
principle of a bandgap voltage reference system is shown in FIGURE 4.
BGRs with different temperature coefficients can be implemented
over a wide temperature range. There are many possible implementations
for the BGR concept, where each one achieves a different accuracy. Often
tradeoffs have to be met, as for instance, more accurate BGRs often
demand larger silicon area. Thus, it is the application who defines which
BGR architecture should be used in each design. For many applications,
such as an operational amplifier, a simple low-precision reference is fully
adequated.
The small dependence of VREF upon temperature is achieved
through a balanced adding of two voltages with opposite temperature
coefficient, as described by equation if the constants 1 2 both
temperature-independent are chosen in such way that equation is
satisfied; VREF with zero TC at room temperature is achieved at some
given temperature T where the equation below applies.
V BE =1 V 1+ 2V 2
1 V 1 2 V 2
0= +
T T
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Considering that V1 increases with temperature, it is usually called
Proportional to Absolute Temperature (PTAT) voltage. Then, V2 decreases
with temperature and is frequently called Complementary to Absolute
Temperature (CTAT) voltage [5]. There are different ways to generate V1
and V2.
1.5 Comparison of the three reference approaches
The approach in process (a) is not popular, because the breakdown
voltage of a zener diode is typically larger than the power supplies used
in modern circuits. Approach in (b) cannot either be used in most CMOS
circuits because depletion transistors are not typically available. Though
this approach can be used to make stable references with respect to
temperature, the actual reference voltage/current is difficult to determine
accurately. This is due to the process sensitivity of the difference between
the threshold voltage of an enhancement device and a depletion device.
For these reasons, the approaches in (a) and (b) are not popular. Instead
the approach(c) is mostly used in both bipolar and CMOS technologies.
Voltage references based on the last approach are commonly called
bandgap voltage references.
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CHAPTER 2
STUDY OF BGR CIRCUITS
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2.1 Introduction
In this section, the different operation principles of BGR circuits
are discussed. The operation principle of BGR circuits is to sum a voltage
with negative temperature coefficient with another one exhibiting the
opposite temperature dependence.
2.2 Major Bandgap Dependencies
2.2.1 Process variations
As mentioned, the voltage reference should be insensitive to
process variations as well. This is usually coped with by making the
output dependent on a ratio of values (pair of resistances, pair of BJTs,
etc.). Taking special care when laying out these devices, their values will
be very similar during fabrication and depend very similarly on other
parameters, such as temperature.
2.2.2 Power supply
If you need a precision voltage reference, that means you do not
have one already, right? So, the power supply to the reference will not be
precise and the reference should be insensitive to it. The way to solve this
is by differential circuits. In the bandgap examples, if the power supply
changed, the currents of both branches would be affected equally.
Therefore, the assumption of equal currents would still hold and effects
of power supply variations would cancel at the output voltage.
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2.2.3 Temperature
Still, not every temperature dependent effects can be cancelled. For
instance .Temperature changes resistance values, resistance changes
collector current and collector current changes the sensitivity of Vbe to
temperature slightly. Temperature changes the offset voltage of the
opamp, which in turn changes the voltages across the
transistors/resistances and unbalances the collector current of both
transistors.
We study two alternative topologies in this section. The first
operates by summing two currents with opposite temperature
dependence fed through the resistor. Thus, a temperature stable voltage
is generated with a value controlled by the resistor. The second technique
uses voltage summing.
2.3 Current summing approach
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Figure 5 Schematic of Sum of currents configuration [1]
A circuit using the sum of currents configuration is shown in
FIGURE 5. In this case, the circuit is split into three sub circuits
operating in parallel: The first generates a current proportional to
absolute temperature. This current is mirrored into the second sub
circuit which is employed to generate the other component. The third sub
circuit is just a resistor in which the sum of the two currents flows and
which converts them into a voltage of suitable value.
2.4 Voltage summing approach
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Figure 6 Schematic of Sum of voltages configuration [1]
A circuit using the sum of voltages configuration is shown in the
fig.6. In this case, the circuit is again divided into three sub circuits. The
only difference between the current summing BGR and the voltage
summing BGR is the third sub circuit. The third section is composed of a
differential amplifier in a non inverting feedback loop. The offset voltage
generates the PTAT component. The applied diode voltage is not the full
base-emitter voltage, as in a standard BGR, but a fraction. The minimum
supply voltage of one of the path is VT plus a V CEsat, plus the source to
drain voltage of the current source. The second paths minimum supply
voltage is a Vbe plus the minimum voltage of the current source plus the
output voltage of the VBE generator.
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2.5 A Simple Three-Terminal IC Bandgap Reference
This section deals with implementation using bipolar devices.
Conventional bandgap circuits use parallel current paths with voltage
sensing connections between the paths. These circuits are typified by
Figure 6, discussed earlier to illustrate the operation of more complex,
but fundamentally similar circuits. In this well-known circuit parasitic
currents exchanged between the parallel paths are not accounted for in
the theory and give rise to beta-dependent voltage errors and
temperature drift. To generate higher voltages with the conventional
circuit, it is necessary to stack junctions to produce a multiple of the
bandgap voltage or use a second amplifier to multiply the separately
stabilized bandgap voltage.
Here, transistors Q1 and Q2 are operated at different current
densities to produce voltages proportional to temperature across the
resistors R3 and R2. The transistor Q3 is used to sense the output
voltage at R2. So, Q3 drives the output to a voltage which is the sum of
its VBE and the temperature dependent voltage across R2. When the
output voltage is set to approximately the bandgap voltage of silicon, the
voltage across R2 will compensate the temperature coefficient of VBE,
and the output voltage will have a low TC.
To minimize the output voltage temperature coefficient, the
collector current of Q3 is made proportional to temperature, as are the
currents in Q1 and Q2. Introducing this temperature dependent currents
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make it inconvenient to produce an output voltage greater than the
bandgap voltage.
Figure 7 Conventional bandgap circuit [1]
The idealized circuit shown in FIGURE 8 reduces the difficulties in
increasing the output voltage above the bandgap voltage and also
reduces the problem of hfe variability. hfe is the term used to describe the
current gain parameter of a bipolar transistor. It gives the ratio of the
collector current to the base current. The circuit can be implemented
with thin-film resistors on the monolithic chip, if it is supplied by the
vendor, to virtually eliminate the nonlinear temperature coefficients of
the resistors as an error factor. Here, this idealized circuit uses two
transistors and collector current sensing to produce the bandgap voltage.
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Since, the output voltage is fed to the base of the transistor it becomes
easy to obtain output voltages above the bandgap voltage.
Figure 8 Idealized circuit illustrating two-transistor bandgap cell [1]
In the circuit in fig .8 [10], the emitter area of Q2 is made larger
than that of Q1 by a ratio of 8-to-1. When the voltage at their common
base is small, so that the voltage across R2 is small. The larger area of
Q2 causes it to conduct a larger part of the total current through R1.
This results in a difference of collectors voltages, which in turn drives the
opamp to increase the base voltage. Hence, a negative feedback loop is
used. The difference in current density to increase the difference in VBE,
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between Q1 and Q2, which will appear across R2. This difference is given
by the equation
kT J 1
V BE= ln
q J 2
Since, in the DC operation point, the current in Q1 is equal to current in
Q2, the current in R1 is twice that the current in R2. So, the voltage
across R1 is given by the equation

2 R1 kT J 1
V 1= ln
R2 q J2
The voltage at the base of Q1 is the sum of VBE of Q1 and the
temperature dependent voltage across R1. So, the output voltage can be
set by the adjustment of R1/R2.
Figure 9 Circuit for developing higher output voltages [1
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Even high output voltage level can be increased in the following
way. Suppose that the amplifier in fig .8 has sufficient low frequency
gain. So it will balance the collector currents of Q1 and Q2 despite an
additional voltage drop added between its output and the common base
connection. This additional drop will not affect the base voltage which
results in collector current balance. If the voltage is introduced by means
of a resistive voltage divider, the opamp output voltage will be
proportional to the common-base voltage. The circuit of fig .9 uses an
active load to sense the collector currents of Q1 and Q2. The function of
the opamp is replaced by Q10, Q11 and Q7. The pnp transistors form a
simple current mirror, where the difference of the collector currents of
Q1 and Q2 is fed to Q7. Then Q7 supplies the circuit output voltage. This
voltage is divided between R4 and R5 and applied to the base of Q1.
Since the output voltage depends on resistors R4 and R5, it can be set to
any convenient value and need not be an integral multiple of the
bandgap voltage.
In the circuit of fig .9 the base current of Q1 and Q2 must flow
through R4. This current will require an increase in the output voltage
above the nominal to bring the base of Q1 to the proper level. This
increase will depend on hfe which varies with temperature and process
parameters. This effect can be minimized by using relatively low values
for R4 and R5, or R3 can be added to compensate the effect. The proper
value of R3 is given by the following analysis. To make the analysis
simpler, neglect the effects of finite hfe and output conductance of Q10,
Q11, Q7 in fig 13. to idealize the performance of the amplifier function. If
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V is taken to be the circuit output voltage in the absence of base current
for Q1 and Q2, then V resulting from considering R3 and the two base
currents is given by
2 R1 R4
'
V =V + R4 ( i b 1 +i b 2 )i b 2 R 3 ( )
R2
(1+ )
R5
This relation contains a term due to the base currents through R4
and an offsetting term due to reduction V be of by base current
through R3. If V' is set equal to V, the above equation can be reduced
to a constraint on R3 as given by
ib 1 R2 R4 R5
R3=( + 1)
ib 2 2 R1 (R4 + R 5)
The general form of the expression is useful in circuits where the current
density ratio is controlled by forcing unequal collector currents, rather
than by emitter area ratios.
2.5.1 Limitations of this circuit
Although, the circuit of fig .9 can be used in some simple
applications, there are some limitations in its applicability like,
1. Base width modulation of Q1 and Q2
2. Finite output impedance of Q11
3. Finite hfe of Q7, Q10 and Q11.
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All these factors combine to raise the circuits dynamic impedance and to
degrade its input-voltage rejection.
2.6 CMOS Bandgap Reference Circuit
A conventional bandgap reference circuit is shown in fig.7. This
conventional bandgap reference circuit consists of an Opamp, two bipolar
transistors and resistors. The bipolar transistor can often be
implemented in CMOS technology. The bipolar transistors are connected
as diodes. The principle of operation is that the Opamp ensures equal
voltage in nodes X and Y.
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Figure 10 Conventional bandgap reference circuit [1]
The relation of the current versus voltage in a general diode is

expressed as
I = Is. ( e q V BE / kT
1 )
when VBE >> kT/q, then
I = Is . e qVBE/kT
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VBE = VT . in (I/Is) where VT = kT/q, k is Boltzmanns constant and q is
the electron charge. In the conventional bandgap circuit, the inputs of
the opamp, Vx and Vy are maintained at the same voltage. So, the
voltage across resistor R3 is given as
VBE = VBE1 VBE2 = VT ln(nR2/R1)
The emitter area of Q2 is n times of that of Q1. So the output
voltage Vref, of this bandgap reference becomes
Vref = VBE1 + R2/R3 VBE
= VBE1 + R2/R3 ln(n* R2/R1) . VT
where VBE1 is the built-in voltage of the bipolar Q1. By choosing
the appropriate resistance ratio of R1,R2 and R3, temperature
dependence of Vref will become negligibly small.
Two major drawbacks of this circuit are
1. The input offset voltage of Opamp will introduce error in the
output bandgap voltage.
2. The output of the Opamp has resistive impedance.
2.7 Basic bandgap design considerations
2.7.1 Traditional Bandgap
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For applications where accuracy is critical for a broad range of
environments, a temperature-compensated reference is required. The
standard design methodology for such a reference is to sum predictable,
well-characterized, temperature-dependent components, in order to
achieve a well-adjusted temperature- compensated response. Thus the
first step is to find well characterized voltages or currents that do not
vary significantly with process variations.
2.7.2 Basic Bandgap Considerations
In most bandgap topologies are the voltage of a diode connected
bipolar transistor is chosen to be the main element with well-
characterized, temperature-dependent characteristics as shown in Fig.1.
In this case, the base-emitter voltage is related to the bandgap energy
and is to be used as part of the compensation method. The collector
current of a BJT as a function of the base-emitter voltage in the forward
active region is
Ic(T)=Ics(T)exp(qVBE/kT)
where is VBE is the base-emitter voltage, T is the is the absolute
temperature, is the k Boltzmann constant and q is the electron charge.
Ics is the scale current that is proportional to the base-emitter area and
is equal to:
(T )
qA n2i D
I CS (T )=
NB
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where A the emitter area, n(T) intrinsic carrier concentration, D(T) is the
effective minority carrier diffusion constant in the base and NB is the
total number of impurities per unit area in the base. There exists a
relation between the intrinsic carrier concentration and the bandgap
energy which is
E G (T )
N i ( T )=CT exp [ -
2 3

kT
where C is constant and is the bandgap energy. The effective minority
carrier diffusion constant in the base has a temperature dependency
which can be expressed with the help of Einstein relation which connects
a carriers drift mobility and its diffusion constant

D as follows
(T )= kT (T )
D
q
where (T ) is the mean mobility of the minority carriers in the base
and has the following temperature dependency
(T )=B T n
where B and n are constants. Using the above equations we can write
kT I (T )
V BE ( T )=V G ( T ) + ln [ c n ]
q C T
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where V G ( T ) is the bandgap voltage and is a constant. Finallywe can
derive the most general equation without approximation of the
temperature dependence of the base-emitter voltage [11]
T
T
I c ( r )
( r )
I (T )
I s (T ) c
Is

k Tr
( )
V BE ( T )=
T
Tr ( )
{V BE }+
q
ln
where T is arbitrary temp and Tr specified reference temperature.
2.8 BGR and process parameters relation
The variations of the VDD, temperature, number of bipolars, W/L of
PMOS, DC gain, RL, CL are calculated for the practical generation of
PTAT current generator circuit. Also, we will study the process variations
and non-idealities of the opamp like input offset voltage, bandwidth, etc.
38
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CHAPTER 3
STUDY OF OPAMP
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3.1 Introduction
Operational Amplifiers are the basic building block of many analog
circuits. They have wide applications in many analog circuit including
switched capacitor filters, sigma delta A/D converter, sample and hold
amplifiers etc.
The trend towards low voltage low power silicon chip systems has
been growing due to the increasing demand of smaller size and longer
battery life for portable applications in all marketing segments including
telecommunications, medical, computers and consumer electronics. The
operational amplifier is undoubtedly one of the most useful devices in
analog electronic circuitry. Op-amps are built with different levels of
complexity to be used to realize functions ranging from a simple dc bias
generation to high speed amplifications or filtering. With only a handful
of external components, it can perform a wide variety of analog signal
processing tasks. Op-amps are among the most widely used electronic
devices today, being used in a vast array of consumer, industrial, and
scientific devices. Operational Amplifiers, more commonly known as Op-
amps, are among the most widely used building blocks in Analog
Electronic Circuits.
An operational amplifier is a DC-coupled differential input voltage
amplifier with an rather high gain. In most general purpose op-amps
there is a single ended output. Usually an op-amp produces an output
voltage a million times larger than the voltage difference across its two
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input terminals. An ideal Opamp is characterized by very high input
impedance (ideally infinite) and low output impedance at the output
terminal(s) (ideally zero).to put it simply the opamp is one type of
differential amplifier. This section briefly discusses the basic concept of
op-amp. An amplifier with the general characteristics of very high voltage
gain, very high input resistance, and very low output resistance generally
is referred to as an op-amp. Most analog applications use an Op-Amp
that has some amount of negative feedback.
Over the last few years, the electronics industry has exploded. The
largest segment of total worldwide sales is dominated by MOS market.
CMOS technology continues to mature with minimum feature sizes now.
Designing high performance analog integrated circuits is becoming
increasingly exigent with the relentless trend toward reduced supply
voltages and transistor channel length. A large part of the success of the
MOS transistor is due to the fact that it can be scaled to increasingly
smaller dimensions, which results in higher performance. The feature
size of individual transistor is shrinking from deep sum-micrometer
(DSM) to even nanometer region. As the scale of integration improves,
more transistors, faster and smaller than their predecessors, are being
packed into a chip. This leads to the steady growth of the operating
frequency and processing capacity per chip. Operational Amplifier is the
most common building blocks of most of the electronics system may not
need introduction. The design of OPAMPs continues to pose a challenge
as the supply voltage and transistor channel lengths scale down with
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each generation of CMOS technologies. At different aspect ratio, there is
a tradeoff among speed, power, gain and other performance parameters.
The realization of a CMOS OPAMP that combines a considerable dc gain
with high unity gain frequency has been a difficult problem. There have
been several circuit approaches to evade this problem.
The aim of the design methodology in this paper is to propose
straightforward yet accurate equations for the design of high-gain 2
staged CMOS op-amp. To do this, a simple analysis with some
meaningful parameters (phase margin, gain-bandwidth, etc.) is
performed. The method handles a very wide variety of specifications and
constraints. In this paper, we formulate the CMOS op-amp design
problem and their aspect ratios. The method we present can be applied
to a wide variety of amplifier architectures, but in this paper we apply the
method to a specific two stage CMOS op-amp. The variation in the
performance of the op-amp with variations in the width and length of the
CMOS and the effect of scaling the gate oxide thickness is discussed.
3.2 Impact of op-amp in cmos bandgap references
One of the most used topologies of CMOS Bandgap Voltage
References (BGR) is that one with operational amplifier (op-amp), current
source, three resistors and two parasitic bipolar transistors. Besides the
simplicity and good performance achieved by this BGR, this topology can
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be easily modified to achieve high-accuracy. In literature, many different
op-amps are employed in this BGR architecture. Since the BGR
performance depends strongly on the performance of the amplifier used,
the op-amp design deserves attention and its architecture must be
careful chosen. Therefore, aiming to achieve the best trade-off between
several op-amps used in BGRs, it is necessary to realize a comparative
analysis.
3.3 Basic CMOS Op-Amp
Operational Amplifiers are the backbone for many analog circuit
designs. Op-Amps are one of the basic and important circuits which have
a wide application in several analog circuit such as switched capacitor
filters, algorithmic, pipelined and sigma delta A/D converter, sample and
hold amplifier etc. The speed and accuracy of these circuits depends on
the bandwidth and DC gain of the Op-amp. Larger the bandwidth and
gain, higher the speed and accuracy of the amplifier Op-amp are a
critical element in analog sampled data circuit, such as SC filters,
modulators. The general block diagram of an op-amp with an output
buffer is shown below.
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Figure 11 Block diagram of OpAmp [ 6 ]
The first block is a differential amplifier. It has two inputs which are
the inverting and non-inverting voltage. It provides at the output a
differential voltage or a differential current that, essentially, depends on
the differential input only. The next block is a differential to single-ended
converter. It is used to transform the differential signal generated by the
first block into a single ended version. Some architecture doesnt require
the differential to single ended function; therefore the block can be
excluded. In most cases the gain provided by the input stages is not
sufficient and additional amplification is required. This is provided by
intermediate stage, which is another differential amplifier, driven by the
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output of the first stage. As this stage uses differential input unbalanced
output differential amplifier, so it provide required extra gain. The bias
circuit is provided to establish the proper operating point for each
transistor in its saturation region. Finally, we have the output buffer
stage. It provides the low output impedance and larger output current
needed to drive the load of op-amp or improves the slew rate of the op
amp. Even the output stage can be dropped: many integrated
applications do not need low output impedance; moreover, the slew rate
permitted by the gain stage can be sufficient for the application. If the
op-amp is intended to drive a small purely capacitive load, which is the
case in many switched capacitor or data conversion applications, the
output buffer is not used. When the output stage is not used the circuit,
it is an operational transconductance amplifier, OTA. The purpose of the
compensation circuit is lower the gain at high frequencies and to
maintain stability when negative feedback is applied to the opamp. Now
we going to know each part in block diagram
3.3.1 Input differential amplifier
The MOSFET is by far the most widely used transistor in both
digital and analog circuits, and it is the backbone of modern electronics.
One of the most common uses of the MOSFET in analog circuits is the
construction of differential amplifiers. The latter are used as input stages
in op-amps, video amplifiers, high-speed comparators, and many other
analog-based circuits. MOSFET differential amplifiers are used in
integrated circuits, such as operational amplifiers, they provide a high
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input impedance for the input terminals. A properly designed differential
amplifier with its current-mirror biasing stages is made from matched-
pair devices to minimize imbalances from one side of the differential
amplifier to the other.
The general topology of a differential amplifier is shown below. Two
active devices are connected to a positive voltage supply via passive
series elements. The transistors must be a matched pair (i.e., two
matched MOSFETs or two matched BJTs). The "pull up" loads are
similarly matched to each other. The lower terminals of the active devices
are connected together, and a dc current source pulls current down
toward the negative voltage bus to effect the bias. The controlling input
ports of the devices are connected to input signals.
3.3.2 Compensation
Types of Compensation
Miller - Use of a capacitor feeding back around a high gain,
inverting stage.
Self compensating - Load capacitor compensates the op amp
(later).
Feed forward - Bypassing a positive gain amplifier resulting in
phase lead. Gain can be less than unity.
3.3.3 Bias circuit
Op amps with simple input structures using MOSFET long-tailed
pair have bias currents that flow in one direction. More complex input
structures (bias-compensated and current feedback op amps) may have
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bias currents that are the difference between two or more internal
current sources, and may flow in either direction .Bias current is a
problem to the op amp user because it flows in external impedances and
produces voltages, which add to system errors. By providing this
necessary bias currents via an internal current source. the only external
current then flowing in the input terminals is the difference current
between the base current and the current source, which can be quite
small.
3.4 Characteristic features of op-amp
3.4.1 Open loop gain
The ratio of change in output voltage to the change in voltage
across the input terminals is known as open loop gain of the op-amp. It
is also known as differential mode voltage amplification
3.4.2 Common mode gain
The ratio of output voltage to the input voltage when both the
terminals of the op-amp are supplied same potential is known as
common mode gain of opamp. It is also known as common-mode voltage
amplification [ 7 ] .
3.4.3 Common mode rejection ratio
The ratio of differential voltage amplification to common-mode
voltage amplification is known as common mode rejection ratio (CMRR).
Ideally this ratio would be infinite with common mode voltages being
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totally rejected.
3.4.4 Slew rate
The rate at which the output changes with respect to the time
required for a step change in the input is known as slew rate of the op-
amp. It is generally expressed in the units of V/ sec.
3.4.5 Input common mode voltage range
The range of common-mode input voltage that may cause the operational
amplifier to cease functioning properly if the input voltage goes beyond
this range is known as input common mode voltage range.
3.4.6 Unity gain bandwidth:
The range of frequencies within which the open-loop voltage
amplification is greater that unity is referred as the unity gain bandwidth
of the op-amp.
3.5 Design Of Two Stage CMOS Operational Amplifier
3.5.1 Steps in designing a cmos Opamp
Choosing or creating the basic structure of the op amp.

Decide on a suitable configuration determination of the type of
compensation needed for meeting the specification. Most of the
effort of design is in this category. Simulators are used to aid the
designer in this phase.

Selection of the dc currents and transistor sizes.
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Physical implementation of the design. Floor planning the
connections pinouts, power supply buses and grounds. Extraction
of the physical parasitics and re - simulation.

Fabrication
Measurement
Verification of the specifications
Modification of the design as necessary
3.5.2 Some practical thoughts on op amp design
Decide upon a suitable topology.
The topology should be the one capable of meeting most of
the specifications
Try to avoid inventing a new topology but start with an
existing topology
Determine the type of compensation needed to meet the
specifications.
Consider the load and stability requirements
Design dc currents and device sizes for proper dc, ac, and
transient performance.
This begins with hand calculations based upon approximate
design equations.
Compensation components are also seized in this step of the
procedure.
After each device is sized by hand, a circuit simulator is used
to fine tune the design
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3.6 Design strategy of op-amp
The design process involves the two major steps, the first is the
conception of design, and second one is optimization of design. The
conception of the design has been accomplished by proposing
architecture to meet the given specifications. This step is normally done
by using hand calculations in order to maintain the intuitive view point
necessary for choices that must be made. Second step is to take the
first-cut design and verify and optimize it. This is normally done by
using Computer simulation and can include such influences as
environmental or process variations.
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Figure 12 Basic two stage cmos operational amplifier topology[ 4 ]
The design procedure assumes that the gain at dc (Av), unity gain
bandwidth (GB), input common mode range (Vin(min) and Vin(max)),
load capacitance (CL), slew rate (SR), output voltage swing (Vout(max)
and Vout(min)), and power dissipation (Pdiss) are given. Choose the
smallest device length which will keep the channel modulation parameter
constant and give good matching for current mirrors. The basic 2 stage
operational amplifier consists of three sections shown in fig.9.
3.6.1 Dual input Differential Amplifier
In Fig.12, the transistors M1, M2, M3 and M4 form the first stage
i.e. differential stage of the operational amplifier.M1 and M2 are nmos
transistors whose gate acts as the differential input node. Gate of nmos
M2 is the inverting input and the gate of nmos M1 is the non-inverting
input. In this stage current is mirrored from M3 by M4 and M1 and
subtracted from the current through M5.This current mirror topology is
used for converting the differential input signal to single ended output
signal.
3.6.2 Bias String
In Fig. 12, the bias string block of the op-amp architecture is
formed by transistor M5 that supplies a voltage between the gate and
source of M7 , M5 and M7 are diode connected and hence, it ensures
that they operate in saturation region. The required biasing of the
remaining transistors is controlled by their respective node voltages.
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3.6.3 Output Buffer
The Output buffer, more commonly known as Second Gain Stage,
comprises of transistor M6 and M7 in Fig. 9. It is a common source
amplifier which provides an additional gain to the amplifier. The output
of the differential input stage acts as the input for this stage. The gain
provided by this stage is the product of trans-conductance of M6 and the
effective load resistance i.e. the output resistance of M7 and M6.
3.6.4 Calculation of w/l values
The values of (w/l) for the transistors were calculated using the
following process
1.Design parameters
DC Gain (Av) , Unity Gain Bandwidth, Power Dissipation,
Slew Rate, Input Offset Voltage, PSRR, Output Voltage Swing , ICMR &
CMRR, Frequency Response, Phase Margin ,Load Capacitance ,Device
Dimensions ,Compensation
2.Boundry conditions
Process steps : Vt , uncox etc.. , Supply voltage , Supply current
and range and Operating temperature.
3. pole zero concept
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Figure 13 Opamp genral gain and phase plot [ 4 ]
Let p1 and p2 be two poles and z be the zero occurring in the gain
transfer function . P1 is dominant pole and releated to bandwidth and p2
is second pole and releated to GBW. Both poles p1 and p2 and also z
governs to phase margin M . by solving simple two port network with
Kirchhoffs use leads to
( g ds2 + g ds4 ) (gds 6 + gds 7)

p1 = and
gm6 cc
g m 6
p2=
c2
gm 6
Z=
cc
And the unity gain band width GBW given as
g m1 gm 2
GBW = =
cc cc
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The phase margin defined as
w
p2

w
M =180 tan 1 ( )tan1
p1
For second stage we have
w
p2

w
M =60 =180 tan1( )tan1
p1
Or
w
p2

w
M =120 =tan 1 ( )+ tan 1
p1
From the above equation unity at unity gain band with
GBW
p2

GBW
M =120 =tan 1 ( )+ tan 1
p1
In general z is placed as at least 10 times of GBW frequency
w
So we take z =0.1
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GBW
p2

Then
1 GBW
M =120 =tan ( )+ tan 1
p1
However p1 which is dominant pole the gain is Av 0
1 GBW
So A v 0=tan ( )
p1
Since Opamp dc gain Av 0 is chosen very high and phase given as
GBW
p2

M =120 =90+ tan1
GBW
p2 GBW
From this =24.3 or p2
=0.4515
1
tan
Hence p2=10 GBW
Since z can be placed ahead of 10 * GBW
Therefore Pole |p2| can be placed >= 2.2 * GBW
gm6 gm2
Or c2
2.2
cc
2.2 c 2 g m 2
Or C c = gm 6
From zero placement we take
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Z1 > 10 GBW or
gm6 gm2
2.2 Or gm 6 10 gm 2
cc cc
Hence c c 2.2 c 2
By considering the differential amplifier pole and zero we have a
capacitor c3 as a part of diffamp. This c3 leads to a pole and zero for DA
gain function and its found that pole p3 and zero z3 due to c3 the pole
and zero approximated as

g m 3
p3=
c3
and
2 gm 3
z 3=
c3
Since gm 3 much higher than gm 6g m 7 and |p3| > |p2| and so is |
z3| > |p2| as well may be > |z|.
Since both p3 and z3 are negative and hence they are likely to
cancel each other, leading stability. Hence normally does not care about
c3 in gain evaluation. However there is still worry about of control of
right half plane zero. To eliminate effect of z1, we can break feed forward
path and hence one possible way is to put a resistor. Lets back to design
part From the desired phase margin, have to choose the minimum value
for Cc, i.e. for a 60 phase margin we use the following relationship. This
assumes that he phase margin of 60 (good stability) consider
Cc >= 0.22 CL = 2.2 pf
Now slew rate SR = ( I5/Cc )
For a differential amplifier
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I1= I2 = I5/2
We see that for a mos transistor in saturation region
1+ ds
1 w )
Ids= ' n
2 ( )
l
[ V gs V t ] 2
From this we have

2 I ds
V gs=V t +
w
' ( )
l
From the circuit of two stage op amp we have
V min (ve )=V ss+V Dsat 5+V GS 1
( )
2I1
V min =V SS +V T 1max +V Dsat 5 +
W
5
L
Similarly
( )
2I3
V max =V DD V T 03 max + V Tmin
W
3
L
W I5
( )=
L 3 [V V
n DD inmax V 3 +V Tpmin ]
Because of symmetry
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W W I5
( ) ( ) =
L 3 L 4 [V V
n DD inmax V 3 +V Tpmin ]
Just Cheak weather the pole has value >> GB so that it has no role in
stability we have to calculate pole as

gm 3
P3=
2 c gs 3
gm1 gm2
We know GBW= =
2 cc 2 cc
W W g2m 1
( ) ( ) =
L 1 L 2 2 n I1
From the expression of V min we get
( )
2 I1
V Dsat 5=V SS V T 1 max +V min
W
5
L
Since M5 in saturation region
W
L

V
[ Dsat 5]2
1
I Dsat 5= n
1
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W
L

That gives V
[ Dsat 5] 2
n

From the phase margin M =60 we have obtained an expression as
gm 6 >10 gm 2 or gm 6 10 gm 1
Since M3 is always in saturation region , so M3 gate always connected to
drain of M3
V ds 3=V gs3=V gs 4
But V sg 3=V sg6
2I6
+ V T 6
6
Therefore 2 I3
+ V T 3 =
3

Since M3 and M6 are p- channel devices so

W
L

I 3 I6
=
3 6 or 6

W
( )
L 3

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W
L I6 W
Or ( )
I4 L 4

()
2I7
L V min =V Dsat 7 =
Similarly and W
n 7
L

Finally we get the gain equation as
gm1
g
(gds 2 +gds 4 ) m 6
A v 0=
( g m 6+g m 7)
3.7 Bandgap Reference - Opamp with 1V power supply
Implementing an Opamp with 1V power supply is challenging. The
Opamp is implemented as shown in fig.6. The input stage makes use of
depletion mode PMOS transistors, in order to cope with the power supply
voltage reduction. So, this solution makes the circuit not useful for
standard, low-cost CMOS technologies, where such special devices are
rarely available or precisely modeled. The differential amplifier used in
the Op amp in fig.6 makes use of a MOS depletion differential pair to
accommodate a common mode voltage as low as Vf. However, the use of
special devices is not convenient due to the higher costs related to the
further process steps and to device characterization and modeling. A
general purpose architecture should make use of devices available in
conventional CMOS technologies. Keeping these things in mind, two
other implementations of the opamp were developed. Reference voltage
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generators with low sensitivity to the temperature and supply are
commonly required both in analog and digital circuits. Since the
conventional implementation of the bandgap voltage reference provides
an output voltage almost equal to the silicon energy gap, measured in
electron volts, it cannot be used in the latest deep-submicron
technologies whose supply voltage is already in the 1-V range. A recently
designed current-mode (CM) realization of the bandgap reference in
CMOS technology has the potential of circumventing the supply-voltage
limitation.
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CHAPTER 4
SIMULATION RESULTS
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4.1 Opamp
The opamp is simulated using cadence virtuoso tool and the
implemented in 90nm standard CMOS technology with supply voltages
as Vdd = 1 V and Vss = -1 V
4.1.1 Implemented Opamp
Figure 14 Implemented 2 stage cmos Opmap
Table.1 shows the chosen values w and l of the components in
Opamp circuit. Large channel lengths are used to decrease the sensitivity
to process variations and lithography errors.
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Table 1 Dimensions of the proposed opamp
Component Parameter
PM0 , PM3 W=27.27um, L=360nm
PM4 , PM5 W=40um, L=5um
PM1 W=4.59um, L=360nm
PM2 W=6.48um/ L=360nm
NM2 , NM3 W=990nm, L=990nm
NM1 W=1.16um, L=355nm
NM0 W=460nm, L=1.2um
4.1.2 Opamp testing
Figure 15 Testing Opmap with symbol
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4.1.3 opamp waveforms
Figure 16 Opamp gain and phase plot
4.1.4 Simulation results
Result value
Bias current 30uA
Cc 100 fF
Open loop gain( A) 70dB
Phase margin 55
Unity gain band width 60MHz
Table 2 Simulation results of the proposed opamp
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4.2 Bandgap circuit

The proposed Bandgap reference using bipolar technology works as
explained in chapter 2 generating an output voltage of 0.9mV .Every BGR
presents a balanced sum of two voltages with opposite temperature
coefficient to achieve a good temperature performance. As already
explained, the most common voltages used in this addition are the VBE
and VTH produced by means of parasitic BJTs. The Bandgap Reference
(BGR) implements this concept through the architecture depicted in
below figure.
4.2.1 Implemented BGR
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Figure 17 Implemented CMOS bandgap reference
This BGR design is implemented in a 90nm CMOS technology
shown in FGURE 17. In order to obtain low voltage and low power
operation, all MOS transistors are designed to operate in weak/moderate
inversion. Threshold voltages of the PMOS and NMOS transistors in the
process used are -0.19 V and 0.16 V respectively. The transistor and BJT
sizes along with resistor values of implemented BGR given in table 3.
Table 3 dimensions of the proposed BGR
Component Value
MP0, MP2, MP3, MP4, MP5, MP6, W=6 um and L=12 um
MP7, MP14
MP1, MP8, MP9, MP10, MP11, W=40 um and L=4 um
MP12, MP13, MP15
Q1,Q2,Q4,Q5,Q6 Vert10=100 um2 (area)
Q3 20 * Vert10
R1 42.7K ohm
R2 1K ohm
R3 333K ohm
R4 202.6K ohm
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R5 1M ohm
4.2.2 BGR waveforms
The temperature dependence of the implemented bandgap
reference was shown below. The variation of the bandgap voltage varies
from 994mV to 997mV in between the temperature range of -50 0C to
1500C
Temperature vs. reference voltage
Figure 18 Temperature dependence of the Bandgap reference voltage
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Noise analysis
Figure 19 Noise spectrum of the proposed bandgap reference
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Supply voltage vs. reference voltage
Figure 20 reference
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CONCLUSION
In this thesis work the detail study of operational amplifier design
was studied and implemented according to our requirement. Later
different types of bandgap reference methods discussed and finally
bandgap voltage references implemented as it is independent of
temperature, power supply and noise. The total design of bandgap
reference circuits was done here by using CADENCE tool in 90nm cmos
technology.
Future work:
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The present implemented circuit has some drawback (less
variation) with process parameters and would certainly need to have a
constant reference implementation.
APPENDIX
Cadence: Virtuoso Analog Design Environment
Introduction
Cadence is an Electronic Design Automation (EDA) environment which
allows different applications and tools to integrate into a single
framework thus allowing to support all the stages of IC design and
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verification from a single environment. These tools are completely
general, supporting different fabrication technologies.
The various Design steps:
Firstly a schematic view of the circuit is created using the Cadence
Composer Schematic Editor. Alternatively, a text netlist input can be
employed.
Then, the circuit is simulated using the Cadence Affirma analog
simulation environment. Different simulators can be employed, some
sold with the Cadence software (e.g.,Spectre)some from other vendors
(e.g., HSPICE) if they are installed and licensed.
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Once circuit specifications are fulfilled in simulation, the circuit
layout is created using the Virtuoso Layout Editor. The resulting layout
must verify some geometric rules dependent on the technology (design
rules). For enforcing it, a Design Rule Check (DRC) is performed.
Then, the layout should be compared to the circuit schematic to
ensure that the intended functionality is implemented. This can be done
with a Layout Versus Schematic (LVS) check.
All these verification tools are included in the Diva software in
Cadence (more powerful Cadence tools can also be available, like
Dracula, or Assura in deep submicron technologies).
Finally, a net list including all layout parasitic should be extracted,
and a final simulation of this netlist should be made. This is called a Post
Layout simulation, and is performed with the same Cadence simulation
tools. Once verified the layout functionality, the final layout is converted
to a certain standard file format depending on the foundry (GDSII, CIF,
etc.) using the Cadence conversion tools. The Summary of the design
steps is again explained with an inverter example as follows.
1. Invoking Cadence tool
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The command Interpreter Window can be invoked by typing icfb&
The tool is available on vlsi34, vlsi35, vlsi36, vlsi27. The following window
will appear on the screen on invoking the command.
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2. Create Library
In order to create the library go to Tools > Library Manager on the
Tools menu of the CIW.
Now to create a new library go to File > New > Library from the File menu
of the Library Manager.
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Then fill in the name of the new library. Click OK. The following figure
appears
Now click on Attach to an existing techfile as shown
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Now the library you created should appear in the Library Manager
window.
3. Create Schematic
Start by clicking on the library (created by you) in the Library
Manager window, then go to File > New > Cell View and fill in with
Inverter ( in this case) as the cell name, schematic as the view name, and
Composer Schematic as the tool, then press OK.
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An empty Window appears as next figure.
Placing the Intances
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Click on the Instance Icon and then click the Browse button in the
form to open Libraries browse window.
Select the following:
Under the Library column, select tsmc35mm.

Under Cell, nch.( for nmos)
Under View, select symbol
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You can edit the properties of the instance when the above figure appears
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Now Click on the Schematic window to place an instance as shown below
Similarly you can place pmos. You can press the ESC key on the
keyboard to get out of the place instance mode or you can keep placing
other parts.
Adding the I/O Pins
In the lower left side of the Composer window click on the Pin icon.
Add the input and output pins, shown as following. Under Pin Names,
type In or Out or any other name. Note that Direction in the form reads
input or output.
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Adding Wires
On the left side of the Composer window click on the Wire icon. Now
click on the schematic from where you want to draw the wire and click
on the point where you want to finish the wire. The final schematic
should look somewhat like this
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Now you need to Check and Save your design (either the top left
button or Design > Check and Save). Make sure you look at the CIW
window and there are no errors or warnings, if there are any you have to
go back and fix them Assuming there are no errors we are now ready to
start simulation.
4. Simulation
In the Virtuoso Schematic window go to Tools > Analog Environment.
There is going to another "What's New" popup window that you can read
and close or minimize. The design should be set to the right Library, Cell
and View. The window appears as shown below.
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Choosing a Simulation Engine
In the Simulation window, select Setup Simulator/Directory/Host
Choose the Simulator cyclic field is reading Spectre
85
Reference Circuits
Choosing the Analyses
In the Affirma Analog Circuit Design Environment window, click
Analysis Choose pull down menu to open the analyses window. Several
analyses modes are set up.
Transient Analysis
In the Analysis Section, select tran and set the Stop Time and Before
Clicking OK button, click APPLY button.
86
Reference Circuits
Saving and Plotting Simulation Data
Select Output > to be Plotted >Select on Schematic to select nodes to
be plotted. By clicking on the wire on the schematic window to select
voltage node, and by clicking on the terminals to select currents Select
the input and output wires in the circuit. Observe the simulation window
as the wires get added.
Running the Simulation
Click on the Run Simulation icon. When it complete, the plots are
shown automatically.
87
Reference Circuits
REFERENCES
[1] Ramanarayana Reddy Sanikommu Design and implementation of

bandgap reference circuits, Master thesis, Report number: LITH-
ISY-EX-3728-2005 Linkping, 13th June, 2005.
[2] Charalambos M. Andreou, Savvas Koudounas, and Julius

Georgiou, A Novel wide-temperature - range, 3.9 ppm/ C CMOS
Bandgap Reference Circuit, IEEE J. Solid-State Circuits , vol. 47,
no. 2, February 2012.
[3] Sayan Bandyopadhyay, Deep Mukherjee, and Rajdeep Chatterjee ,

Design Of Two Stage CMOS Operational Amplifier in 180nm
Technology With Low Power and High CMRR, Int. J. of Recent
Trends in Engineering & Technology, Vol. 11, June 2014.
[4] Arun N.Chandorkar Department of Electrical Engineering Indian

Institute of Technology, Bombay, mixed signal vlsi design a tutorial
on design of a two stage opamp, PPT, 16th March 2009.
[5] A.Pierazzi, A.Boni and C.Morandi " Band-gap references for near 1-
V operation in standard CMOS technology " Proc. of the Custom
Integrated Circuits Conference, 2001, pp.463-466.
[6] B.Razavi " Design of Analog CMOS Integrated Circuits ", McGraw-
Hill Education ,Singapore, 2001.
[6] Amana Yadav, Design of Two-Stage CMOS Op-Amp and Analyze the
Effect of Scaling, International Journal of Engineering Research and
Applications (IJERA), Vol. 2, Issue 5, September- October 2012,
pp.647-654.
88
Reference Circuits
[7 ] Mehul Garg et al Int. Journal of Engineering Research and

Applications ISSN : 2248-9622, Vol. 4, Issue 7( Version 1), July
2014, pp.64-67 .
[8] A. Paul brokaw, A Simple Three-Terminal IC Bandgap Reference,

J. Solid-State Circuits ,vol.sc-9,no. 6, December 1974.
[9] https://www.youtube.com/watch?v=wJz6claEGa0.
89

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Implementation of Bandgap

We would like to extend our heartfelt gratitude to those individuals

Firstly, we would like to thank our guide Mr. G. Shiva Kumar,

Assistant Professor, Department of Electronics and Communication

Engineering who supported us a lot in successfully completing our

We would like to thank the Head of the Department Dr. K.

Manjunatha chari, for encouraging us and giving a due support in our

and willingness to share his vast knowledge, made us understand this

project and its manifestations in great depths and helped us to complete

the assigned tasks.

We would also thank our Institution and my faculty members

without whom this project would have been a distant reality.

their encouragement and support.

In the design of analog integrated circuits its important to create

reference voltages and currents with well defined values. Bandgap

reference circuits are regularly used to achieve it on-chip. Especially in

analog to digital conversion, where the input voltage is compared to

several reference levels in order to determine the corresponding digital

value, a best application is this bandgap reference voltages. The main

intention in this project work is to understand the performance

limitations as well as the design of a bandgap reference circuit, BGR.

In this project work we studied the different types of bandgap

reference types and bandgap circuits. Then a detailed analysis of Opamp

design was studied. Finally the BGR circuit which is capable of

producing an constant output reference voltage for given supply voltage

was implemented .The tool used is CADENCE for schematic simulation

and all of these circuits are implemented in 90nm CMOS technology.

1.1.Introduction to bandgap reference circuits.....................................1

1.2 Zener diode references....................................................................3

1.3 Enhancement and depletion reference............................................4

1.4 Bandgap reference approach..........................................................6

1.5 Comparison of the three reference approaches...............................9

STUDY OF BGR CIRCUITS....................................................................10

2.2 Major Bandgap Dependencies......................................................11

2.2.1 Process variations..................................................................11

2.2.2 Power supply..........................................................................11

2.3 Current summing approach.........................................................12

2.4 Voltage summing approach..........................................................13

2.5 A Simple Three-Terminal IC Bandgap Reference...........................14

2.5.1 Limitations of this circuit.......................................................19

2.6 CMOS Bandgap Reference Circuit................................................20

2.7 Basic bandgap design considerations...........................................22

2.7.1 Traditional Bandgap...............................................................22

2.7.2 Basic Bandgap Considerations...............................................22

2.8 BGR and process parameters relation.........................................24

3.2 Impact of op-amp in cmos bandgap references.............................28

3.3 Basic CMOS Op-Amp...................................................................29

3.3.1 Input differential amplifier......................................................31

3.3.3 Bias circuit.............................................................................32

3.4 Characteristic features of op-amp.................................................32

3.4.1 Open loop gain..........................................................................32

3.4.2 Common mode gain................................................................32

3.4.3 Common mode rejection ratio.................................................32

3.4.4 Slew rate................................................................................33

3.4.5 Input common mode voltage range.........................................33

3.4.6 Unity gain bandwidth.............................................................33

3.5 Design Of Two Stage CMOS Operational Amplifier........................33

3.5.1 Steps in designing a cmos Opamp..........................................33

3.5.2 Some practical thoughts on op amp design............................34

3.6 Design strategy of op-amp............................................................35

3.6.1 Dual input Differential Amplifier............................................36

3.6.2 Bias String.............................................................................36

3.6.3 Output Buffer.........................................................................36