Lab4

1. Implement pre-lab1.
Input: clk, rst
Output: [7:0] a
Block Diagram:

Implementation:
Lab3 1Hz 1Hz
Shifter Flip-flop clock<= Verilog Code
Shifter

Discussion:
prelab FPGA
input output

rst = 0, 2n 2n+1
2. Construct a ring counter similar to that of pre-lab1 but the initial value of the
DFFs can be set randomly.

Input: clk, rst, [7:0] random

Output: [7:0] a
Block Diagram:

Implementation:
flip-flop rst = 0
rst = 0 a <= random
random
Discussion:

3. Use the idea from pre-lab1. We can do something on the seven-segment display.
Assume we have the pattern of E, H, N, T, U for seven-segment display as shown
below. Try to implement the scrolling pre-stored pattern NTHUEE with the four
seven-segment displays.

Input: rst, clk

Output: [3:0] ssd_ctl, [7:0] segs
Block Diagram:

Implementation:
frequency divider, shifter, scan control, display modules
frequency divider outputs shifter
(1Hz) output scan control
4 shifter

outputs [3:0] a[1:0] b[3:0] a

scan control display
decoder shifter binary

Discussion:
block diagram
verilog code output
input block diagram
shifter flip-flop <= =
nnTnnn