NATIONAL INSTITUTE OF TECHNOLOGY

JAMSHEDPUR
SPRING SEMESTER 2016-17
Department of Computer Science and Engineering
TEST-1
Course Code: CS602 (6th Sem) Course Title: Advanced Computer Architecture

Date: 20/02/2017 Course Instructor: Ansuman Mahapatra

Duration: 1 Hour Max. Marks: 20

All Questions are compulsory. Assume any missing data.

1. The simplest predictor to reduce branch penalties is the Not-taken predictor which predicts not-
taken every time. Why we dont use a Taken predictor instead? [1]
Book
2. How number of bits utilized for a 4 bit history predictor? [1]
Check class copy
3. What is the speed up with 8 processors if 80% of the application is parallelizable. Assume for
each processor added, the communication overhead is 0.5% of the original execution time.
[2]
Book Exercise Instructions Issue Dispatch Write
4. What is the LD F6, (0)R2 disadvantages of 1 bit, 2 bit
predictor. What is MUL F2, F0, the advantage of history
predictors. [2] F1
Check class copy ADD F6, F2,
5. What is the F6 difference between
Tournament and ADD F6, F2, Hierarchical predictor?
Explain with F6 diagram. [2]
Check class copy ADD F1, F1,
6. Use Tomasulos algorithm to compute in
F1
which cycle the ADD F1, F3, following instructions will
be issued, F4 dispatched and write their
result. Fill the table below with number of
cycles. Assume latency for LD 1 cycle, ADD 1 cycle, MUL 5 cycles. There are 2 ADD, 1 LD,
and 1 MUL reservation station available. Assume that we cant do issue - dispatch, capture -
dispatch and reservation station free - allocation in the same cycle. Assume unlimited ALUs
available.
Instructions Issue Execute Write Commit
DIV R2, R3, R4 [6]
Check class MUL R1, R5, R6 example
7. Use reorder ADD R3, R7, R8 buffer to compute in
which cycle MUL R1, R1, R2 the following set of
instructions SUB R4, R3, R5 will be issued, start
ADD R1, R4, R2
executing, write result and commit. Assume latency for ADD 1 cycle, MUL 3 cycles, DIV 10
cycles. Assume 3 ADD/SUB and 2 MUL/DIV reservation stations with unlimited ALUs available
and all operations on instructions are done in separate cycles. [6]
Check class example

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