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INTRODUCTION
This regulator is recommended to bias a two stage, grounded source GaAs FET LNA with constant drain currents1. With
minor modification, two additonal bias stages could be added to this circuit.
SPECIFICATIONS
CIRCUIT DIAGRAM
+ 15V 2N3643
DUAL
_ 15V
+
.01F .01F
2.2K 6.8V
100K 100K
5.6K
CIRCUIT OPERATION
When the 15 volt power supply is turned on, integrator A1 ramps on which allows VDS and -VGS voltages to also ramp on. The
drain to source voltage (VDS) is a constant voltage, which is adjusted by the variable resistor R1. The constant drain current (ID)
is maintained by the comparator A2 and is adjusted by R2 for stage one and R3 for stage two. Nodal voltages are shown in the
circuits Of IDl = 10mA and ID2 = 20mA. The resistance values for the above conditions are R2 = 350 and R3 = 10.
AN80901
100K
100K 100K
D1 D2 G1 6.8V
A1 G2
A2 2.2K 100K 4.3K
2N
1.50" 10K
3643
330
330
747
747
100K
4.3K
1 1
100K
500 500
.01
V+ V
COM 3.3K
6.8V
3.25"
Actual Size
REFERENCE
1. D. Lane, Smart Bias Supply for Delicate MW Transistors, Microwave Journal, June 1978, pp. 126-142.