What is design flow for VHDL?

What is entity,architecture,package,configuration,driver,bus,attribute,generic,process?
What do you mean by HDLs?
What is VLSI Design?
What is VHDL? What are capabilities of VHDL?
What can be the various uses of VHDL?
What are the various levels of abstractions in VLSI design?
What is the difference between Entity and Architecture?
Explain various types of Modelling styles?
Explain various types of delays in VHDL?
What are Generics?
What is the difference between STD_LOGIC and BIT types?
What is the difference between Concurrent & Sequential Statements?
Discuss process and wait statements? Can they be used simultaneously
in the program?
What is the difference between Signal and the Variable?
What are VHDL Subtypes?
What is Synthesis?