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Assembly language
Appendix A
Contract between software and hardware
Software portability
Hardware flexibility
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Accumulator Register-Memory
The accumulator provides an
implicit input, and is the There is no implicit operand
implicit place to store the One input operand is
result. register, and one in memory
Ex. C = A + B Ex. C = A + B
Load R1, A
Load A Add R3, R1, B
Add B Store R3, C
Store C Processors include VAX,
x86
Used before 1980
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Variants of GPR Architecture How Many Registers?
Number of operands in ALU instructions: two or If the number of registers increase:
three
Add R1, R2, R3 Add R1, R2 Allocating more variables in registers (fast accesses)
Maximal number of memory operands in ALU Reducing code spill
instructions: zero, one, two, or three Reducing memory traffic
Load R1, A Load R1, A
Load R2, B Add R3, R1, B Longer register specifiers (difficult encoding)
Add R3, R1, R2 Increasing register access time (physical registers)
Three popular combinations More registers to save in context switch
register-register (load-store): 0 memory, 3 operands
register-memory: 1 memory, 2 operands
MIPS64: 32 general-purpose registers
memory-memory: 2 memories, 2 operands; or 3 memories, 3
operands
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11 12
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Little or Big: Where to Start? Addressing Modes
Register ADD R16, R8
Byte ordering: Where Number 0x5678 Immediate ADD R17, #100
is the first byte?
Little-endian Big-endian Displacement ADD R2, (100)R1
Big-endian: IBM, Direct (absolute) ADD R1, (1000)
SPARC, Motorola
Register indirect SUB R2, (R1)
Little-endian: Intel, DEC Indexed ADD R1, (R2 + R3)
Supporting both: MIPS, Scaled SUB R2, 100(R2)[R3]
PowerPC Autoincrement ADD R1, (R2)+
00000003 5 8
Issue: when they 00000002 6 7 Autodecrement SUB R2, -(R1)
exchange data 00000001 7 6 Memory indirect ADD R1, @(R3)
00000000 8 5 (see textbook pA-9)
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Instructions for Control Flow Issues in Control Flow
Conditional branch: change control flow based on a
Instructions
condition Memory addressing modes
Jump: unconditional change of control flow How to specify addresses to transfer
Procedure call Can be either PC-relative or register indirect
Procedure return Conditional branch options
What kind of conditions can be directly used
When and how to evaluate conditions
How to link branch instructions with conditions
Procedure invocation options
When to save and restore register contents
When to save global variables
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d
Fewer bits in displacement
With position independence
e.g. loop
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Register Indirect Conditional Branch
Conditional code
Jump or branch to an address stored in a
Test special bits set by ALU operations
+ Sometimes condition is set for free
register
- CC is extra state, constraint on inst order
80x86, ARM, PowerPC, SPARC, SuperH
Condition register
Used for programming language with Test register (result of comparison)
+ Simple
Case or switch statements - Use up a register
Alpha, MIPS
Virtual function or methods Compare and branch
Compare is part of the branch
Function pointers
+ One inst for a branch
- Too much for the branch inst
Dynamically shared libraries
PA-RISC, VAX
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Encoding Instruction Set Conflicting Desires
address address address
operation Encoding more registers and addressing
field 1 field 2 field 3
modes
Compiler needs, DSP needs, etc.
What to encode
Operation (opcode) Reducing size of instruction (program)
Address field (for operands)
Facilitating pipelining
Address specifier (for addressing modes) Align to byte boundary
Only for ISA with complex addressing modes Prefer fixed length
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Compression
IBM CodePack (full-size inst. in cache, compressed
inst. in main memory, disk)
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MIPS ISA MIPS Addressing Modes
Register
Registers
DADDU R4, R2, R1
32 GPRs (integer registers) Immediate
DADDIU R4, R2, #3
R0, R1, , R31
Displacement
32 FPRs (floating-point registers) LW R4, 100(R1)
Register indirect
F0, F1, , F31 Place 0 as displacement
A few special registers
LW R4, 0(R1)
Absolute
e.g. FP status register Use R0 as base register (R0 is always 0)
LW R4, 100(R0)
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31 32
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MIPS R-type Instructions R-type Example
op rs rt rd shamt funct op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
rd: destination register number 000000 10001 10010 01000 00000 100000
shamt: shift amount
000000100011001001000000001000002 = 0232402016
funct: function code (extends opcode)
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