H O M E WO R K P RO B L E M A N S W E R S

Chapter 1

1.1-1. Base-10 value 5 13/16

vout G1(G2 2 gm1)

1.1-4. 5
vin G1G2 1 G1G4 1 G2G4 1 G3G2 1 G3G4 1 G2gm1

vout R3R4(1 2 gm R2)

1.1-5. 5
vin R1 R2 1 R1R4 1 R1R3 1 R2R3 1 R3R4 1 gmR1R3R4

iout 2rmR1/R3
1.1-6. 5
iin R 1 R1 2 rm

v2 gmRL v1 1
1.1-7. 5 5 RL 1
v1 1 1 gmRL i1 gm

vout 2R2
1.1-8. 5
vin R1

vout 2rmR3
1.1-9. 5
vin R1R2 1 R1R3 1 R1rm 1 R2R3

vout 2gmR1R2R3
1.1-10. 5
vin R1 1 R2 1 R3 1 gmR1R3

R1R2R4 1 R2R3R4 1 R1R3R4

1.1-11. Z0 5
R1R2 1 R2R3 1 R3R4 1 R1R4 1 R1R3 1 gmR1R3R4

1.1-12. Rin 5 5 M

727
728 HOMEWORK PROBLEM ANSWERS

Chapter 2

2.2-1. NA 5 5 3 1015/cm3, ND 5 1020/cm3

o 5 0.9168
xn 5 43.5 3 10212 m
xp 5 20.869 mm
xd 5 0.869 mm
Cj 0 5 21.3 fF
Cj 5 11.94 fF

3e 1/3
2.2-3. xp 5 2xn 5 a b (0 2 VD)1/3
2qa
2.2-5. BV h 58.27 volts

2.2-6. vD 5 vD1 2 vD2 5 59.6 mV

2.3-2. VT 5 0.736 volts

v2DS
c (vGS 2 VT0) vDS 2 (1 1 a) d
WnCox
2.3-3. iD 5
L 2
2.3-5. For tox 5 210 : VT0 5 0.331 V
For tox 5 200 : VT0 5 0.306 V (Example. 2.3-1 result)
The difference is 25 mV.

2.3-6. VT0 5 0.6496 V;  5 0.882 V1/2

2.4-2. (a) AR 5 252 3 25 m2 5 6308 m2 and AC 5 6308 m2

Also Rpoly 5 R 5 252 3 50  5 12.6 k and CMOS 5 6308 m2 3 2 fF/m2 5 12.6 pF

1
(b) Maximum 23dB frequency 5 5 1.6MHz
2(0.7)(12.6k)(0.9)(12.6pF)
1
Minimum 23dB frequency 5 5 0.7MHz
2(1.3)(12.6k)(1.1)(12.6pF)
2.4-5. VOUT 5 1.22713 V

2.4-6. VOUT 5 1.2398 V

2.4-8. R 5 150 

1 dvD
2.5-1. 5 2.775 3 1023
vD dT
 Chapter 3 729

A-2. C 5 CAREA (d 6 0.05)2

where d is one (both) sides of the square capacitor
d 5 200.1

Chapter 3

W
3.1-5. iD 5 K (vGS 2 VT)2[1 1 (vDS 2 vDS (sat))], 0 , (vGS 2 VT) # vDS
2L
3.2-1. Off: CGB 5 11.3 fF, CGS 5 1.1 fF, and CGD 5 1.1 fF
Saturation: CGB 5 0.575 fF, CGS 5 7.868 fF, and CGD 5 1.1 fF
Nonsaturation: CGB 5 0.574 fF, CGS 5 6.18 fF, and CGD 5 6.18 fF
3.2-2. NMOS: CBX(0) 5 5.2 fF and CBX(20.75 V) 5 4.07 fF
PMOS: CBX(0) 5 4.31 fF and CBX(10.75 V) 5 3.425 fF
3.2-3. The device is in saturation; therefore, CGB 5 0.575 fF, CGS 5 7.868 fF, and CGD 5 1.1 fF.
3.2-4. (a) RD 5 RS 5 7.95 V 1 0.2 V 5 8.15 V, (b) CBD 5 CBS 5 176 fF, (c) W 5 22 m and L
5 2 m, and (d) CGD 5 4.8 fF
3.2-5. |p1| 5 835.7 kHz
vout(s) 1
3.3-1. 5
vin(s) s
11
13.77 3 109
3.3-2. WM2 5 592 m
3.3-3. Example 3.3-1, NMOS: gm 5 332 S, gmbs 5 40.4 S, and gds 5 0.5 S
Example 3.3-1, PMOS: gm 5 224 S, gmbs 5 38.2 S, and gds 5 0.5 S
Example 3.3-2, NMOS: gm 5 1.1 mS, gmbs 5 134 S, and gds 5 3.28 mS
Example 3.3-2, PMOS: gm 5 500 S, gmbs 5 85.2 S, and gds 5 1.428 mS
3.3-4. gm 5 1.12 mS, gmbs 5 136 S, gds 5 0.0228 S, CGB 5 0.575 fF, CGS 5 15.8 fF, and CGD 5
2.2 fF
1
3.3-5. ID(TOTAL) 5 (vGS 2 vT)2 (1 1 vDS)[
Wi]
L
i
3.3-6. LEQUIVALENT 5 o0 Li

3.5-1. von 5 82.67 mV

ID
5 a bIDO exp a b5
W 1 vGS ID
3.5-2. gm 5
VGS L n(kT/q) n(kT/q) n(kT/q)
730 HOMEWORK PROBLEM ANSWERS

W
3.5-3. ID 5 2K [n(kT/q)]2
L
3.6-1. Part (a)
Problem 3.6-1 (a)
M1 2 1 0 0 nch W=1u L=1u
M2 2 3 4 4 pch w=1u L=1u
M3 3 3 4 4 pch w=1u L=1u
R1 3 0 50k
Vin 1 0 dc 1
Vdd 4 0 dc 5
.MODEL nch NMOS VTO=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
.MODEL pch PMOS VTO=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
.op
.end

Part (b)
Problem 3.6-1 (b)
M1 2 1 0 0 nch W=1u L=1u
M2 2 3 4 4 pch w=1u L=1u M=2
M3 3 3 4 4 pch w=1u L=1u
R1 3 0 50k
Vin 1 0 dc 1
Vdd 4 0 dc 5
.MODEL nch NMOS VTO=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
.MODEL pch PMOS VTO=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
.op
.end

Chapter 4

4.1-2. VS (volts) R (ohms)

1.0 1460
3.0 5253
5.0 infinity
 Chapter 4 731

4.1-3. Vs (volts) R (ohms)

1.0 infinity
3.0 2694
5.0 1163
4.1-4. Vs (volts) R (ohms), parallel
1.0 1460
3.0 1781
5.0 1163
4.1-5. W/L 5 2.64
4.1-6. f(23 dB) 5 8.44 3 106 Hz
4.1-7. Vout(t1) 5 1.777 V
4.1-8. t 5 124.3 ps
4.1-9. f1 must increase.
4.1-10. Reducing the magnitude does not affect the result of feedthrough in the slow regime.
Decreasing the magnitude does affect the accuracy.
4.1-11. Case 1: Vout(t1) 5 1.967 V and Case 2: Vout(t1) 5 1.984 V

L2COX(5 2 VS 2 VT) 21
4.1-12. W2 5 W1 a2 1 b
CGDO (VS 1 VT)
Design L2 to be the minimum allowed device length and calculate W2.
4.1-13. Error due to charge injection is 116 V.
4.1-14. RON 5 1606 ohms. Loss 5 28.32dB. The bridge switch dissipates more power, has higher
ON resistance, and couples more signal during the OFF phase than the single switch.
1
4.2-1. RAB 5 In general, for the same-size transistors, Fig. P4.2-1 will be more linear
2(VC 2 VT)
than Fig. 4.2-3.

4.3-1. rout 5 21.7 3 106 ohms

4.3-2. W1/L1 5 1/22
4.3-3. Vout(min) 5 3.02 V. For the circuit in Problem 4.3-2, the minimum output voltage is lower
than the circuit in Problem 4.3-1 and is thus generally a better choice.
4.3-4. Vout(min) 5 1.082 V and rout 5 764 3 106 ohms. From the SPICE results, Iout 5 10.157 A.
4.3-5. Vout(min) 5 0.3868 V and rout 5 717 3 106 ohms. From the SPICE results, Iout 5 8.185 A.
4.3-6. W4/L4 5 1/2 and W3/L3 5 2/1
4.3-7. SPICE results give Iout 5 10.233 A. Notice that the output current is more accurate than that
simulated in Problem 4.3-5. This is because M3 and M1 have more closely matched terminal
conditions.
732 HOMEWORK PROBLEM ANSWERS

4.3-8. Rout 5 2rds1 assuming gm > gds > (1/R)

4.3-9. VBias(min) 5 1.553 V, Vmin 5 0.306 V, and Rout < 29.31 MV
4.4-1. iO(min) 5 27.82 A and iO(max) 5 56.93 A
4.4-2. vOUT 5 691 V
4.5-2. VREF 5 VT1
4.5-3. IREF(min) 5 3.81 3 1026 and IREF(max) 5 21.3 3 1026

1 2iD 1 1
4.5-4. Iout 5 I 5 2
R E K E (W/L)1 E (W/L)2

4.5-5. (a) rout < 1/gm. (b) rout < 1/gm.

VREF
4.5-6. S 5 0.0965
VDD
4.6-1. R1 5 59.64 kV and R2 5 732 kV. Stacking bipolar transistors reduces sensitivity to amplifi-
er offset.
4.6-2. The other end of the capacitor should be connected to VDD.
4.6-3. VREF 5 1.169 V
4.6-4. R2 5 47.95 kV and VREF 5 1.262 V
4.6-5. Assuming the technology is p-substrate with a deep n-well, Fig. 4.6-8(a) will have much less
current injected into the substrate than Fig. 4.6-8(b).
4.6-6. R1 5 1 kV, R2 5 11.04 kV, and R3 5 8.748 kV
W23 W24 W25
4.6-7. 5 0.4770, 5 1.8276, and 5 0.6933. The value of the resistors is arbitrary.
W18 W3 W8
4.6-8. R1 5 29.93 kV, R2 5 299.3 kV, and R4 5 3825 V

Chapter 5

5.1-1. vout(max) 5 5 V and vout(min) 5 0.5 V

5.1-2. Vout(min) 5 0.183 V
5.1-3. 2/1 5 0.306 and Av 5 21.8 V/V
5.1-4. Vin 5 1.303 V, Av 5 22.345 V/V, and Rout 5 7.07 kV
5.1-5. vOUT(max) 5 4.3 V, Av 5 21.972 V/V, Rout 5 13.296 kV, z1 5 47.2 GHz, and p1 5 11.71 MHz
5.1-6. Vin 5 1.7 V, Av 5 26.95 V/V, and Rout 5 31.6 kV
 Chapter 5 733

5.1-7. Active load inverter: Rout 5 14.14 kV, Av 5 22.097 V/V, and f23dB 5 10.9 MHz
Current source inverter: Rout 5 222.22 kV, Av 5 232.93 V/V, and f23dB 5 0.697 MHz
Pushpull inverter: Rout 5 222.22 kV, Av 5 248.63 V/V, and f23dB 5 0.697 MHz
5.1-8. Av 5 2170.9 V/V (ID 5 0.1 A), Av 5 270.27 V/V (ID 5 5 A), and Av 5 215.71 V/V (ID 5 100 A)
5.1-9. VGG 5 2.05 V, Vin 5 3.406 V, Av 5 224.85 V/V, and f23dB 5 2.51 MHz
5.1-10. f23dB 5 1.102 MHz, e
ni 5 6.277 nV/ 2Hz

5.1-11. (a) Circuit 5 has the highest gain. (b) Circuit 4 has the lowest gain (assuming normal values
of gm/gmb). (c) Circuits 5 and 6 have the highest output resistance. (d) Circuit 1 has the low-
est output resistance.
5.1-12. Av 5 243.63 V/V, and f23dB 5 283.36 kHz
5.1-13. Active area of active load inverter 5 4546 m2, active area of current source load inverter 5
4.64 m2, and active area of pushpull load inverter 5 2.55 m2.
5.1-14. Av 5 243.63 V/V, Rout 5 55.55 kV, and f23dB 5 286.5 kHz
5.2-1. (a) gm 5 104.8 S and Av 5 23.31 V/V. (b) gm 5 331.4 S and Av 5 36.82 V/V.
5.2-2. (a) gm 5 70.71 S and Av 5 15.7 V/V. (b) gm 5 223.6 S and Av 5 24.84 V/V.

IDD IDD
5.2-3. VIC (max) 5 VDD 2 ZVT1Z 2 2
E KP(W1/L1) E KP(W5/L5)

IDD
VIC(min) 5 VSS 2 ZVT1Z 1 VT3 1
E KP(W1/L1)
5.2-4. VIC(max) 5 4.86 V, VIC(min) 5 0.93 V, and ICMR 5 3.93 V
5.2-5. Av 5 233.1 V/V, and f23dB 5 7.16 kHz
5.2-6. Rout 5 2.22 kV, Av 5 104.1 V/V, VIC(max) 5 2.184 V, and VIC(min) 5 1.2147 V
5.2-7. ISS 5 10 A: gmd 5 23.36 S and Av 5 249.69 V/V. ISS 5 1 A: gmd 5 7.07 S and Av 5
2157.11 V/V.
5.2-8. SR 5 0.1 V/s (ISS 5 10 A) and SR 5 0.01 V/s (ISS 5 1 A)
5.2-9. Avcm < 0.02 V/V
5.2-10. Av 5 0.74V/V
vo 1
5.2-11. 52 if gmrds >> 1
vic (gm32rds5)

ISS
5.2-12. VG1(max) 5 VDD 1 VT1 2 VT3 1
E KP(W/L)3

ISS 2ISS
VG1(min) 5 VT1 1 1
E K N (W/L)1 E K N (W/L)5
734 HOMEWORK PROBLEM ANSWERS

5.2-13. VOS(max) 5 0.18 V

5.2-14. VIC(min) 5 2.305 V, VIC(max) 5 3.282 V, and ICMR (worst case) 5 0.978 V

5.2-15. Circuit Rout vout/vin

1 gm1gm2 0.5gm2
1 5
gds2 1 gm8 1 gds8 (gm1 1 gm2)(gds8 1 gm8 1 gds8) gds2 1 gm8 1 gds8

1 gm1gm2 0.5gm2
2 5
gds2 1 gds8 (gm1 1 gm2)(gds2 1 gds8) gds2 1 gds8
1 gm1 1 gm2
3
gds2 1 gds8 2(gds2 1 gds8)
1 gm6 (gm1 1 gm2)gm6
4 5
gds6gds8 gds6 gds8 1 gm6gds2 2(gm6gds2 1 gds6gds8)
gds2 1
gm6
gm4gm6 (gm1 1 gm2)gm4gm6
5
gds2gm6gds4 1 gm6gds4gds8 2(gds2gm6gds4 1 gm6gds4gds8)

5.2-16. eeq 5 1.567 nV/ 2Hz and ito 5 164 fA/ 2Hz

gm1 a0.25 2 b
gds1
gm3
5.2-17. vs1 5 vid
a0.75gm1 1 gds1 a2 2 b 2 gds5 b
gm1
gm3
The value of vs1 is nonzero because the loads (M3 and M4) seen by the input transistors (M1
and M2) at their drains are different.
5.2-18. (a) v1(max) 5 2 V and v1(min) 5 0.9302 V. (b) ICMR 5 1.07 V. (c) Av 5 149.8 V/V. (d) f23dB
5 111.4 kHz.
gm1 2 2
5.2-19. e eq
2
5 4 e nl
2
1 2a b e n6
gm6

5a ba b
v3 20.5gm1 sC2 1 gm5 1 gm6 2gm1
5.2-20. as s 0
vin sC1 1 Gout sC2 1 gm6 gds1 1 gds5
v3
5 273.69 V/V, p1 5 24.5 3 106 rad/s, p2 5 2223.6 3 106 rad/s, and z1 5 2447.2 3 106
vin
rad/s

vout 2KN(W/L)1 2 2
5.2-21. 52 and Rout 5 5
vin E IBIAS( 1 1 3)2 (gds1 1 gds3) IBIAS( 1 1 3)
5.2-22. VIC(min) 5 VT1 1 Vdsat1 1 Vdsat5, VIC(max) 5 VDD, and VDD 5 2Vdsat 1 VT1
5.2-23. SR 5 ISS/(2CL) for capacitive load. SR 5 ISS/CL for resistive load.
 Chapter 5 735

ZVosZ 5 0.3 1 5 0.48 V if ISS 5 100 A

ISS ISS
5.2-24. 2
E 0.9  E 1.1 

5.3-1. Av 5 220 V/V. From the transfer characteristics, the small-signal gain is approximately 210 V/V.
5.3-2. Hint: Assume that VGG2 2 VT2 is greater than vDS1 and express Eq. (5.3-4) as iD2 < 2(VGG2
2 VT2)vDS2. Solve for vOUT as vDS1 1 vDS2 and simplify accordingly.
3
(VDD 2 VGG3 2 ZVT3Z)2 c d (1 1 3 VDD)
1 1
5.3-3. Vout(min) 5 2
21 VDD 2 VT1 VGG2 2 VT2
gm3rds3rds4
5.3-4. RS2 5 5 rds
gm2rds2

, ID4 5 990 A, and Rout > [gm2rds2rds1 7 rds3]

Av ID4
5.3-5. 5 11
Avo E ID2
5.3-6. Av 5 2306.78 V/V and Rout 5 3.686 MV
5.3-7. (a) Circuit 3 has the highest gain. (b) Circuit 1 has the lowest gain. (c) Circuits 3 and 4 have
the highest output resistance. (d) Circuits 1 and 5 have the lowest output resistance. (e)
Circuits 14 have the lowest power dissipation. (f) Circuits 1 and 5 have the highest
Vout(max). (g) Circuit 4 has the worst (lowest) Vout(max). (h) Circuits 2 and 6 have the best
(lowest) Vout(min). (i) Circuit 3 has the worst (highest) Vout(min). (j) Circuits 1 and 5 have the
highest 23 dB frequency because of lowest Rout.
5.3-8. Av 5 241.42 V/V and Rout 5 8.838 MV
21 21 21
5.3-9. p1 5 > 5
R1(AvC2 1 C1) R1(AvC2) gm1R1R3C2
5.3-10. Vout(min) 5 24.85 V for current source load inverter. Vout(min) 5 23.6 V for simple cascode
amplifier.
2gm1 2 22K1(W/L)1
5.3-11. Av 5 or Av 5
a b
gds1gds2 gds3gds4
1 2 3 4
ID
1
gm2 gm4 1
22K2(W/L)2 22K 3(W/L)3

5.3-12. Av 5 2418 V/V

0.5gm1
5.3-13. (a) Av 5 . (b) The magnitude of VBIAS should be at least VGS 1 Vdsat. One
gds2gds4 gds6gds8
1
gm4 gm6
way to implement VBIAS is shown in Fig. 6.5-1(b) of the text. (c) If the currents were not equal,
the voltages at the drains of M3M5 and M4M6 will be near VDD or near the sources of M1
and M2. Either way, M5M8 or M1M4 will not be saturated. The best way to solve this problem
is through the use of common-mode feedback. This is illustrated in Fig. 5.2-15 of the text.
736 HOMEWORK PROBLEM ANSWERS

5.3-14. Choose ID3 5 ID2 5 ID1 5 25 A. The maximum output swing gives W3/L3 5 W4/L4 5 1.
From the gain we get W1/L1 5 3. The minimum output swing gives W2/L2 5 1. Therefore,
VGG2 5 1.76 V and the power dissipation is 0.125 mW.
vo R2/R1
5.4-1. 5
vs 1 1 (1/Ai)
5.4-2. W2 5 10 m and L2 5 1 m, Rin 5 6.74 kV and Rout 5 25 kV
5.4-3. Ai(0) 5 0.988, Rin 5 2796 V, Rout 5 250 kV and f23dB 5 973 MHz
vx gds3 1 gds4
5.4-4. Rin 5 <
ix gm1gm3
3.25
5.4-5. Rin 5 and Rout < rdsP
gmN2rdsN
vx
5.4-7. Rin 5 < gm1rds1gm3rds3rds2
ix
vx 1
5.4-8. Rin 5 < . Plot iout 5 2iin.
ix g m3 m4rds3
g
rds1 1 rds2
1 1 gm2rds(gm3 1 gm4)rds3 7 rds4
5.4-9. Rin 5

5.4-10. Ai 5 210 A/A, Rin5 1.8 kV, and Rout 5 22.2 kV

vout rds3 1 gm2rds2rds3 iout rds1(1 1 gm2rds2)
5.4-11. 5 , 52 ,
vin rds2 1 rds3 iin rds1(1 1 gm2rds2) 1 rds2 1 rds3
rds1(rds2 1 rds3) rds2rds3
Rin 5 and Rout 5 rds2 ZZ rds3 5
rds1 1 rds2 1 rds3 1 gm2rds2rds1 rds2 1 rds3
5.5-1. W2/L2 5 38 m/1 m and W1/L1 5 3 m/1 m
5.5-2. W1/L1 5 8.6 m/1 m
5.5-3. Av 5 0.943 V/V and Rout 5 6.37 kV
5.5-4. (a) vOUT(max) 5 12 V. (b) vOUT(min) 5 21.6514 V. (c) SR1 5 14 V/s. (d) SR2 5 2482
V/s. (e) Rout < 408 V.
5.5-5. (a) vOUT(max) 5 12 V. (b) vOUT(min) 5 21.5815 V. (c) SR1 5 14 V/s. (d) SR2 5 21069
V/s. (e) Rout < 4275.24 V.
5.5-6. Av 5 0.9026 V/V and Rout5 1361 V
(VDD 2 VSS)2
5.5-7. max 5 < 20%
(VDD 2 VT1)(VDD 2 VSS 2 VT1)
5.5-8. Fig. 5.5-3(a): z 5 214.9 GHz and p 5 2140.8 MHz. Fig. 5.5-3(b): z 5 214.9 GHz and p 5
271.1 MHz.
 Chapter 5 737

5.5-9. (a) Circuit 5 has the highest voltage gain. (b) Circuit 4 has the lowest voltage gain. (c) Circuit
6 has the highest output resistance. (d) Circuit 1 has the lowest output resistance. (e) Circuits
2, 4, and 6 have the highest output swing. (f) Circuits 1, 3, and 5 have the lowest output
swing.
V2DD
2RL
5.5-10. 5 which is /4 when VDD2VSS 5 VDD/2
V2DD
(VDD 2 VSS)a b
RL

a b a bZVT2Z
K P W2 L1
VT1 2
E K N L2 W1
5.5-11. VBias 5

a ba b
K P W2 L1
12
E K N L2 W1

5.5-12. Vout(max) 5 (VDD 1 VBIAS 2 VT1) 1 Y

1 1 2(VDD 2 VBIAS 2 VT1)

where Y 5 2 2 1
RLKN (W/L)1 E (RLKN(W/L)1) (RLKN (W/L)1)
Vout(min) 5 (VSS 2 VBIAS 1 ZVT2Z) 2 Z

1 1 2(VSS 2 VBIAS 1 ZVT2Z)

where Z 5 2 2 1
RL KP (W/L)2 E (RLKP (W/L)2) (RLKP (W/L)2)

VDD
5.5-13. Vout(max) 5
1
11
W2
KP Rl(VSS 2 VDD 1 VTR2 1 ZVT2Z)
L2
VSS
Vout(min) 5
1
11
W1
KN RL(2VSS 1 VDD 1 VTR2 2 ZVT2Z)
L1
5.5-14. Set up a means for monitoring the output sinking and sourcing current and then connect this
current through the drain of a transistor to the drain of an opposite-type transistor whose cur-
rent is fixed at the short-circuit limit. Use the voltage between these drains to ground to drive
a circuit that will protect the sinking (M2) and sourcing (M3) transistors.

Rout 5 c d 7 RL
2 2
5.5-15. Rout 5 and
gm1 1 gm2 gm1 1 gm2
738 HOMEWORK PROBLEM ANSWERS

5.5-16.
Fig. 5.2-1 Fig. 5.3-1 Fig. 5.3-6 Fig. 5.5-1 Fig. 5.5-3b

2 KN W1 2KN W1 See Eq. (5.3-37) 22 KN W1 22KN (W1/L1)ID

Av 2 Gain I21
N 1 P E 2IDL1 E L1ID 2p D N 1 P E 2IDL1 1 1 22KN (W1/L1)ID
1 1 1 1 1
Rout
ID ID ID21.5 ID 2ID
Zp1Z ID ID I1.5
D ID I0.5
D

Chapter 6
vout R2
6.1-1. 511
vin R2
vS
6.1-2. vin 5 where vin 5 input to op amp, vS 5 external input signal, f 5 feedback factor, and
1 1 fAv
Av 5 differential voltage gain of the op amp. As Av , then vin 0.
6.1-3. Use the definitions to show that vout 5 Acmvcm.
6.1-6. The gain in the circuit is already at the level of a two-stage op amp. The gain could easily be
increased by making the W/L ratio of M7 to M4 and M6 to M5 greater than one.
6.2-2. The actual phase margin is 51.83 compared to 45 estimated from the Bode plot.
6.2-7. The RHP zero occurs because there are two paths from the gate of M6 to the drain and at
some value of the complex variable, s, these paths will cancel, giving a zero. The RPH zero
has a stronger influence on MOSFETs because gmMOS < gmBJT.
6.2-8. (a) p2 5 214.2 3 106 rad/s. (b) PM 5 71.7 (c) PM 5 34.4.
6.2-10. W1/L1 5 10 and W6/L6 5 12.33
6.2-11. (a) Rz 5 2 kV, p1 5 24,444 rads/s, p2 5 2100 3 106 rad/s, and p4 5 2500 3 106 rad/s.
(b) Rz 5 2.33 kV, p1 5 24,444 rad/s, and p4 5 2429 3 106 rad/s.
6.3-1. I5 5 20 A, I6 5 125.66 A, W1 5 W2 5 7.17 m, W3 5 W4 5 10 m, W5 5 20 m, W6 5
125.66 m, and W7 5 125.66 m

6.3-4. Characteristic Circuit 1 (n-channel input) Circuit 2 (p-channel input)

Noise Worse but not by much because Better but degraded by the lower
the first-stage gain is higher first-stage gain
Phase margin Poorer (gmI larger but gmII smaller) Better
Gain bandwidth Larger (GB 5 gmI/Cc) Smaller
Vicm(max) Larger Smaller
Vicm(min) Smaller Larger
Sourcing output current Large Constrained
Sinking output current Constrained Large
 Chapter 6 739

6.3-5. The new value of ICMR is 2.62 V as compared to 3 V.

6.3-6. W1 5 W2 5 6 m, W3 5 W4 5 7 m, W5 5 29 m, W6 5 43 m, and W7 5 90 m
6.3-7. I5 5 I8 5 36 A, I7 5 60 A, Av 5 2489 V/V, Rout 5 185 kV, Pdiss 5 660 W, Vin,(max) 5 0.51
V, Vin,(min) 5 22.21 V, Vout,(max) 5 1.8 V, SR 5 6 V/s, p1 5 21.16 kHz, and p2 5 22.8 kHz
6.3-8. For Av 5 9090 V/V: W1/L1 5 W2/L2 5 2 m/2 m, W3/L3 5 W4/L4 5 3 m/2 m, W5/L5
5 20 m/2 m, W6/L6 5 12 m/2 m, W7/L7 5 40 m/2 m, and W8/L8 5 20 m/2 m.
Rz < 4 kV, CC 5 74.2 pF, CL(max) 5 141.5 pF, and SR 5 0.674 V/s
6.3-9. For Av 5 5000 V/V: W1/L1 5 W2/L2 5 2 m/2 m, W3/L3 5 W4/L4 5 3.6 m/2 m, W5/L5 5
40 m/2 m, W6/L6 5 7.2 m/2 m, W7/L7 5 40 m/2 m, and W8/L8 5 20 m/2 m. Rz <
5.24 kV, CC 5 105 pF, CL(max) 5 110 pF, and SR < 1 V/s
6.3-10. I8 5 10.75 A, I5 5 2I8 5 21.5 A, I7 5 10I8 5 107.5 A, Av(0) 5 5395 V/V, GB 5 4.90
MHz, |SR| 5 4.3 V/s, Pdiss 5 0.699 mW, and PM 5 63.6
6.3-11. Av 5 3079 V/V, Rout 5 333 kV, p1 5 21391 Hz, GB 5 0.697 MHz, SR 5 2 V/s, and Pdiss
5 1.4 mW
W6B I8 CC 1 CL 2
a b5a b a b , W6A/L6A 5 W6/L6 5 94, I8 5 I9 5 I10 5 I11 5 15 A,
W6A
6.3-13.
L6A L6B I7 CC
W6B/L6B < 32, Rz 5 4.59 kV, and z1 5 p2 5 215 MHz

gm1gm6
6.3-14. Av 5
(gds2 1 gds4)(gds6 1 gds7)

6.3-15. Cc I W1 = W2 W3 = W4 W5 = W8 W6 W7 W9 = W10 W11 = W12 Pdiss

2 pF 20 A 33 m 7 m 202 m 165 m 800 m 80 m 120 m 450 W

6.3-16. The compensation capacitor, CC, is removed from the op amp when the output voltage is high
because M10 is off. This is due to the fact that the drain-source voltage of M10 is the same
as the output and the gate is connected to VDD. M10 needs to be moved to the right of CC or
paralleled with a PMOS connected to VSS or both.
6.4-2. PSRR1 5 1737 V/V, PSRR2 5 2171 V/V, p1 5 172.4 kHz, z1 5 11.6 MHz, and z2 5 p2
5 6.2 MHz.
6.4-3. Fig. P6.4-3 has a PSRR1 that is approximately Cgd/Cc less than Fig. 6.4-2(a).
21
5 c d
vout 2gmIgmII GI(gds6 2 gds7 2 gm7)
6.4-4. and z1 < .
vground GI(gds6 2 gds7 2 gm7) Cc(GI 1 gm6 2 gm7 1 gds6 2 gds7)
The two poles are the same as given by the zeros of Eq. (6.4-14) in the text.
6.5-1. VBIAS 5 1.3 V, R 5 12.65 kV, and Av 5 26248 V/V.
6.5-2. WB1/LB1 5 WB2/LB2 5 WB3/LB3 5 WB4/LB4 5 1 and WB5/LB5 5 0.25. I5 5 110 A
740 HOMEWORK PROBLEM ANSWERS

6.5-3. (a) RC1 < gmC1 and RC2 < rds. (b) RC1 < gmC1 and RC2 < gmC2.
6.5-4. W1/L1 5 W2/L2 514.5 m/1 m
6.5-5. Av 5 22620 V/V
6.5-6. I5 5 250 A and W6 5 W7 5 W3 5 W4 5 W8 5 40
6.5-7. Rout 5 11.11rdsN and Av 5 18,518 V/V
6.5-8. Rout 5 20 rdsN and Av 5 100,000 V/V
6.5-9. ICMR 5 Vin(max) 2 Vin(min), where

I7 2I7
Vin(max) 5 VDD 1 VT1(min) 2 1
E K N(W3/L3) E K N(W5/L5)

I7 2I7
Vin(min) 5 VSS 1 VT1(max) 2 1
E K N(W1/L1) E K N(W7/L7)
W1/L1 5 W2/L2 5 64 m/10 m, and W3/L3 5 W4/L2 5 135 m/10 m

8K NK P(W1/L1)(W8/L8) 1
6.5-10. Av 5 and Rout 5
E I7I9( P 1 P)2 2P gds8 1 gds9
2
6.5-11. Rout 5 0.2gmNrdsN and Av 5 2000 V/V if k 5 1
6.5-12. pout 5 25000 rad/s, pA < pB < 2416.7 Mrad/s, p6 < 2909 Mrad/s, p8 < 2181.2 Grad/s,
and p9 < 2909 Mrad/s

6.5-13. W1 = W2 W3 = W4 = W6 W9 = W10 W5 I5(A) Avd VBP VBN Pdiss

= W7 = W8 = W11

90 40 18 11 250 A 17,324 V/V 3.3 V 1.7 V 2.5 mW

6.5-14. S1 5 S2 5 79, S3 5 21.6, S4 5 S5 5 S14 5 36.4, S6 5 S7 5 S13 5 7.3, S8 5 S9 5 S10 5 S11

5 80, S12 5 27, and Av 5 4364 V/V
6.5-15. W1 5 W2 5 36 m, W3 5 W4 5 W6 5 W7 5 24 m, W8 5 W9 5 W10 5 W11 5 121 m, W15
5 4 m, W12 5 W13 5 W5 5 1.4 m, W14 5 16 m, Rout 9.3682 MV, and Av 5 3217 V/V
6.5-16. pA 5 2gm6/C and pB 5 21/rdsC. Both of these poles will appear as output poles in the over-
all voltage transfer function.
6.5-17. Rout 0.556 GV, Av 5 10,417 V/V, and pdominant < 180 rad/s
6.6-1. VOS < 1 mV
vOUT 22 3 106(s 1 0.01)
6.6-2. 5
vIN (s 1 41.07)(s 1 1529.72)
6.6-10. The positive and negative slopes require extra current to allow the relationship i 5 C(dv/dt)
to be satisfied. This means that the current through M6 is different for the positive and nega-
tive rise and fall times. This changes gm6, which changes the dominant pole and influences the
phase margin.
 Chapter 7 741

Chapter 7

7.1-1. W18/L18 5 13.5, W19/L19 5 4.9, W21/L21 5 10.5, and W22/L22 5 55.
7.1-2. VA 5 0.9 V, VB 5 1.0 V, and VC 5 0.1 V
vout 2gm1gm4
7.1-5. 5
vin gm2gm4 2 (gm3 1 gds4)(gds1 1 gds2)
7.1-6. Rout 5 67.3 V and f23dB 5 236 MHz
7.1-7. Rout 5 294.5 V, f23dB 5 10.81 MHz, max/min output 5 1 V, and Pdiss 5 3.9 mW
7.1-8. In a bulk CMOS p-well (n-well) technology, npn (pnp) BJTs (both substrate and lateral) are
available. The advantage of using a BJT in a Class A output is a reduced output resistance.
The disadvantages include unsymmetrical drive and limited output current.
1 1
7.1-9. Rout > 1 and Rout 5 1152 V
gm10 (1 1 F)gm9
7.1-10. p1 5 284.3 Mrad/s, p2 5 223.32 Mrad/s, and z1 5 2614 Mrad/s. Neither p1 nor p2 is greater
than 10GB if GB 5 5 MHz, so they will deteriorate the phase margin of the amplifier of
Example 7.1-2.
7.1-11. I1 5 I2 5 I3 5 I2 5 60 A, I5 5 120 A, I6 5 I7 5 40 A, IQ1 5 2 A and IQ2 1 I9 5 200
A. Av 5 532.2 V/V and Rout 5 287.4 V.
7.2-1. GB 5 26.79 MHz and Cc 5 18.66 pF
7.2-2. GB < 0.23p6
7.2-3. PM 5 16
7.2-4. GB 65 MHz and CL 1.54 pF
W1 W2 W5 W6
7.2-5. 5 50, 5 5.6, 5 50.5, and 5 5.6
L1 L2 L5 L2
7.2-6. pin 5 2466 MHz and pout < 250 MHz
7.2-7. Rin 5 1076 V, Rout 5 636V, and f23dB 5 13.87 MHz.
7.2-8. R1 5 1/gm13

7.3-1. Fig. 7.3-3 Fig. 7.3-5 Fig. 7.3-6 Fig. 7.3-8 Fig. 7.3-11

Noise Good Good Poor Poor Poor

PSRR Poor Poor Good Good Good
ICMR
Vic(max) VDD 2 VON VDD 2 VON VDD 2 VON 1VT VDD 2 VON 1VT VDD 2 VON
Vic(min) VSS12VON 1VT VSS12VON 1VT VSS12VON 1VT VSS12VON 1VT VSS13VON 12VT
OCMR
Vo(max) VDD 2 VON VDD 2 VON VDD 2 2VON VDD 2 2VON VDD 2 2VON
Vo(min) VSS 1 VON VSS 1 VON VSS 1 2VON VSS 1 2VON VSS 1 2VON
SR ISS/Cc ISS/Cc ISS/CL ISS/CL ISS/CL
742 HOMEWORK PROBLEM ANSWERS

7.3-2. 0.5RL
7.3-3. For Fig. P7.3-3(a) Av 5 3673 V/V, and for Fig. P7.3-3(b) Av 5 9117 V/V
7.3-4. Avd < (gm2rds2)/4 and rout < rds/2
7.3-5. Avd < (gm2rds2)/2 and rout < rds/2
7.3-6. Avd < (gm2rds2)/6 and rout < 2(gmrds2)/3
7.3-7. Avd < (gmrds)/2 and rout < rds
7.3-8. Avd < (gm2rds2)/2 and rout < 2(gmrds2)/3
7.3-9. Avd < (gm2rds2)/2 and rout < (gmrds2)
7.3-11. (a) CMFB LG 5 2111.8 V/V. (b) CMFB LG 5 23290 V/V
gmC2gm4
7.3-12. ZLGZ 5
2gmC5 a b
gds4gds6 gds8gds10
1
gm4 gm10
The compensation of the common-mode feedback loop can be done using the output load
capacitor (single-ended load capacitors to ac ground).
7.3-13. Avd < (gm3rds3)/6 and rout < 2(gmrds3)/3
7.3-14. Avd < (gm2rds2)/3 and rout < 2(gmrds2)/3
7.4-1. Av(0) 5 19,508 V/V, GB 5 61.43 kHz, SR 5 0.05 V/s, and Pdiss 5 1.35 W
7.4-2. Av(0) 5 73,846 V/V, GB 5 122.5 kHz, SR 5 0.1 V/s, and Pdiss 5 0.9 W. W15/L15 5 2.02
and W13/L13 5 0.7.
7.4-3. vin /nVt 5 0.908
7.4-4. W2 /L2 5 100 and Vds2 5 7 mV
7.5-1. Veq < 10 nV/ 2Hz
7.5-2. fc 5 150.4 kHz and Veq(rms) 5 4.45 V for a 100 kHz bandwidth
14.72 310212 2
7.5-3. e2eq(1/f) 5 V /Hz, e2eq(Thermal) 5 2.42 310217 V2/Hz,
f
fc 5 608 kHz and Veq(rms) 513.1 nV/2Hz
7.5-4. Veq(rms) 5 75.5 V
7.5-5. Veq(rms) 5 55.73 V
7.6-1. VDD 5 0.671 V
7.6-2. VDD 5 0.411 V
7.6-3. VDD 5 0.711 V
7.6-4. Vonn 5 1.578 V and Vonp 5 0.57 V
 Chapter 8 743

7.6-7. Interchange IVBE and IPTAT in Fig. 7.6-16(a). Add the two correction terms, INL and K3INL1, to
the uncorrected IVBE 1 K1IPTAT to achieve the desired temperature compensation.
7.6-8. p2 5 220 MHz, p6 5 21.2 GHz, and p3 5 2101 MHz. GB = 58 MHz and Cc 5 2 pF.
7.6-9. ICMR 5 0.9 V
7.6-10. ICMR 5 0.8 V

Chapter 8

8.1-3. tp 5 500 ns
8.1-4. Vin > 100.05 mV
8.2-1. VOH 5 2.43 V; VOL 5 2VSS 5 22.5 V
Vin(min) 5 1.5 mV; p1 5 1.074 MHz; p1 5 0.67 MHz
8.2-2. Slew rate should be greater than 36.79 V/ms
8.2-3. When Vin 5 10 mV, k 5 15.576 and tp 5 35.8 ns
When Vin 5 100 mV (assuming no slewing), k 5 155.76 and tp 5 11.3 ns
When Vin 5 1 V (assuming no slewing), k 5 1557.6 and tp 5 3.58 ns
8.2-5. VTRP 5 1.89 V; VTRP(max) 5 3.22 V; VTRP(min) 5 0.39 V
8.2-6. The total propagation delay is 133.2 ns.
8.2-7. The total output fall time is 79.8 ns, and the total output rise time is 9.5 ns; thus, the total prop-
agation time delay of the comparator is 44.7 ns.
8.2-8. tfo1 5 6 ns; tr, out 5 2.36 ns; tp1 5 8.36 ns; tro1 5 27.3 ns
tf, out 5 131.6 ns; tp2 5 158.9 ns
The average propagation delay is 83.63 ns.
8.2-9. (W/L)6 5 120; (W/L)7 5 55; (W/L)1 5 (W/L)2 5 12; (W/L)5 5 16; (W/L)3 5 16 5 (W/L)4
8.2-10. (a) tp 5 0.513 s, (b) tp 5 0.100 s, and (c) tp 5 0.100 s
8.2-11. tp 5 125 ns
8.2-12. (W/L)1 5 (W/L)2 5 4.5; I5 5 30 mA
Vdsat5 5 0.2 V, thus (W/L)3 5 (W/L)4 5 15
(W/L)7 5 31.5, (W/L)6 5 210, and I7 5 210 mA
VTRP2 5 23.1 V
tfo1 5 15 ns; tr, out 5 2.4 ns; tp1 5 17.4 ns; tro1 5 35 ns
tf, out 5 21.4 ns; tp2 5 56.4 ns
The average propagation delay is 36.9 ns, which is well below 1000 ns.
744 HOMEWORK PROBLEM ANSWERS

8.3-1. tp 5 20 ns
8.3-2. |p1| 5 10318 rps. The maximum slope is 0.77 V/s and since the SR 5 20V/s, the compara-
tor does not slew. The propagation delay time is tp 5 3.3 s.
8.3-3. The total gain is 5.052 3 109 V/V and tp 5 57.5 ps.
8.3-4. SR2 5 216 V/s and SR 1 5 48.4 V/s
8.4-1. T 5 0.47 s; as t  vout (t) 5 0.999 VOS
8.4-2. R2 5 2R1 5 200 k; VREF 5 2/3 V
8.4-3. R2 5 R1 5 100 k
8.4-4. ZLGZ 5 22.6
8.4-5. R2 5 3R1 5 200 k; VREF 5 0 V
1 2
8.4-6. VTRP 5 0.215 V; VTRP 5 20.215 V
8.4-7. There are two possibilities that could account for the differences. The first is due to the sim-
ple Sah model, which does not model the saturation voltage very well. This voltage is the
point at which transistors make the transition from active to saturation and is an important part
of the development of the trip points. The second is the neglect of the bulk effects on transis-
tors M1 and M2.

8.5-1. Advantages Disadvantages

Fig. 8.5-1 Can remove input-offset voltage Requires switches

Positive terminal on ground Charge feedthrough
eliminates need for good ICMR Must be stable in autozero mode
Open-loop Stability not of concern Requires good ICMR
comparator Continuous time operation Cant remove input-offset voltage

8.5-2. The NMOS latch would be faster because it has a larger small-signal loop gain.
8.5-3. For Vin 5 0.01(VOH 2 VOL), tp 5 422 ns
For Vin 5 0.1(VOH 2 VOL), tp 5 174 ns
8.5-4. For Vin 5 0.01(VOH 2 VOL), tp 5 188 ns
For Vin 5 0.1(VOH 2 VOL), tp 5 76.8 ns

8.5-6. Advantages Disadvantages

Fig. 8.5-3 Work with smaller power supply Class A outputcant source an
sink with the same currentslow
Fig. 8.5-8 Pushpull is good for sinking and Needs larger power supply
sourcing a lot of currentfast

8.5-7. |VOS| 5 0.314 V

 Chapter 9 745

8.6-1. (a) The closed-loop gain is 225. Thus, the 23 dB bandwidth becomes for  2 3 dB 5 400
krad/s.
(b) The closed-loop gain is 25. Thus, the 23 dB bandwidth becomes for  2 3 dB 5 2000
krad/s.
8.6-2. Av 5 6.6 V/V; p1 5 5.15 MHz
8.6-3. Av 5 6.873 V/V; f23dB 5 2.62 MHz
8.6-4. The minimum delay is 20.08 ns and if it is achieved then x 5 1/8.
8.6-5. tp 5 t1 1 t2 5 3.13 ns 1 16.095 ns 5 19.226 ns
8.6-6. tp 5 t1 1 t2 5 1.131 ns 1 0.916 ns 5 2.047 ns
8.6-7. tp 5 t1 1 t2 5 3.16 ns 1 1.477 ns 5 4.637 ns

Chapter 9

9.1-4. INL: 11LSB, 22.5LSB, DNL: 11.5LSB, 22LSB. The converter is not monotonic.
9.1-5. SNR 5 54 dB
9.1-6. Rms noise 5 21.6 mV; fractional temperature coefficient 5 0.3052 ppm/(C
I1 I2 I4
9.2-1. IOUT 5 IO, , ,
2 4 8
2i2N
9.2-2. (a) Tolerence of ith current sink is 3 100%
2
2i2N
(b) Tolerence of ith current sink is 3 100%
2N
7
9.2-3. (a) vout 5 3 ideal characteristic
8
VREF
(b) Gain error of 1/16 and offset of
15
(c) INL 5 10.5LSB and 21.0LSB, DNL 5 10.5LSB and 21.5LSB. This converter is not
monotonic.
9.2-4. (a) INL 5 10.5LSB and 22.0LSB, DNL 5 10.5LSB and 21.5LSB
32
(b) For 0010, R3 5 R0; for 1000, R3 5 2R0
5
9.2-5. (a) VOS 5 0.01613VREF. (b) A 56.2 V/V. (c) T 5 1.0488 s.
746 HOMEWORK PROBLEM ANSWERS

9.2-6. (a) I 5 500 mA. (b) GB 5 0.496 MHz. SR 5 0.5 V/ms.

(a) FS 5 RI a1 2 b . (b) I 5
1 VREF
9.2-7.
2N
b
1
Ra1 2
2N
(c) N 5 12. (d) f 5 87.4 3 103 conversions/s.
9.2-8. Time for conversion 5 6 ms
9.2-9. DC/C 0.0488%

1
(a) vout 5 CL a 1 1 p 1 N21 1 N bVREF
b0 b1 bN22 bN21
9.2-10.
11 2 4 2 2
2C
C
(b) If CL << 2C, the error is a gain error. (c) CL .
2N
i51 i51
bi bi
9.2-11. vOUT 5 2VREF
on
2i
(b0 5 1) and vOUT 5 2VREF o2
n
i (b0 5 0)

With amplifier offset not equal to zero

i51
bi
vOUT 5 2(VREF 2 VOS)
o2
n
i (b0 5 1)

i51
bi
vOUT 5 (VREF 2 VOS)
o2 n
i (b0 5 0)

VOS causes a gain error.

9.2-13. The worst case occurs when the MSB and all other bits switch oppositely. 1DNL 5 1.275LSB
and 2DNL 5 21.275LSB.
9.2-14. (a) CX 5 2NC. (c) Max component spread 5 2N. (d) This DAC should be fast. (e) Yes. (f) N 5 7.
9.2-15. (a) A 5 1022. (b) T 5 1.9857 ms.

(a) CF 5 2C. (b) vout 5 a 1 bVREF.

b0 b1 b2 b3
9.2-16. 1 1
2 4 8 16
(c) Advantages: Smaller area, better accuracy and auto-zeros the offset of the op amp.
Disadvantages: Has floating nodes, parasitics will deteriorate the accuracy, not monotonic,
and requires a two-phase nonoverlapping clock.
9.3-1. k 5 2: INL 5 13LSB and 0LSB, DNL 5 11LSB and 23LSB
k 5 6: INL 5 10LSB and 21 LSB, DNL 5 11LSB and 20.3333LSB
9.3-2. k 5 3: INL 5 11LSB and 0LSB, DNL 5 10.33LSB and 21LSB
k 5 5: INL 5 10LSB and 20.6 LSB, DNL 5 10.6LSB and 20.2LSB
 Chapter 9 747

9.3-3. k 5 5: INL 5 10.75LSB and 23LSB, DNL 5 10.25LSB and 21.75LSB

9.3-4. WC tolerance 5 7.143%
9.3-5. (a) k 5 4. (b) k 5 6. (c) k 5 2.4.
9.3-7. Rx 5 3R
15
9.3-8. (a) R8 5 16R and R9 5 R. (b) 15.48368R # R8 # 16.5517R. (c) R9 , R.
16
5
bi252i
a1 2 b o bi222i 1 a1 1 b .
8C VREF 7e 2 7e
9.3-10. (a) CX 5
7
. (b) vOUT 5
8 64 i50 8 o
i53
8

Cx
(c) # 1.685%.
Cx
1
9.3-11. fclock 5 5 283 kHz
Tclock
vOUT (2) b1
9.3-12. 5 1 f(b2, 4) 1 f(b3, 2) 1 f(b4, 4). INL 5 13LSB and 0LSB, DNL 5 11LSB
VREF 2
and 23LSB. The converter is not monotonic.

R R
9.3-13. (a) INL(R) 5 2M21 a b LSBs and DNL(R) 5 ;2K a bLSBs
R R
C 2KC
INL(C) 5 ;2K21 a b LSBs and DNL(C) 5 a bLSBs
C C
R C
INL 5 INL(R) 1 INL(C) 5 2M21 a b 1 2N21 a b
R C
R C
DNL 5 DNL(R) 1 DNL(C) 5 2K a 1 b
R C
R
(b) INL(R) 5 2N21 a b LSBs and DNL(R) 5 a bLSBs
;R
R R

C C
INL(C) 5 ;2N21 a b LSBs and DNL(C) 5 2N a bLSBs
C C
R C
INL 5 INL(R) 1 INL(C) 5 2N21 a 1 bLSBs
R C
C R
DNL 5 DNL(R) 1 DNL(C) 5 a2N21 1 bLSBs
C R
9.3-14. The DAC combination where the MSBs are charge scaling and the LSBs are voltage scaling
gives the most bits when both INL and DNL are 1LSB. The number of bits is n 5 9 with m 5
7 bits of charge scaling for the MSB DAC and k 5 2 bits of voltage scaling for the LSB DAC.
748 HOMEWORK PROBLEM ANSWERS

2 2 V2 VREF
9.3-15. vx 5 vAnalog 2 V1 1 2 . For ABCD 5 1011 and vanalog 5 0.8VREF, the compara-
5 5 10 16
tor output will be low.

9.3-16. Errors are (1) Op amp/comparator gain, GB, SR, settling time (offset not a problem). (2)
Resistor and capacitor matching. (3) Switch resistance and feedthrough. (4) Parasitic capaci-
tances. (5) Reference accuracy and stability.
9.4-1. vC1 5 vC2 5 0.6340VREF.
9.4-2. The output voltage is 0.6340VREF.
9.4-3. Error occurs at the third bit.
9.4-4. Vout 5 0.60156VREF. For k 5 0.55, Vout 5 0.3066VREF.
9.4-6. INL 5 11LSB and 20.5LSB, DNL 5 10.5LSB and 21.5LSB. DAC is nonmonotonic.
9.4-7. INL 5 10LSB and 21.1875LSB, DNL 5 11.1875LSB and 20.8125LSB
9.4-9. 0.205 # A # 0.590
9.4-10. 0.41 # A # 0.77
9.4-11. At 4th bit conversion
9.4-12. At 4th bit conversion
9.5-1. Max DNL 5 62 LSB
9.5-2. (a) INLA 5 11LSB, 2INLA 5 21.5LSB; DNLA 5 10.5LSB, 2DNLA 5 21.5LSB
(b) INLD 5 12LSB, 2INLD 5 21LSB; DNLD 5 11LSB, 2DNLD 5 22LSB
9.5-3. (a) INL 5 13LSB and 23LSB, DNL 5 12LSB and 23LSB. (b) WC INL 5 0.5LSB.
9.5-4. N58
9.5-5. N59
9.6-1. For vinp 5 0.25VREF Clock periods 5 1.25NREF
For vinp 5 0.7VREF Clock periods 5 1.7NREF
9.7-1. 10110011

9.7-2. Clock B1B2B3B4 Guessed Vout Comparator Actual

Period D1D2D3D4 Output D1D2D3D4

1 1000 1000 2.5 V 1 1000

2 0100 1100 3.75 V 0 1000
3 0010 1010 3.125 V 0 1000
4 0001 1001 2.8125 V 1 1001

9.7-3. 1001
 Chapter 9 749

9.7-4. 111001
9.7-5. 10101001
9.7-6. 10100111
9.7-7. (a) Minimum e 5 0.0178. (b) minimum VOS 5 60.2 V.
9.7-8. Error at 7th bit
9.7-9. Error occurs at 4th bit when vinp 5 0.1VREF and offset voltage 5 0.1 V
9.7-10. (a) 10001101. (b) 10001011 and the 7th bit is in error.
9.7-11. (a)  # 0.0417. (b) VOS 0.2 V.
9.7-12. Error occurs in the 4th bit.
9.7-13. (a) 01001100. (b) Vanalog 5 0.296875VREF. (c) Never go smaller than 60.2VREF.
9.8-2. 1110000
9.8-3. C1 5 C/3, C2 5 C, C3 5 3C
ADC Comp. Offset Conv. Speed Accuracy Other Aspects

Conv. Flash ADC 0.5LSB Fast Poor Equal R s

Proposed ADC Autozeroed Faster, comp. is simpler Better Unequal Cs, No CMRR problems

9.8-4. R1 5 4/3R, R2 5 2R, R3 5 4R

Conventional Flash ADC Proposed Flash ADC

Advantages Less resistor area Insensitive to CM effects

Guaranteed monotonic
All resistors are equal
Vin* does not supply current
FasterVin* directly connected
Disadvantages Sensitive to CM effects
High impedance nodesonly a
disadvantage if VREF changes
Positive input grounded
No high impedance nodes, fast
More resistor area
Can be nonmonotonic
Resistor spread of 2N
Vin* must supply current
More noise because more resistors

9.8-5. Max conversion rate 5 0.356 3 106 samples per second

9.8-6. (a) N 5 7, (b) N 5 5.
R 1
9.8-7. , 5 12.5%
R 8
9.8-8. All delays are equal and are RC.
750 HOMEWORK PROBLEM ANSWERS

9.8-9. 21 comparators needed for a 7-bit flash

9.8-11. INL 5 13LSB and 21LSB; DNL 5 12LSB and 0LSB; missing codes are 0111, 1010, and
1011. This ADC is monotonic.
9.8-12. 1INL 5 3LSB, 2INL 5 0LSB; 1DNL 5 1LSB, 2DNL 5 0LSB. This ADC is monotonic.
9.8-13. INL 5 11LSB and 20LSB; DNL 5 60LSB
6VREF 6VREF
9.8-14. (a) VREF 5 . (b) VREF 5 .
24 12
k
9.8-15. 5 612.5%
k
9.8-16. INL 5 1LSB; DNL 5 11LSB 5 22LSB. The ADC is not monotonic.
9.9-1. For k 5 1 23dB 5 1.476 MHz; for k 5 0.5 23dB 5 0.654 MHz
9.9-2. (a) L 3. (b) b 5 3
9.9-4. fB 5 53.74 kHz
9.9-5. (a) OSR 55.26. (b) OSR 45.33. (c) OSR 81.
Y(z)
9.9-6. (a) 5 (1 2 z21)2. (b) fB 5 70.909 kHz
Q(z)
9.9-7. Yo(z) 5 z21 X(z) 1 (1 2 z21)2 Q2(z)
9.9-8. (a) NTFQ(z) 5 (1 2 z21)3. (b) fB 46.78 kHz or fB 5 19.5 kHz depending on the assumptions.
9.9-9. (a) DR 5 71.64 dB. (b) DR 5 77.64 dB.
9.9-10. fB 5 15.47 kHz
9.9-11. fB # 189 kHz