m CCD SIGNAL PROCESSOR FOR CAMCORDER

0.35 BW1220X

GENERAL DESCRIPTION

The BW1220X is complete CCD and video signal processor for digital cameras. It converts the analog input signal into
10-bit binary digital codes at a maximum sampling rate of 12MHz. The BW1220X includes CDS(Correlated Double
Sampler), PGA(Programmable Gain Amplifier), clamp for video input, and 10-bit analog to digital converter with
reference generator.

APPLICATIONS

Digital Camcorder
Still Camera

FEATURES

Integrated Correlated Double Sampler

Analog Programmable Gain Amplifier (gain step: 0.156, gain range: 0.156 - 40 time)
Video Input available
Internal Voltage Reference
No Missing Code Guaranteed
Operation by 3.3V Single Power Supply
64 QFP Package

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FUNCTIONAL BLOCK DIAGRAM

VDDA

VBB
VDDD

VDDC
VSSD

VSSA

VSSC

SELIN

OEN
CLAMP

VIDEOIN Video Buffer

10 b
CLAMP MUX 10 b ADC DO[9:0]

PG
CDS PGA
DG
PBLK
CLAMP

RPGA
CLP4 BandGap Clock

Serial to parallel
converter
8b
SHP
SHD
CLP1
MCLK
MODE
DP[7:0]

DS

SDI

SCSN

SCLK

REFT
REFB
COM
BGR
PD

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CORE PIN DESCRIPTION

Name I/O Type I/O Pad Pin Description

SCLK DI picc_bb External clock forserial gain control input
DS DI picc_bb Serial PGA gain control input
SDI DI picc_bb PGA gain control select (low for serial input)
SCSN DI picc_bb Serial gain control input enble(active low)
CLP1 DI picc_bb Black level restore clamp(active high)
DP[0] DI picc_bb Parallel PGA gain control input
DP[1] DI picc_bb Parallel PGA gain control input
DP[2] DI picc_bb Parallel PGA gain control input
DP[3] DI picc_bb Parallel PGA gain control input
DP[4] DI picc_bb Parallel PGA gain control input
DP[5] DI picc_bb Parallel PGA gain control input
DP[6] DI picc_bb Parallel PGA gain control input
DP[7] DI picc_bb Parallel PGA gain control input
SHP DI picc_bb Reference sample clock input
SHD DI picc_bb Data Sample clock input
MCLK DI picc_bb External clock for ADC
MODE DI picc_bb Clock select (high MCLK)
CLP4 DI picc_bb Input clamp (Active High)
PG AI piar10_bb CDS input (AC coupled CCD output through 1uF)
DG AI piar10_bb CDS input (AC coupled CCD output through 1uF)
SELIN DI picc_bb Analog input select(low CCD output)
VIDEOIN AI piar10_bb Composite video input
PD DI picc_bb Power down (active high)
BGR AO poar50_bb Bandgap output voltage
IOUT AO poar50_bb Current output for testing
IVB AO poar50_bb Bias current control for testing
COM AO poa_bb Common mode level
REFT AO poa_bb Reference top voltage
REFB AO poa_bb Reference bottom voltage
PBLK DI picc_bb Pixel blanking control(Active Low)
OEN DI picc_bb control input enable

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CORE PIN DESCRIPTION (Continued)

Name I/O Type I/O Pad Pin Description

DO[0] DO pot4_bb Digital output
DO[1] DO pot4_bb Digital output
DO[2] DO pot4_bb Digital output
DO[3] DO pot4_bb Digital output
DO[4] DO pot4_bb Digital output
DO[5] DO pot4_bb Digital output
DO[6] DO pot4_bb Digital output
DO[7] DO pot4_bb Digital output
DO[8] DO pot4_bb Digital output
DO[9] DO pot4_bb Digital output

I/O Type Abbr.

AI: Analog Input
DI: Digital Input
AO: Analog Output
DO: Digital Output
AB: Analog Bidirectional
DB: Digital Bidirectional
AP: Analog Power
DP: Digital Power
AG: Analog Ground
DG: Digital Ground

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CODE CONFIGURATION

VIDEOIN

SELIN
VDDA

REFT

IOUT
VSSA

REFB

COM

BGR
IVB
PD
VDDC

DG

bw1220X DO[9:0]

PG
VSSC
VBB
CLP4
MCLK
OEN
MODE

SHP

SHD
CLP1
SCSN
SDI

DS
SCLK
VDDD

VSSD

PBLK
DP[7:0]

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ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Supply Voltage VDD 4.5 V
Analog Input Voltage DP/DG/VIDEOIN VSS to VDD V
Digital Input Voltage SHP/SHD VSS to VDD V
Digital Output Voltage VOH,VOL VSS to VDD V
Reference Voltage REFT/REFB/COM/BGR VSS to VDD V
Storage Temperature Range Tstg -45 to 150
Operating Temperature Range Topr 0 to 70
NOTES:
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently.
Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value
is applied with the other values kept within the following operating conditions and function operation under any of
these conditions is not implied.
2. All voltages are measured with respect to VSS unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5k resistor (Human body model)

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ANALOG SPECIFICATIONS

Characteristics Symbol Min Typ Max Unit Conditions

Resolution 10 bits
CDS
Maximum Input Range 1.4 V
Maximum Pixel Rate 12 MSPS
PGA Ain=1Vpp
Gain Range min 0.3 time Gain=2
Gain Range max 38 time
Gain Step 0.156 time
ADC DNL - - 1 LSB
Differential
Nonlinearity
Integral INL - 1.5 LSB Maximum Conversion
Nonlinearity Rate
fc 12 - - MSPS
Reference Top Reference REFT 2.0 V
Bottom REFB 1.0 V
Power Supply
Analog Voltage VDDA 3.3 V
Digital Voltage VDDD 3.3 V
Analog Current IDDA 50 mA
Digital Current IDDD 10 mA
Power Consumption 200 250 mW

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DIGITAL SPECIFICATIONS

Characteristics Symbol Min Typ Max Unit Conditions

Logic Input
High Level Input Voltage VIH VDD-0.5 VSS+| V Logic Output
Low Level Input Voltage VIL 0.5 V High Level Output Voltage
High Level Input Current IIH 10 uA Low Level Output Voltage
Low Level Input Current IIL 10 uA High Level Input Current
Input Capacitance CIN 5 pF Low Level Input Current

VOH VDD-0.5 VSS+| V
VOL 0.5 V
IOH 100 uA
IOL 100 uA

TIMING SPECIFICATIONS

Characteristics Symbol Min Typ Max Unit

SHP Clock Period 83 ns
SHD Clock Period 83 ns
SHP Clock High Period 63 ns
SHP Clock Low Period 20 ns
SHD Clock High Period 63 ns
SHD Clock Low Period 20 ns
ADC Clock Period 83 ns
ADC Clock High Period 41.5 ns
ADC Clock Low Period 41.5 ns
Digital Output Delay td 5 10 ns

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TIMING DIAGRAM

Video A(2)
Input A(0) A(1)

External or
Internal
Clock

SELIN
td

Digital D(-3) D(-2) D(-1) D(0) D(1) D(2) D(3)

Output

tsa tha

DS D7 D6 D5 D4 D3 D2 D1 D0

SCLK

tsa tsclk

SCSN
tsa = 4ns(min);tha = 4ns(min)
tsclk = 100ns(min)

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Effective pixel
Effective interval
pixel interval Optical Optical
Black Horizontal Dummy
CCD interval flyback interval
Output interval

CLP1

PBLK

CLP4

N N+1 N+2 N+3

CCD
Outpu
t

SHP

SHD

CDS
Outpu N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9
t

Internal
CLK
Latency
MODE td

Digital
Outpu N-5 N-4 N-3 N-2 N-1 N N+1 N+2 N+3 N+4 N+5
t

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N N+1 N+2 N+3

CCD
Output

SHP

SHD

CDS N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9
Output

External
CLK

MODE td
Latency

Digital
N-5 N-4 N-3 N-2 N-1 N N+1 N+2 N+3 N+4 N+5
Output

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CORE EVALUATION GUIDE

1. BW1220X is evaluated by external check on the bidirectional pads connected to input nodes of DSP back-end
circuit.
2. The reference voltages may be biased externally through REFT , REFB and COM pins, otherwise these
voltages are internally generated at Reference Voltage Block (Bandgap).

0.1u
0.1u
0.1u

0.1u

10u 10u
0.1u
REFB

REFT

VIDEOIN
SELIN

IOUT
BGR
VSSA
VDDA

PD
COM
IVB

VDDC

DG
HOST

bw1220X DO[9:0] DI[9:0]

MUX
DSP

CORE
PG
VSSC
VBB
CLP4

DO[9:0]
VDDD
VSSD
PBLK
DP[7:0]
MODE
MCLK
SHP
SHD
CLP1
SCSN
SDI

SCLK
DS
OEN

BIDIRECTIONAL PAD FOR

TESTING

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PACKAGE CONFIGURATION

Video in VDDA

50
0.1 0.1

10K
0.1

0.1

0.1
0.1
10

10
u 10u

u
u

u
u
u
u
0.1 u
u
OEN

VDDA
REFB
REFT
VSSA
VSSA
VDDA
VDDA
VIDEOIN
SELIN
PD
COM
IVB
BGR
IOUT
VSSA

VSSP NC
10u

0.1
u

VDDP NC
DO[0] NC
DO[1] NC

10u
0.1
DO[2] VDDC

u
DO[3] VDDC
1u DG
DO[4] DG
DO[5]
DO[6]
DO[7]
BW1220X PG
VSSC
VSSC
1u
PG

DO[8] VBB
DO[9] VBB
DP[0] R1
DP[1] NC
DP[2] NC
DP[3] CLP4
MCLK
MODE
VDDD
PBLK

SCLK
VSSD

SCSN
DP[4]
DP[5]
DP[6]
DP[7]

CLP1
SHD
SHP
SDI
DS

0.1
u
10u

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PACKAGE PIN DESCRIPTION

Name Pin No. I/O Type Pin Description

DP[4] 1 DI Parallel PGA gain control input
DP[5] 2 DI Parallel PGA gain control input
DP[6] 3 DI Parallel PGA gain control input
DP[7] 4 DI Parallel PGA gain control input
PBLK 5 DI Pixel blanking control (Active Low)
VSSD 6 DG Internal digital Ground
VDDD 7 DP Internal digital Supply
SCLK 8 DI External clock for serial gain control input
DS 9 DI Serial PGA gain control input
SDI 10 DI PGA gain control select (low for serial input)
SCSN 11 DI Serial gain control input enble
CLP1 12 DI Black level restore clamp (active high)
SHD 13 DI Data sample clock input
SHP 14 DI Reference sample clock input
MCLK 15 DI External clock for ADC
MODE 16 DI Clock select (high MCLK)
CLP4 17 DI Input clamp (active high)
NC 18
NC 19
R1 20 Chip I.D.
VBB 21 AG Substrate Ground
VBB 22 AG Substrate Ground
VSSC 23 AG Analog Ground
VSSC 24 AG Analog Ground
PG 25 AI CDS input (AC coupled CCD output through 1uF)
DG 26 AI CDS input (AC coupled CCD output through 1uF)
VDDC 27 AP Analog Supply
VDDC 28 AP Analog Supply
NC 29
NC 30
NC 31
NC 32

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PACKAGE PIN DESCRIPTION (Continued)

Name Pin No. I/O Type Pin Description

IOUT 33 AO Current output for testing
BGR 34 AO Bandgap output Voltage
IVB 35 AO Bias current control for testing
COM 36 AO Common mode level
PD 37 DI Power down (active high)
SELIN 38 DI Analog input select (low CCD output)
VIDEOIN 39 AI Composite video input
VDDA 40 AP Analog Supply
VDDA 41 AP Analog Supply
VSSA 42 AG Analog Ground
VSSA 43 AG Analog Ground
REFT 44 AO Reference top voltage
REFB 45 AO Reference bottom voltage
VDDA 46 AP Analog Supply
VSSA 47 AG Analog Ground
OEN 48 DI Digital output enble (active low)
VSSP 49 PG Digital Ground for output buffer
VDDP 50 PP Digital Supply for output buffer
DO[0] 51 DO Digital output(LSB)
DO[1] 52 DO Digital output
DO[2] 53 DO Digital output
DO[3] 54 DO Digital output
DO[4] 55 DO Digital output
DO[5] 56 DO Digital output
DO[6] 57 DO Digital output
DO[7] 58 DO Digital output
DO[8] 59 DO Digital output
DO[9] 60 DO Digital output(MSB)
DP[0] 61 DI Parallel PGA gain control input
DP[1] 62 DI Parallel PGA gain control input
DP[2] 63 DI Parallel PGA gain control input
DP[3] 64 DI Parallel PGA gain control input
NOTE: I/O type PP and PG denote PAD power and PAD ground respectively.

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PHANTOM CELL INFORMATION

Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending on design
methods.
The term "External" implies that the pins should be assigned externally like power pins.
The term "External/internal" implies that the applications of these pins depend on the user.
-

O V R R V V V S P C I B I
E D E E S D D E D O V G O VDDC
-

N D F F S D I L M B R U
A B T A A N I T
N

DG
VSSA

PG

DO[0]
BW1220X
DO[1]
DO[2]
CCD Signal Processor for Camcorder
DO[3]
DO[4]
DO[5] VSSC
DO[6]
DO[7]
DO[8]
DO[9] VBB

D D D D D D D D P V V S S C M M C
P P P P P P P P B S D C S C L S S C O L
L S D L D D S P H H L D P
[ ]
[ ]
[ ]
[ ]
[ ]
[ ]
[ ]
[ ]

0 1 2 3 4 5 6 7 K D D K S I N 1 D P K E 4

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Pin Name Pin Usage Pin Layout Guide

VDDA External - Maintain the large width of lines as far as the pads.
- place the port positions to minimize the length of power lines.
- Do not merge the analog powers with anoter power from other blocks.
- Use good power and ground source on board.
VSSA External
VBB External
VDDD External
VSSD External
VDDC External
VSSC External
VIDEOIN External/Internal - Do not overlap with digtal lines.
- Maintain the shotest path to pads.
SCLK External/Internal - Separate from all other analog signals
NCLK External/Internal
REFT External/Internal - Maintain the larger width and the shorter length as far as the pads.
- Separate from all other digital lines.
REFB External/Internal
PD External/Internal
SELIN External/Internal
COM External/Internal
DG External/Internal
PG External/Internal
MODE External/Internal
CLP4 External/Internal
SHP External/Internal
SHD External/Internal
CLP1 External/Internal
SCSN External/Internal
SDI External/Internal
DS External/Internal
PBLK External/Internal
BGR External/Internal - Separate from all other digital signals
IOUT External/Internal
IVB External/Internal
DP[0] - DP[7] External/Internal - Separated from the analog clean signals if possible.
- Do not exceed the length by 1,000um.
D0[0] - D0[9] External/Internal

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FEEDBACK REQUEST

It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the
following characteristic checking table and fill out the additional questions.

We appreciate your interest in our products. Thank you very much.

Characteristic Min Typ Max Unit Remarks

Analog Power Supply Voltage V
Digital Power Supply Voltage V
Bit Resolution Bit
Reference Input Voltage V
Analog Input Voltage Vpp
Operating Temperature C
Integral Non-linearity Error LSB
Differential Non-linearity Error LSB
Bottom Offset Voltage Error mV
Top Offset Voltage Error mV
Maximum Conversion Rate MSPS
Dynamic Supply Current mA
Power Dissipation mW
Signal-to-noise Ratio dB
Pipeline Delay CLK
Digital Output Format
(Provide detailed description &
timing diagram)

1. Between single input-output and differential input-output configurations, which one is suitable for your system
and why?
2. Please comment on the internal/external pin configurations you want our ADC to have, if you have any reason
to prefer some type of configuration.
3. Freely list those functions you want to be implemented in our ADC, if you have any.

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HISTORY CARD

Version Date Modified Items Comments

Ver 1.0 00.1.30 Original version published (preliminary) BW1220X
Ver 2.0 02.4.23 Phantom cell information added BW1220X

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NOTES

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