IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO.

9, SEPTEMBER 2006 2091

Analytical Modeling of Output Conductance in

Long-Channel Halo-Doped MOSFETs
Sivakumar Mudanai, Member, IEEE, Wei-Kai Shih, Rafael Rios, Member, IEEE,
Xuemei (Jane) Xi, Member, IEEE, Jung-Hoon Rhew, Kelin Kuhn, and Paul Packan

AbstractIn this paper, a detailed physical analysis and an

analytical derivation of the degradation of the output resistance
(Rout ) observed in relatively long-channel laterally nonuniformly
doped devices with halo implants are presented. Two-dimensional
device simulations were performed, and the simulations show that
the channel can be split into two uniformly doped transistors in
series for the purpose of analysis. The lower doped bulk transistor
is on the source side, while the higher doped halo transistor is
toward the drain end. Based on this two-transistor analysis, a
simple Rout degradation model is derived for implementation in
a MOSFET compact model.
Index TermsCompact model, halo, MOSFET, output-
resistance degradation.

Fig. 1. Illustration of the doping profile in a halo-doped long-channel device.

I. INTRODUCTION

T RADITIONALLY, CMOS devices have been optimized

for digital performance, although recently, the same tech-
nology is being used in the development of RF and analog
components [1]. One of the key variables used in this optimiza-
tion process is the halo or pocket implant [2][5]. There are
several models that describe the result of using halo implants
on threshold voltage [6][8]. While this implant successfully
reduces the drain-induced barrier lowering (DIBL) for short
channel lengths, it causes a severe degradation of the output
resistance for longer channel lengths [9]. In [10], a simplified
analytical expression was derived, but a physical explanation
was never offered. The impact of the pocket implants on the
output resistance (Rout ) degradation is also discussed in [11],
but the explanation presented only goes so far as to say that
the presence of barriers on both source and drain causes lower
early voltages for long-channel transistors. In fact, the barrier
reduction on the drain side due to the drain bias is modeled as
long-channel DIBL in compact models [7], [10], but the output-
resistance degradation caused by this model is insufficient to
explain the Rout degradation observed in the on region [10].
Hence, an additional mechanism is required to model the Rout
degradation observed in the on region. Understanding and com-
Manuscript received February 1, 2006; revised May 5, 2006. The review of
this paper was arranged by Editor S. Saha.
S. Mudanai and J. Rhew are with the Compact Device-Modeling Group,
Intel Corporation, Hillsboro, OR 97124 USA (e-mail: Sivakumar.p.mudanai@
intel.com).
W.-K. Shih is with TCAD, Intel Corporation, Hillsboro, OR 97124 USA.
R. Rios and X. Xi are with Intel Corporation, Hillsboro, OR 97124 USA.
K. Kuhn is with the Portland Technology Development Center, Intel Corpo-
ration, Hillsboro, OR 97124 USA.
P. Packan is with the Device Development Group, Intel Corporation, Hills-
boro, OR 97124 USA.
Digital Object Identifier 10.1109/TED.2006.880371
0018-9383/$20.00 2006 IEEE
pact modeling of this phenomenon is not only critical to analog
and RF designs that make use of longer gate lengths in a partic-
ular technology but is also important in the accurate design of
phase locked loops (PLLs) that tend to use intermediate channel
lengths. In this paper, we offer our understanding of this phe-
nomenon and also a compact model that captures the physics of
the Rout degradation process. In Section II, a physical explana-
tion of the phenomenon is given based on the two-dimensional
(2-D) numerical simulations. In Section III, a detailed deriva-
tion of the Rout degradation phenomenon is given. Section IV
discusses the model implementation and comparison against
the experimental data.
II. UNDERSTANDING Rout DEGRADATION
Two-dimensional numerical device simulations were per-
formed for two devices: A) with uniform doping of
9.7e17 cm3 and B) with a laterally nonuniform doping using
a bulk doping of 4e17 cm3 and a Gaussian halo with a peak
of 3.9e18 cm3 . Both devices are 1-m long and wide, with
arbitrarily chosen gate oxide and junction depths. The doping
along the channel is illustrated in Fig. 1 for the nonuniformly
doped device B. Fig. 2 shows the draincurrent (Id ) versus the
drain voltage (Vds ) curves for the devices A and B biased at
the same gate voltage. The devices have the same threshold
voltage, but the current in the linear region is higher for halo-
doped device B [12]. This is because of the effective reduction
in the channel resistance due to the low-doped middle region of
the transistor. The higher current in the linear region, however,
does not reflect any increase in mobility as studied in [13],
where the doping profile is varied in the vertical direction.
The increase in drive is because of the laterally nonuniform
2092
Fig. 2. Ids versus Vds curves at Vgs = 0.6 V for the halo-doped device and
the uniformly doped device. The Vdsat for the halo-doped device is less than
the uniformly doped device. The parameters used for the device simulation are:
W = 1 m, L = 1 m, and tox = 1.2 nm.
doping where the center region is inverted before the source and
drain ends are inverted. It is also distinctly clear that the output
resistance is much lower for device B. Another interesting point
to observe is that although both devices were designed to have
the same threshold voltage, the device B pinches off sooner than
the uniformly doped device A. Both devices are long enough
that the drain saturation occurs because of channel pinch off.
Under pinch-off conditions, the drain saturation voltage Vdsat
is approximately given by the expression [16]
Vgs Vt
Vdsat = (1)
dQb
=1 + . (2)
ds
In the above equations, Vt stands for the threshold voltage of
the device, alpha represents the depletion charge sensitivity to
surface potential, Qb is the depletion charge normalized to the
gate capacitance, and s is the surface potential.
It should be noted that the Vt used in (1) is the threshold
voltage corresponding to the doping at the drain end of the
channel. Therefore, even though the overall threshold voltage
of the devices A and B are the same, the threshold voltage
corresponding to the halo region of device B is much higher
than the uniformly doped regions of device A. Thus, device B
pinches off sooner than device A because the threshold voltage
corresponding to the heavily doped halo region on the drain side
is higher than that of the threshold voltage corresponding to the
uniformly doping in device A. In other words, as the drain bias
is increased, the drain end of the channel for device B pinches
off earlier because it requires a higher vertical field to support
the inversion charges. Furthermore, for the heavily doped
halo region is greater than for the uniformly doped region.
Thus, the impact of is to further reduce the Vdsat for device B.
The potential along the channel is shown for both devices at
multiple drain biases in Fig. 3. At the lowest drain bias (0.2 V),
the transistor is still in the linear region, while at the other two
drain biases (0.5 and 1.2 V), the transistor is in saturation. Com-
paring the different curves of the uniformly doped device A, we
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 9, SEPTEMBER 2006
Fig. 3. Channel potential along the surface of a uniformly doped device
and nonuniformly doped halo device at Vgs = 0.6 V, Vbs = 0.0 V, Vds =
1.2 V, 0.5 V, 0.2 V.
observe that once the transistor reaches saturation, there is no
further drop in the significant portion of the channel, and as ex-
pected, the additional drain bias is dropped in the small pinch-
off region close to the drain. Thus, in saturation, the current
does not increase for the uniformly doped device. For the non-
uniformly doped device B, however, it is interesting to see that
additional potential drop continues to occur along the entire
channel length even in saturation. Thus, transistor B behaves
almost as if it were still a resistor in the saturation region.
This anomalous behavior can be readily explained using a
two-transistor model. As previously observed [10], [14], only
the halo-doped region on the drain side influences the Rout
degradation. Hence, the channel can be split into two transistors
in series, namely the lower doped transistor of length LLhalo
on the source side and halo-doped transistor of length Lhalo
on the drain side as illustrated in Fig. 4(a). As the drain bias
is increased, the transistor operates in the linear region until
the heavily doped halo transistor saturates. However, the lower
doped transistor continues to operate in the linear region. In
this region of operation, two mechanisms contribute to the
anomalous behavior: 1) DIBL, which is modeled as long-
channel DIBL and 2) movement of the pinch-off point toward
the source occurring in the halo transistor. Thus, when the
halo-doped transistor is operating in saturation, the following
drops in potential occur in the following different regions of the
transistor.
1) Vds Vdsathalo is dropped in the pinch-off region of the
halo transistor [Region III in Fig. 4(b)].
2) Vdsathalo Vd is dropped in the linear region of the halo
transistor [Region II in Fig. 4(b)].
3) Vd is dropped in low-doped transistor [Region I in
Fig. 4(b)].
With increasing Vds , the pinch-off point moves closer to the
lower doped region. This causes a reduction in the length
of Region II and thus reducing the effective resistance of
Region II. Since Vdsathalo is dropped across both Regions I and
II, a larger value of Vd must now be dropped across Region I
MUDANAI et al.: ANALYTICAL MODELING OF OUTPUT CONDUCTANCE IN MOSFETs 2093

Fig. 4. (a) Illustration of the two-transistor model. The nonuniform transistor can be modeled as two transistors in series. The source-side transistor is uniformly
doped with Cbulk , while the drain-side transistor is uniformly doped with Chalo . (b) Low-doped Region I operates in the linear region; the halo-doped region
behaves like a transistor in saturation. Region III is the pinch-off region. (c) Equivalent-circuit model to approximate the equivalent Rout for the two-transistor
system.

causing an increase in the draincurrent. This effect thus A. Ghalo

m
reduces the Rout of the halo-doped transistor in saturation.
Under saturation conditions, the draincurrent of the halo
transistor can be described using the textbook equation [16]
III. ANALYTIC MODELING OF Rout DEGRADATION
2
Vgd
Vthalo
Id =  (4)
In the previous section, a simple physical reasoning was pro- Lhalo 2halo
vided to explain the cause for Rout degradation in long-channel = W Cox (5)
transistors that have nonuniform doping in the channel. As
described in Section II, the Rout degradation can be explained where Lhalo is the effective channel length of the halo-doped
by modeling the laterally nonuniformly doped transistor as transistor after taking into account the channel-length modula-
two transistors in series. The source-side transistor is doped tion, is the mobility, W is the width of the transistor, and Cox
uniformly at Cbulk /cm3 and is of length L Lhalo , while the is the oxide capacitance per unit area. To first order, the Gm of
drain-side transistor is doped uniformly at Chalo /cm3 and is the halo transistor can be obtained as
of length Lhalo . L is the total length of the nonuniformly doped

dId Vgd
Vthalo
transistor. It should be noted that the doping in the vertical halo
Gm = =  . (6)
direction is assumed to be uniform for both transistors. The dVgd
Lhalo halo
equivalent circuit for the two transistors can be represented, as
The above equation can be rewritten in terms of the
shown in Fig. 4(c). The equivalent Rout for the two transistor
draincurrent Id to eliminate Vgd
and is given as
can be approximated by the following equation [15]:

halo 2Id

 Gm = . (7)
dVd halo halo Lhalo
Rout = = Rout 1 + Ghalo Bulk
m Rout (3)
dId
halo
B. Rout
where the superscripts stand for the respective doped transis- The derivation of the output resistance for the halo transistor
tors. In the following sections, we will derive simple analytical is the most critical part of this analytical model. Essentially, the
halo
forms for Rout , Ghalo Bulk
m , and Rout . halo transistor is a short channel-length transistor, whose output
2094 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 9, SEPTEMBER 2006

resistance is modulated by the channel-length reduction with

increasing drain bias (CLM). This effect has been extensively
studied and modeled in the literature [17]. Starting with (4)

2
dId Vgd
Vthalo dLhalo
halo
1/Rout = = 2 (8)
dVdd
Lhalo 2halo ddd

Id dLhalo
halo
1/Rout = . (9)
Lhalo ddd

From [17]
  
Lhalo = Lhalo l log y + 1 + y 2 (10)

Vdd Vdsat
halo
y= . (11)
l Esat
In (10), l is a characteristic length, which is a function of
the oxide thickness, junction depth, and dielectric constants,
and Esat is the lateral field needed for velocity saturation.The
saturation voltage for the entire device can be written as
halo
Vdsat = Vd
s + Vdsat . (12)
halo
Using (9), (10), and (12), the Rout can be derived as
 2  2
halo L Vdsat Vds Vdsat
Rout = halo + . (13)
Id L l

Bulk
C. Rout
Fig. 5. (a) Id versus Vds fits for a 2-m drawn gate length and 10-m-wide
As discussed in Section II, the bulk-doped transistor on the NMOSFET at Vbs = 0.0 V and Vgs = 0.5, 0.6, 0.7, 1.1, 1.2 V. (b) Gds versus
source side operates in the linear region. Hence, the channel Vds fits with and without the Rout model for a 2-m drawn gate length and
10-m-wide NMOSFET at Vbs = 0.0 V and Vgs = 0.5, 0.6, 0.7, 1.1, 1.2 V.
current can be expressed as The plot without the Rout model includes long-channel DIBL model.

Bulk

Id = Vgs VtBulk Vd
s Vd
s . (14)

LBulk 2 overall Rout for the cascode system by combining (7), (13),
Differentiating the above expression w.r.t Vd
s , we get an ex- and (19)
Bulk
pression for Rout  2  2
L Vdsat Vds Vdsat
dId
 Rout = halo +
Bulk
1/Rout = = Vgs VtBulk Bulk Vd
s . Id L l
dVd
s LBulk  
(15) 2Id LBulk
Equation (15) can be further simplified by observing that 1+ . (20)
Lhalo (Vt )
Bulk
Vd
s Vdsat and 1. (16)
halo IV. MODEL IMPLEMENTATION AND VALIDATION
From (15) and (16) The above equation is implemented in Intels in-house com-

 pact model by integrating the following equation and adding it

Bulk
1/Rout = Vgs VtBulk Bulk Vdsat (17) to the draincurrent in saturation:
LBulk
 
LBulk Bulk
 Vds
Bulk
Rout = Vgs VtBulk
Vgs Vthalo
(18) dVds
halo Id = . (21)
Rout
Bulk LBulk Vdsat
Rout = (19)
(Vt )
If the draincurrent in the saturation region for a uniformly
where Vt is the difference in threshold voltage between the doped long-channel device is treated to be independent of
halo and the bulk transistor.We now have an expression for the the drain bias, which is a reasonable approximation, then the
MUDANAI et al.: ANALYTICAL MODELING OF OUTPUT CONDUCTANCE IN MOSFETs 2095

Fig. 7. Comparison of Gds versus length between the experimental data and
the compact model with and without the analytic Rout model at Vds = 0.8 V
and Vgs = 0.6 V.

Fig. 6. (a) Id versus Vds fits for 2.0-m drawn gate length and 10.0-m-
wide PMOSFET at Vbs = 0.0 V and Vgs = 0.5, 0.6, 0.7, 1.1, 1.2 V.
(b) Gds versus Vds fits with and without the Rout model for 2-m
drawn gate length and 10-m-wide PMOSFET at Vbs = 0.0 V and Vgs =
0.5, 0.6, 0.7, 1.1, 1.2 V. The plot without the Rout model includes
long-channel DIBL model.

integral in (21) can be simplified and integrated to yield the

following:
Id 1 

Id =    l ln + 1 + 2
Lhalo 1 + 2Id LBulk
Lhalo (Vt )
where
Vds Vdsat L
= .
Vdsat l
The analytic Rout model was fit to the NMOS and PMOS IV
data from Intels 90-nm technology [18]. The Ids and Gds as a
function of the drain bias for the NMOSFET at L = 2.0 m
are compared well with the experimental data, as shown in
Fig. 5(a) and (b). A similar fit is shown for the PMOSFET
IV data at L = 2.0 m at Vbs = 0.0 in Fig. 6(a) and (b). It
should be noted that in Figs. 5 and 6, the curves without the
Rout model do include the long-channel DIBL model that was
developed in house. The long-channel model was calibrated
based on the observed DIBL in the subthreshold region.
Thus, the comparison in Figs. 5(b) and 6(b) shows the effect
of CLM only in the halo transistor and not the long-channel
DIBL. In Fig. 7, a comparison of Gds versus L is shown for the
NMOSFET device between the experimental and the compact
(22)
(23)
Fig. 8. (a) Third-derivative fits for a 2-m drawn gate length and 10-m-wide
NMOSFET at Vbs = 0.0 V and Vgs = 0.5, 0.7, 1.2 V. (b) Third-derivative fits
for 2-m drawn gate length and 10-m-wide PMOSFET at Vbs = 0.0 V and
Vgs = 0.5, 0.7, 1.2 V.
model with and without the analytic Rout model. The impact of
the Rout model is lucid in this comparison. As the gate length is
reduced, the halo implants from the source and the drain sides
begin to merge, as a result, the Rout degradation effect slowly
begins to reduce. This region can be seen at lengths somewhat
greater than 0.1 m as a mild hump. Another important result
to be noted is that at lengths below 0.1 m, where the two halo
regions are already merged, the Rout degradation model has no
effect on the characteristics of the very short devices. This is
2096
achieved through the Vt term in (22), which becomes zero for
very short devices. Finally, for use in low-distortion analog and
RF applications, the compact model must be able to predict the
harmonic distortion. It is well known [19] that when a sinusoid
is applied to the input terminals of a MOSFET, the output signal
contains higher order harmonics in addition to the fundamental
frequency, and that harmonic distortion is related to the higher
derivatives of the draincurrent. Thus, the third derivative of
the measured draincurrent with respect to the drain bias is
compared against the model to ensure that the model meets the
requirements of distortion simulations in Fig. 8(a) and (b). The
harmonic distortion of the draincurrent in the saturation region
originates from the channel-length-modulation model used to
describe the halo transistor, and it can be seen that the compact
model captures the third derivative in this region accurately.
V. CONCLUSION
The degradation of Rout for long-channel devices has been
explained using the 2-D numerical device simulation. A phys-
ical argument was presented to help understand how the pres-
ence of a potential barrier on the drain side impacts the channel
resistance using a simple two-transistor model. An analytic
approach to model the Rout degradation was developed and
implemented in conjunction with our previous three-transistor
threshold-voltage model. The model was validated on several
Intels technologies, but the model results are shown against
Intels 90-nm technology data. The model was also shown to
capture the hump in Gds observed as a function of the length in
technologies that use a strong halo.
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Sivakumar Mudanai (M04) received the B.Tech.
degree from the Indian Institute of Technology,
Chennai, Madras, India, and the M.S. and Ph.D. de-
grees from the University of Texas at Austin, Austin.
He is currently with the Compact Device-
Modeling Group, Intel Corporation, Hillsboro, OR.
His research interests include MOSFET modeling
for digital, analog, and RF applications.
Wei-Kai Shih received the B.S. degree in physics
from National Taiwan University, Taipei, Taiwan,
in 1989, the M.A. degree in physics and the Ph.D.
degree in electrical engineering from the Univer-
sity of Texas at Austin, Austin, in 1994 and 1997,
respectively.
In 1997, he joined TCAD, Intel Corporation,
Hillsboro, OR, to develop electrothermal modeling
and simulation tools for full-chip reliability verifi-
cation. He later moved into the compact transistor
modeling area, focusing on gate leakage modeling
and analog-RF modeling. His current research interests include modeling front-
end, back-end, and process variations for aggressively scaled technology, as
well as improving computer-aided design methodology to facilitate design and
process convergence in all phases of a product development cycle.
Rafael Rios (S84M85) studied engineering sci-
ences in Montevideo, Uruguay. He received the M.S.
and Ph.D. degrees in electrical engineering from
Drexel University, Philadelphia, PA.
He is currently with Intel Corporation, Hillsboro,
OR, where he works on the development and valida-
tion of models and tools for circuit design.
Xuemei (Jane) Xi (M02) received the B.S., M.S.,
and Ph.D. degrees in microelectronics from Peking
University, Beijing, China.
In 1995, she joined the Institute of Microelec-
tronics, Peking University, where she became an
Associate Professor in 1997. From 1999 to 2000, she
was a Senior Engineer with Motorola China. From
2000 to 2005, she was a Research Staff with the
Department of Electrical Engineering and Computer
Science, University of California, Berkeley, where
she worked on the Berkeley Short-Channel IGFET
Model 3 (BSIM3)/BSIM4/BSIMSOI model development and offered technical
support to BSIM users from both the industry and the academics. In 2006, she
joined Intel Corporation, Hillsboro, OR.
MUDANAI et al.: ANALYTICAL MODELING OF OUTPUT CONDUCTANCE IN MOSFETs 2097

Jung-Hoon Rhew received the B.S. degree from Po- Paul Packan received the B.S. degree in electri-
hang University of Science and Technology, Pohang, cal engineering from the University of Washington,
Korea, in 1994, the M.S. degree from the University Seattle, in 1984, and the M.S. and Ph.D. degrees
of Washington, Seattle, in 1999, and the Ph.D. de- in electrical engineering from Stanford University,
gree from Purdue University, West Lafayette, IN, in Stanford, CA, in 1985 and 1991, respectively.
2003, all in electrical engineering. His study and re- After graduation, he joined Siemens AG, Munich,
search focused on the physics and modeling of semi- Germany, as a Guest Scientist, working on high-
conductor devices. speed bipolar transistor design. In 1992, he joined
In 2003, he joined the Compact Device-Modeling Intel Corporation, Hillsboro, OR, working on MOS
Group, Intel Corporation, Hillsboro, OR, where transistor technology development. After working on
he works on device modeling and associated four generations of Intel technologies and managing
automation. the Process and Device-Modeling Group, he moved into circuit-level device
modeling, where he managed the Compact Device-Modeling Group. He is
currently managing the Device Development Group for the 32-nm technology
node. He is the author and coauthor of more than 30 papers and is also the
Kelin Kuhn received the B.S. degree in electri- holder of multiple patents in the area of transistor design and architecture.
cal engineering from the University of Washington,
Seattle, in 1980 and the M.S. and Ph.D. degrees
in electrical engineering from Stanford University,
Stanford, CA, in 1985.
Prior to joining Intel, she was a Tenured Fac-
ulty Member with the Department of Electrical and
Computer Engineering, University of Washington. In
1997, she joined Intel Corporation, Hillsboro, OR,
where she has held a variety of technical positions
on the 0.35-$\mu\hbox{m}$, 130-nm, and 90-nm
nodes and, most recently, was the Integration Manager for the RF/analog deriv-
ative technology on 90 nm. She is currently the Device Manager for the Intel
45-nm CMOS technology, which is being developed at the Portland Technology
Development Center, Intel Corporation. She is the author of numerous technical
publications on optical and electronic properties of semiconductor devices.