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EFFICIENT IMPLEMENTATION OF BIT-PARALLEL FAULT TOLERANT POLYNOMIAL BASIS

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MULTIPLICATION AND SQUARING OVER GF(2M) 2016
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CoreProjects February13,2017

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Efficientimplementationofbitparallelfaulttolerantpolynomialbasismultiplication
andsquaringoverGF(2m)2016
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Abstract:
Subject
This study presents the design and implementation of an efficient structure for
fault tolerant bitparallel polynomial basis multiplication and squaring over Re: Efficient implementation of bitparallel fault tolerant polynomial basis multiplicatio
GF(2m), based mostly on the same strategy of Roving methodology with a
Message
minimum overhead. The Roving technique is an economical method for the
circuitsinthatseveralsimilarandindependentstructuresexist.Thearchitectures
of the polynomial basis multiplication and squaring over binary finite fields have
inherent regularity in their subsections of the structures. Thus, they are compatible to the applied version of Roving fault tolerant
method.Togeneralisetheproposeddesign,themultiplicationandsquaringoperationsareexaminedforvariousprimitivepolynomial,
as well as general irreducible polynomials, irreducible pentanomials and irreducible trinomials. In the proposed style, the extracted
common circuit has low hardware utilisation compared with that of the most circuit. The fault tolerant circuit is constructed by using
three copies of the common circuit, a comparator and a voter circuit. The comparator and voter have parallel architectures with low
critical path delays, which is a essential issue in any highly computational system. The look has been successfully verified and
synthesised onVirtexfour XC4VLX20zero FPGA using Xilinx ISE 11. The results show an overall improvement in the speed and
hardwareusagecomparedwiththoseofpreviousstyles.
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