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HomeELECTRONICSVLSI/VHDL/VerilogHSPICEProjectsEfficientStaticDLatchStandardCellCharacterizationUsingaNovelSetupTimeModel2015

EFFICIENT STATIC D-LATCH STANDARD CELL CHARACTERIZATION USING A NOVEL SETUP

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TIME MODEL 2015
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HSPICEProjects,MicroWindProjects,TannerEdaProjects February4,2017

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EfficientStaticDLatchStandardCellCharacterizationUsingaNovelSetupTime
Model2015
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Abstract:
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In this paper we propose a simple setup time model for a transmission gate
based static latch, which we later use to simplify standard cell library Re: Efficient Static DLatch Standard Cell Characterization Using a Novel Setup Time
characterization methodology. We propose a simple model for the setup time
Message
whichrelatesitlinearlywithinputtransitiontime(TR)andloadcapacitance(CL).
WealsoderivetheregionofvalidityofourmodelintheTR,CLspace.Wederive
the relationship of the model coefficients and the models region of validity with
the size of CMOS latch standard cell. We then derive simple expressions relating our model coefficients with the supply voltage,
threshold voltage, and temperature variations. We use these relationships to simplify latch setup time characterization methodology,
eliminating the necessity of about 67% HSPICE simulations. We show that our model and method of improving the characterization
processarevalidwiththetechnologyscalingandrealisticinputsignals.Weobservethatthevalueofsetuptimeobtainedusingour
model based approach for latch characterization differ from their corresponding HSPICE based method by a maximum (average) of
3.2%(1.5%).

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