Clock tree synthesis

Why we are doing the clock tree synthesis?

To minimize the insertion delay and skew
Meet (max tran/cap/fanout)
Why we minimize the skew?
we can minimize the skew w.r.t to HOLD
if skew is minimum HOLD violation is +ve slack
Why we are talking insertion delay is minimum ?
If we have insertion dealy =1ns..1
Skew=tcap(max)-tlan(min)
Apply ocv on 20% on clk = 1200-800
= 400
If we have insertion delay =2ns .2
Skew=tcap(max)-tlan(min)
Apply ocv on 20% on clk = 2400-1600
= 800
When compared case 1 and case 2 the skew is minimum in insertion delay is less.
Why we are applying the NDR (non-default-routing)?
To avoid the Crosstalk and Electromigration.
For crosstalk: increasing the space
Shielding
For Electromigration: increasing the width.
How does u reduce timing violation after placement?
What is mean by clock reconvergence path?

What is mean by clock insertion delay? Clock network delay?

Insertion delay: the delay from clock source to clock definition point.
Network delay: the delay from clock definition point to clock pin of a flip-flop
If you increase clock frequency in the design, what are the issues you
could expect?
Power dissipation is more.
Setup violation increases.
Utilization increases.
If you want to reduce clock network power, what do you do?

Clock network is the most power consuming circuit in the design. Can you
justify why?

What are different low power techniques that you follow to reduce power?
(Static &
Dynamic)
Power gating
Clock gating
What is mean by clock gating?
The purpose of the clock gating is to minimize the power dissipated inside the flip
flop by eliminating the clock activity at the flip flop during clock cycles when the
flip-flop input is not active.
What is clock divider mean?
What is clock buffer? How it is different compared to signal buffer?
Clock buffers are designed with some special property like high drive strength and
less delay.
Clock buffers are equal rise time and fall time.
Normal buffers are designed with W/L ratio such that sum of rise time and fall time
is minimum.
They too are designed for higher drive strength.
*If you have timing violations (setup & hold) after CTS, how do you decide
to go ahead to routing? or go back to CTS again?

To counter EM issues what do you do on clock nets?

Increasing the width of the clock net
To avoid SI issues, what is the special care you take on clock nets?
What is mean by aggressor & victim in SI? Why always clock nets are
aggressors?
Affecting signal is termed as aggressor
Affected signal is victim
Clock net is a high toggling signal.
What is mean by Signal Integrity ? Cross talk? Why does it occur? How
Clock nets effect SI?
Which layers did you used in your design for clock net routing? Can you
justify why did you used that layers?
Next lower layer to the top two metal layers
Because it has less resistance

In which situation we might need shielding to clock nets?

When crosstalk is more.
Why do we need to give more spacing & width to clock nets compared to
default foundry given rules?
Clock net are highly toggling networks.
What are different non-default rules that we apply on clock nets compared
to signal nets?
Double width double space
Double width single space
Single width double space
shielding
*What does CRPR will impact timing?

How does Derate factor will impact timing?

What is OCV? Why do we need Derate factor?
OCV is On Chip Variation with respect to PVT (process, voltage, temperature)

What is CRPR? Why do we need it?

What is useful skew concept?
*In case you cant reduce further skew, which is causing some timing
violations, what is alternate method to solve timing issue?

*In case if you got new setup violations after CTS compared to pre-CTS,
what could be the reason, how do you solve it?
1)

*If you have congestion issue after CTS, where as you dint had before CTS,
what would be the reason, how do you solve it?

*Can you add any number of buffers to meet skew? How does clock buffers
will impact design? (How do you decide the max number of clock buffers in
a clock path?)

What is mean by skew group?

How do you balance two asynchronous clocks?

What is mean by clock group?

Will you check hold time before CTS? Why cant we check ?
We wont check hold before CTS, why because clock is not propagated so the real
skew not coming to picture.
** if we want to try to fix hold violation before CTS the skew will effect because of
adding buffers implies increases area.

If you have any hold timing violations after CTS, how will you solve it?
Adding buffer / Inverter pairs /delay cells to the data path helps to fix the hold
violation.

Downsizing the cell

What are the different checks you do before you take database to CTS
stage?
What is clock transition violation?
What is inter clock skew balancing mean?
If you have met setup timing before CTS, can you expect setup violations
after CTS? If YES, Why?
Yes.we can expect setup violation after CTS.

What are different clock balancing techniques you followed?

*Can you expect any congestion increase after CTS compared to before
CTS? I f Y ES, why congestion may increase after CTS?

What is mean by clock tree spec file? What does it contain?

Where the clock tree info exists during - among inputs you take in CTS
stage?
What are mandatory inputs needed for CTS?
Clock Tree spec file.
Placement database (DEF)
Netlist
Timing constraints file (SDC)
.lib
Lef
What are other violations will you check other than setup timing &
congestion after placement?
Max transition
Max capacitance
Max fan out
Will clock frequency will be same in setup timing report & hold? Any
comment?

Assume you have 100 setup timing violations after placement. What is y
our next step? Will you go back, change floorplan? or Will you continue to
CTS? Or will you fix setup violations using any ECOs? or Will you try to
solve this issue any other way?.

How do y ou decide even with some setup timing violations to go forward

to CT S or not?

How can you find the operating clock frequency?

How do you find uncertainty of the the clock defined? & What is
uncertainty, why do we
define that?

If you give priority to timing.. Does it impact congestion? If YES, how &
why?

Will you check HOLD timing after placement? If YES why? if NO why?
NO.
*clock is ideal so real skew not coming to picture.

Did you do setup timing check on any design after placement? Which tool
did you used? How did you do? (Any command you remember?, any
options you used?)

How does setup timing report looks like after placement (In a R-R path,
what are the components you see in timing report)

What is slack, skew?

Skew: the difference in timing between two or more signals. May be data, clock or
both.
Slack: the difference between required time and the time that a signal arrives.

What was the skew value did you see in timing report after placement?
Zero
Clock is ideal.

What is WNS, TNS & Failing end points?

Wns: the path having the maximum negative slack.
TNS: sum of all negative slack in the design.

What is critical path? How do you justify its a critical path?

The path between an input and an output with the maximum delay.
Can you expect net delay s in timing report after placement? (I mean if
you report using -nets option, will you see net delays?. I f Y ES, how does
the net delay is calculated? I f NO, why cant we report estimated net
delay?)

Yes .these are approximations. *based on trial route.

What is Wireload model? What is Zero Wireload model timing?

Which calculate the net delay based on the number of Fanouts of particular gate

What are the challenges in lowpower

What is adjust IO
What are the input files required for prime time
What is the syntax for SPEF
What is the syntax for SDF
What are the input file fot PT if we give SDF
What is gate count
What is the frequency of [lowpower project]
How many registers are required for 256x16 RAM
I have block I can increase frequency from 300Mhz to 3GHZ so what are the
problems we face and what is the effect on setup and hold.

How do we balance skew if their multiple clocks

Using inter-clock-delay balancing.

Why do we need to fix transition values in the design even though timing
is meeting.
If we dont fix the transition the signals may be prone to noise which may lead to
improper functionalty of the chip.

What are the CTS targets?

Skew
Insertion delay
Fanout
Max/min capacitance

What are the stages of CTS?