California Polytechnic State University

EE 306 - Electronic Devices, Fall Quarter, 2016

COURSE DESCRIPTION: Internal operation, semiconductor physics, terminal
characteristics, models and applications of diodes (LEDs,
solar cells, and photo-diodes) and transistors (field-effect
and bipolar). 3 lectures. Prerequisites: CHEM 124, EE
212/242 or EE 214/254, PHYS 211, IME 156 or IME 157
Concurrent: EE-346 Lab.

INSTRUCTOR: Dr. Xiaomin Jin

Room 20-315, Phone: 805-7567046, xjin@calpoly.edu

MEETING SCHEDULE: Monday, Wednesday, and Friday

Section 8, 8-10am, Room: 186 - C101
Section 5, 2-3pm, Room: 186 - C101

OFFICE HOUR: Monday: 10:10am-11:00am

Wednesday: 10:10am-11:00am
Thursday 11-1pm
Friday: 10:10am-11:00am
(Any other time can be arranged by appointments using
either voice or e-mail.)

TEXTBOOK: Semiconductor Device Electronics (1 volume CPE edition

for EE 306) ISBN-9781308560489 OR
Semiconductor Device and Analog Electronics (2 volume
EE edition for EE 306/EE308) ISBN-9781308560496
Please read the recommended sections in Jaeger & Blalock
BEFORE class.

REFERENCES: Microelectronic Circuits by Adel S. Sedra and Kenneth C.

Smith, 5th edition, Oxford, 2004
Microelectronic Circuits and devices by Mark
N.Horenstein, 2nd edition, Prentice Hall, 1996
Introduction to Digital Microelectronic Circuits by K.
Gopalan, Irwin, 1996.
Analysis and Design of Digital Integrated Circuits by D.A.
Hodges and H.G. Jackson, 2nd edition, McGraw Hill, 1988.
Physics of Semiconductor Devices by S. Sze, 2nd edition,
Wiley, 1984.
Microelectronic Devices by E.S. Yang, McGraw-Hill, 1988.

1
COURSE OUTLINE:
Week Class Book Page Topic Homework
No Data
1 9/23 Skim 1-16, 53,
96-98,
Thevenin Eq.
Introduction to Electronics
Ccts. from your
EE 112 Text
27-31 Op-Amp
2 9/26 479-500, HW1:
Electron and Holes in Semiconductors
Definition p. 506
9/28 488-500 Energy Bands 2.3, 2.4, 2.5, 2.7
9/30 492-509,
The Power of
Currents in Semiconductors
the Sun Slide
Show
3 10/3 Drift and Diffusion Currents in HW2:
492-509
Semiconductors p. 506-509
10/5 30-45 review PN Junction Diode Electrostatics 2.10, 2.26, 2.31,
10/7 44-56, 96-98 PN Junction Diode under Bias 2.42, 2.43, 2.47
4 10/10 Forward Bias, Reverse Bias, and HW3:
44-64
Breakdown Ch1: 33ab, 35ab,
10/12 7-16, 64-73, 36ac, 39ab, 42,
Four Diode Models for Circuit Analysis
96-98 pspice 44
10/14 16-27, 82-96 Wave shaping with Diode Circuits
5 10/17 510-512 Photo-Diodes, Solar Cells, and LEDs HW4:
10/19 MOS Capacitor, NMOS Channel Ch1: 1ab, 8a,9a,
227-243
Formation, Threshold Voltage, Body 10a,48, 53,
MOS-FET
Effect
10/21 243-251, 320- NMOS Transistor current vs. voltage
322, 451-452 characteristics and channel-length
MOS-FET modulation
6 10/24 250-265; 513- HW5:
PMOS Transistor, JFET
523 JFET Ch1: 58a, 85,
10/26 265-279 MOSFET Biasing Ch3: 3.2, 3.8,
10/28 Midterm 3.17
7 10/31 253-279, HW6:
MOSFET Biasing
415, 418-419 CH3: 9a, 13abc,
11/2 115-118, BJT- BJT Operation (Ebers-Moll, Gummel- 24, 34, 38
Model Poon,Transport)
11/4 115-117, 207-
BJT Operation and Models
209
8 11/7 136-156 BJT Models - Early Voltage HW7:
11/9 147-162,182- Ch3: 40, 41, 44
Biasing the BJT (DC) CE Amplifier Ch2: 2ab, 6
183, 415-419
11/11 Holiday -------------
9 11/14 156-189 Biasing the BJT (DC) CE Amplifier HW8:
11/16 156-194 Biasing the BJT (AC) Small Signal
Models

2
 11/18 Ch2: 13, 14, 20,
156-194, 203-
CE Amplifier 24
205
10 11/21 Holiday ------ HW9:
11/23 Holiday --------- Ch2: 9b, 29, 49,
11/25 Holiday --- 50a
Ch2: 58, 60, 65ac
11 11/28 156-194, 203-
CE Amplifier
205
11/30 348-352 Biasing the BJT (AC)
11/2 176-177, 262-
Transistor Biasing,
264
12 12.5 176-177, 262- Do not need to
Transistor Biasing,
264 turn in HW 10:
12/7 345-346 Current Mirrors Ch4: 69ac, 70abc
12/9 415-427 Current Mirrors Ch4: 80, 83
13 Final Two hour
Section 1: Wed 12/14 8-10am
exams
Section 2: Fri 12/16 8-10am
GRADING:
Mid-term Examination ........35%
Homework....15%
Final Examination....50%

HOMEWORK AND EXAMS:

Class participation and attendance will be counted according to attendant sheet,
homework, midterms, and final exam.
There will be one comprehensive 50min Mid-term Examinations and one 2-
hour final exam. No make-up exam will be given. If you must miss an exam,
make arrangements with me at least 3 weeks in advance.
Homework will be assigned weekly. It is due very Wednesday by 5pm. Late
homework will be graded 10% off per day.

MIS:
If you are experiencing any problems with this class please contact me immediately. It is
expected that your work will be conducted in a timely fashion, and we can expect this to
be a productive and enjoyable semester.

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 Table of Contents for custom Cal Poly EE 306 Books
Pages Origin Contents
Volume 1 Same for EE & CPE Versions
Franco's Organization, Motivation, Contents, and
1-6 Franco Preface
Advice
7-114 Franco Ch. 1 Diodes and the pn Junction
115-226 Franco Ch. 2 Bipolar Junction Transistors
227-337 Franco Ch. 3 MOS Field-Effect Transistors
338-477 Franco Ch. 4 Building Blocks for Analog Integrated Circuits
479-509 J&B Ch. 2 Solid-state Electronics
510-512 J&B Section 3.18 Photo diodes & Solar Cells (Missing LEDs )
513-523 J&B Section 4.11 Junction Field-Effect Transistor (JFET)
524-525 J&B Section 4.7.7 The Unified MOS Transistor Model
525-526 J&B Section 7.7.8 Sub threshold Conduction
527-547 Franco Index (Ch. 1-7)

Volume 2 Only in EE Version--For EE 308

552-643 Franco Ch. 5 Analog Integrated Circuits
644-764 Franco Ch. 6 Frequency and Time Responses
765-906 Franco Ch. 7 Feedback, Stability, and Noise

Comments about the EE 306 Textbook

Page Where Comment
The top graph (below the drawing) plots n, p (carrier concentrations) using a
logarithmic vertical scale.
41 Fig. 1.39
The bottom three graphs (charge density, electric field, and potential) present
data with linear vertical scales.

4
Comparison of Franco and Jaeger & Blalock conventions and notations:
Franco Jaeger & Blalock

Room temperature
Room temperature
T = 290 K
T = 300 K
VT = 25.0 mV
VT = 25.86 mV 26 mV
For Si at Room Temperature:
For Si at Room Temperature:
ni2 = 1020 cm-6
ni2 = 2 x 1020 cm-6
ni = 1010 cm-3
ni = 1.4 x 1010 cm-3
Equation 2.1 & Figure 2.4 pp.
Equations 1.20 & 1.21 p. 33
483-484
Carrier Mobilities Carrier Mobilities
Figure 1.37 p. 38 Figure 2.8 p. 493

Ideal Diode Model

Ideal Diode
Piecewise Linear Model for Constant Voltage Drop (CVD)
Diode Diode Model
Diode Equation Ideal Diode Law
Missing LEDs Section 3.18.3 LEDs
Missing Ebers-Moll or
Sections 5.2, 5.4, & 5.7
Transport Model