Professional Documents
Culture Documents
J Srinivasa Rao
Govt Polytechnic Kothagudem
Khammam
Microprocessor Fifth Generation Pentium
Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors 40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors 40 pins
First Generation Ability to address large memory spaces
Between 1971 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors 16 pins nesting
8 and 16 bit processors 40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are 2
multiplexed Intel 8085 (8 bit processor)
Microprocessor Functional blocks
4
Pins and signals
8086 Microprocessor
Pins and Signals Common signals
AD0-AD15 (Bidirectional)
Address/Data bus
6
A17/S4, A16/S3 Address/Status
MN/ MX
MINIMUM / MAXIMUM
TEST
READY
RESET (Input)
CLK
12
8086 Microprocessor
Pins and Signals Minimum mode signals
Pins 24 -31
DT/
(Data Transmit/ Receive) Output signal from the
processor to control the direction of data flow
through the data transceivers
Pins 24 -31
14
8086 Microprocessor
Pins and Signals Maximum mode signals
15
S0, S1 and S2 Signals
S2 S1 S0 Characteristics
Interrupt
0 0 0
acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive State
8086 Microprocessor
Pins and Signals Maximum mode signals
17
QS1 and QS2 Signals
19
Memory Interfacing
20
General Bus Operation
21
Architecture
8086 Microprocessor
Architecture
Segment
Registers
25
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
26
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
27
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
28
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
29
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
30
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
Instruction queue
A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.
31
8086 Microprocessor
Architecture Execution Unit (EU)
EU decodes and
executes instructions.
A decoder in the EU
control system
translates instructions.
and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 32
DX can be used as DH and DL
8086 Microprocessor
Architecture Execution Unit (EU)
33
8086 Microprocessor
Architecture Execution Unit (EU)
34
8086 Microprocessor
Architecture Execution Unit (EU)
Example:
35
8086 Microprocessor
Architecture Execution Unit (EU)
36
8086 Microprocessor
Architecture Execution Unit (EU)
37
8086 Microprocessor
Architecture Execution Unit (EU)
38
8086 Microprocessor
Architecture Execution Unit (EU)
39
8086 Microprocessor
Architecture Execution Unit (EU)
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1s ; for odd number
zero of 1s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
is 0, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 40
8086 Microprocessor
Architecture
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
into 4 groups OF DF IF TF SF ZF AF PF CF
Minimum mode:
AD11 5 36 A18/S5
AD10 6 35 A19/S6
the microprocessor.
AD0 16 25 ALE
NMI 17 24 INTA
Maximum mode
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Pull MN/MX logic 0
Larger systems with more than one
processor (designed to be used Lost Signals in
when a coprocessor (8087) exists
in the system) Max Mode
Minimum-mode and Maximum-mode Signals
GND 1 40 VCC
GND 1 40 VCC
AD14 2 39 AD15
AD14 2 39 AD15
AD13 3 38 A16/S3
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD9 7 34 BHE/S7
AD8 8 33 MN/MX Vcc AD8 8
8086
33 MN/MX
GND
AD7
AD6
9
10
8086 32
31
RD
HOLD
AD7
AD6
9
10
32
31
RD
RQ/GT0
AD5 11 30 RQ/GT1
AD5 11 30 HLDA
AD4 12 29 LOCK
AD4 12 29 WR
AD3 13 28 S2
AD3 13 28 M/IO
AD2 14 27 S1
AD2 14 27 DT/R
AD1 15 26 S0
AD1 15 26 DEN
AD0 16 25 QS0
AD0 16 25 ALE
NMI 17 24 QS1
NMI 17 24 INTA
INTR 18 23 TEST
INTR 18 23 TEST
CLK 19 22 READY
CLK 19 22 READY
GND 20 21 RESET
GND 20 21 RESET
AD7.
A8 8 8088 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD
By multiplexed we AD5
AD4
11
12
30
29
HLDA
WR
0 0 0 Code Access
0 0 1 Read Memory
0 1 0 Write Memory
0 1 1 Passive
1 0 0 Interrupt Acknowledge
1 0 1 Read I/O port
1 1 0 Write I/O port
1 1 1 Halt
8086 System Minimum mode
PCLK
+5V
Clock CLK M/IO
READY Control
generator INTA
RES RESET Bus
RD
AEN2 WR
AEN1
F/C MN/MX +5V
8086 CPU
8282
AD0-AD15 Latch
A16-A19
BHE BHE
D0 - D15
8286 16
DT/R T
DEN OE
8086 System Maximum Mode
+5V
MN/MX Gnd CLK MRDC
CLK
S0 S0
Clock READY MWTC
RES S1 S1
Bus Controller
generator AMWC
S2 S2
8288
RESET IORC
DEN IOWC
DT/R AIOWC
Wait-State ALE INTA
Generator
8086 CPU
STB A0 - A19
OE
Address Bus
AD0-AD15 8282
A16-A19 Latch BHE
T
OE DATA
8286
Transceiver
ADDRESSING MODES
&
Instruction set
ADDRESSING MODES
8086 Microprocessor
Addressing Modes
1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data
3. Direct Addressing
5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing memory data
7. Based Index Addressing
8. String Addressing
8. String Addressing
56
8086 Microprocessor Group I : Addressing modes for
Addressing Modes register and immediate data
1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL
8. String Addressing
MOV AX, 0A9FH
9. Direct I/O port Addressing
The 16-bit data (0A9FH) given in the instruction is
10. Indirect I/O port Addressing
moved to AX register
11. Relative Addressing
(AX) 0A9FH
12. Implied Addressing
57
8086 Microprocessor
Addressing Modes : Memory Access
1. Register Addressing
2. Immediate Addressing
Here, the effective address of the memory
3. Direct Addressing
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.
12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.
61
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
(CL) (MA)
(CH) (MA +1)
62
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
(AL) (MA)
63
(AH) (MA + 1)
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
(CL) (MA)
(CH) (MA + 1)
64
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
65
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
1. Register Addressing
2. Immediate Addressing
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
5. Based Addressing
6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
7. Based Index Addressing
operated by the instruction.
8. String Addressing
Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to zero.
10. Indirect I/O port Addressing
69
Addressing Modes for Control Transfer
Instruction
If the destination location lies in the same segment the mode is called
intrasegment mode.
70
Intrasegment Direct Mode: In this mode, the address to
which the control is to be transferred lies in the same segment
in which the control transfer instruction lies and appears
directly in the instruction as an immediate displacement value.
71
Intersegment Direct Mode: In this mode, the address to
which the control is to be transferred lies in the different
segment. This addressing mode provides a mean of branching
from one code segment to another code segment. Here, CS
and IP address are specified directly.
72
INSTRUCTION SET
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
3. Logical Instructions
74
8086 Microprocessor
Instruction Set
75
8086 Microprocessor
Instruction Set
76
8086 Microprocessor
Instruction Set
78
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP
ADD A, data
79
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP
ADDC A, data
80
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP
SUB A, data
81
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP
SBB A, data
82
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP
83
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP
84
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP
85
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP
86
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP
87
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP
88
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP
CMP A, data
89
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL
90
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL
91
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL
92
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL
93
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL
94
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL
95
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL
96
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL
97
8086 Microprocessor
Instruction Set
98
8086 Microprocessor
Instruction Set
REP
99
8086 Microprocessor
Instruction Set
MOVS
(MAE) (MA)
100
8086 Microprocessor
Instruction Set
CMPS
101
8086 Microprocessor
Instruction Set
LODS
103
8086 Microprocessor
Instruction Set
STOS
104
8086 Microprocessor
Instruction Set
CLC Clear CF 0
NOP No operation
Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine
106
8086 Microprocessor
Instruction Set
Checks flags
107
8086 Microprocessor
Instruction Set
Mnemonics Explanation
JC disp8 Jump if CF = 1
JP disp8 Jump if PF = 1
JO disp8 Jump if OF = 1
JS disp8 Jump if SF = 1
109
Assembler directives
8086 Microprocessor
Assemble Directives
Used to :
specify the start and end of a program
attach value to variables
allocate storage locations to input/ output data
define start and end of segments, procedures, macros etc..
111
8086 Microprocessor
Assemble Directives
DB Define Byte
PROC
FAR Example:
NEAR LIST DB 7FH, 42H, 35H
ENDP
Three consecutive memory locations are reserved for
SHORT the variable LIST and each data specified in the
instruction are stored as initial value in the reserved
MACRO memory location
ENDM 112
8086 Microprocessor
Assemble Directives
DB Define Word
PROC
FAR Example:
NEAR ALIST DW 6512H, 0F251H, 0CDE2H
ENDP
Six consecutive memory locations are reserved for
SHORT the variable ALIST and each 16-bit data specified in
the instruction is stored in two consecutive memory
MACRO location.
ENDM 113
8086 Microprocessor
Assemble Directives
ORG
END Segnam SEGMENT
EVEN
EQU Program code
or
PROC Data Defining Statements
FAR
NEAR
ENDP Segnam ENDS
SHORT
ORG
User defined name of
END Segment Register
the segment
EVEN
EQU
PROC Example:
FAR
NEAR ASSUME CS: ACODE, DS:ADATA Tells the compiler that the
ENDP instructions of the program are
stored in the segment ACODE and
data are stored in the segment
SHORT ADATA
MACRO
ENDM 115
8086 Microprocessor
Assemble Directives
ORG
Examples:
END
EVEN ORG 1000H Informs the assembler that the statements
EQU following ORG 1000H should be stored in
memory starting with effective address
1000H
PROC
FAR
LOOP EQU 10FEH Value of variable LOOP is 10FEH
NEAR
ENDP
_SDATA SEGMENT In this data segment, effective address of
SHORT ORG 1200H memory location assigned to A will be 1200H
A DB 4CH and that of B will be 1202H and 1203H.
EVEN
MACRO B DW 1052H
ENDM _SDATA ENDS 116
8086 Microprocessor
Assemble Directives
General form
ASSUME
ORG
procname PROC[NEAR/ FAR]
END
EVEN
Program statements of the
EQU procedure
DB
Examples:
DW
RET
ORG
ADD64 ENDP
END
EVEN
EQU CONVERT PROC FAR The subroutine/ procedure named CONVERT
is declared as FAR and so the assembler will
code the CALL and RET instructions involved
PROC in this procedure as far call and return
ENDP
FAR
RET
NEAR CONVERT ENDP
SHORT
MACRO
ENDM 118
8086 Microprocessor
Assemble Directives
PROC
ENDP
FAR
NEAR
SHORT
MACRO
ENDM 119
8086 Microprocessor
Assemble Directives
PROC
ENDP
FAR User defined name of
NEAR the macro
SHORT
MACRO
ENDM 120
121
Interfacing memory and i/o ports
8086 Microprocessor
Memory
Processor Memory
Registers inside a microcomputer
Store data and results temporarily
No speed disparity
Cost
Secondary Memory
Storage media comprising of slow
devices such as magnetic tapes and
disks
Hold large data files and programs:
Operating system, compilers,
databases, permanent programs etc. 123
8086 Microprocessor
Memory organization in 8086
8086 : 16-bit
Bank 0 : A0 = 0 Even
addressed memory bank
Bank 1 : = 0 Odd
addressed memory bank
124
8086 Microprocessor
Memory organization in 8086
126
8086 Microprocessor
Interfacing SRAM and EPROM
127
8086 Microprocessor
Interfacing SRAM and EPROM
128
8086 Microprocessor
Interfacing SRAM and EPROM
129
8086 Microprocessor
Interfacing SRAM and EPROM
Monitor Programs
Programing 8279 for keyboard scanning and display
refreshing
Initialization of stack
130
8086 Microprocessor
Interfacing I/O and peripheral devices
I/O devices
For communication between microprocessor and
outside world
Ports / Buffer ICs
Microprocessor I/ O devices
(interface circuitry)
Interrupt driven I/ O
I/O device interrupts the
processor and initiate data
transfer
Direct memory access
Data transfer is achieved by 131
bypassing the microprocessor
8086 Microprocessor
8086 and 8088 comparison
The I/O ports or peripherals can be Only IN and OUT instructions can be
treated like memory locations and used for data transfer between I/O
so all instructions related to device and processor
memory can be used for data
transmission between I/O device
and processor
Data can be moved from any Data transfer takes place only
register to ports and vice versa between accumulator and ports
When memory mapping is used for Full memory space can be used for
I/O devices, full memory address addressing memory.
space cannot be used for
addressing memory. Suitable for systems which
require large memory capacity
Useful only for small systems
where memory requirement is less
For accessing the memory mapped For accessing the I/O mapped
devices, the processor executes devices, the processor executes I/O
memory read or write cycle. read or write cycle.
8086 8088
16-bit Data bus lines obtained by 8-bit Data bus lines obtained by
demultiplexing AD0 AD15 demultiplexing AD0 AD7
In MIN mode, pin 28 is assigned the In MIN mode, pin 28 is assigned the
signal M / signal IO /