The blocks of Scicos-HDL 0.

The blocks of Scicos-HDL 0.4

Scicos-HDL is a tool to design digital circuit system; it integrates the

hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital
circuit design, simulation and Hardware Description Language generation. We
develop EMB for helping the hardware engineers and other digital system
engineers to design digital circuit faster and with lower cost. At present,
Scicos-HDL has sequential logic library, combinational logic library and IPcore
blocks, you can design interface circuit of digital system, micro-digital system.
We have been doing our best to improve Scicos-HDL; we expect that Scicos-
HDL can be as a Digital signal processing (DSP) system design tool in the
future. Supports VHDL&Verilog Language.

Introduction

We have developed 4 libraries for Scicos-HDL to design sequential logic circuit and
combinational logic circuit, what innovative thought in Scicos-HDL is that we combine Scicos,
Scicos-HDL with IPcore, this make Scicos and IPcore of EDA work together.

Libraries of Scicos-HDL

HDL_cmd library is the standard interface and simulation blocks of Scicos-HDL to design digital
system with the two compilers (vhdl/verilog compilers) in it. HDL_Combinational_Lib library and
HDL_Sequential_Lib are libraries of combinational and sequential blocks of digital system, and
we have the customized library HDL_IPcore which integrates the IP core.

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 The blocks of Scicos-HDL 0.4

HDL_Combinational_Lib library

This library has the basic components of digital system design, including Gate circuit,
Multiplexer, Encoder, adder,Decoder and BUS related components

Figure 1 Combinational logic library

BLOCKS:
1) encoder16_4

16 bit 4 bit encoder.

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 The blocks of Scicos-HDL 0.4

2) decoder7442

decoder7442.

3) decoder2_4

decoder2_4

4) encoder8421BCD

encoder8421BCD

5) encoder

Complex Encoder:
[4_2s (1).8421BCD (2).74147(3).74148(4)]

6) encoder4_2

encoder4_2

7) adder8

8 bit adder:
the u(1)---u(8) is for the a, and the u(9)---u(16) is for the b,
u(17) is the cin,;
y(1)y(8) is for the sum, y(9) is the cout .
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 The blocks of Scicos-HDL 0.4

8) andgate

And gate
The input port can be form 2 to 5

9) nandgate
Nand gate
The input port can be form 2 to 5

10) orgate

Or gate
The input port can be form 2 to 5

11) norgate

Nor gate
The input port can be form 2 to 5

12) notgate
Not gate

13) LineDemux

LineDemux
The output port can be form 1 to 8
When input port is 1, the out put is 1
When input port is 0, the out put is 0
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 The blocks of Scicos-HDL 0.4

14) showN

Demultiplexer 2-1

15) led driver

led driver

16) Demultiplexer

Demultiplexer 4-1

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 The blocks of Scicos-HDL 0.4

HDL_Sequential_Lib e library

This library includes D trigger,JK trigger,RS trigger without CR port, and D trigger,JK
trigger,RS trigger with CR port, 4-bit counter with self-set up,shift blocks.

Figure 2 Sequential logic lib

BLOCKS:
1) couter4
In port 1 clock input In port 2CR 1 is effective Out
ports 14From high bits to low, binary bit Red input portUsed
in the simulation

2) counter

3)

In port 1 clock input In port 2 CR 1 is

effective Out ports 14 From high bits to low,
binary bit Red input port Used in the
simulation,self-setup

4) shift left

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 The blocks of Scicos-HDL 0.4

8 bit shift left

5) shift right

8 bit shift right

6) D_trigger

D_trigger,
input port 1: clock ; input port 2:d

7) Dtriggers_cr

Dtriggers_cr
input port 1: clock ; input port 2:cr; input port
3:d;

8) JK_trigger

JK_trigger
input port 1: clock ; input port 2:j; input port 3:k;

9) JKtrigger_cr

JK_trigger
input port 1: clock ; input port 2:cr;
input port 3:j;input port 4:k;

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 The blocks of Scicos-HDL 0.4

10) RS_trigger

JK_trigger
input port 1: clock ; input port 2:s; input port
3:r;

11) RStrigger_cr

JK_trigger
input port 1: clock ; input port 2:cr;
input port 3:s; input port 4:r;
input port 2:s;

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 The blocks of Scicos-HDL 0.4

HDL_IPcore library

At present, we have Multiplexer, and decoder74138 and BUS related components.

Figure 3 Ipcore library

BLOCKS:
1) demuxBUS_3

demuxBUS_3:
u(1)u(2): 00->data1(u3-u10),
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01->data2(u10-u17) , others >data3(u18-u25)
 The blocks of Scicos-HDL 0.4

2) demuxBUS_2

demuxBUS_2:
u(1): 0->data1(u2-u9), 1->data2(u10-u17) .

3) muxBUS_3

muxBUS_2:
u(1)u(2): 00->out(u3-u10),
01->out(u10-u17) , others >out(u19-u25)

4) muxBUS_2

muxBUS_2:
u(1): 0->out(u2-u9), 1->out(u10-u17) ,

5) filter

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 The blocks of Scicos-HDL 0.4

Filter

6) dynamic filter

dynamic filter

7) parity check

Parity check

8) hamgen decoder

Hamgen decoder

9) hamdec incoder

Hamdec encoder

10) decoder 74138

decoder 74138

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 The blocks of Scicos-HDL 0.4

11) priority encoder

priority encoder

12) convert number

Convert number

13) complement number

Complement number

14) absolute value

Absolute value.

15) Demultiplexer

Demultiplexer 2-1

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 The blocks of Scicos-HDL 0.4

HDL_cmd

The standard interface and simulation blocks of Scicos-HDL to design digital system

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 The blocks of Scicos-HDL 0.4

Figure 4 Digital system design basic library

BLOCKS:

1) Scicos-HDL INput

This is the input port of Scicos-HDLthe number of the

block is equal to the one of the whole system input
portseach in-signal must through this block, it must
be in every model file.

2) Scicos-HDL OUTput

This is the output port of Scicos-HDL the number of

the block is equal to the one of the whole system
output ports each out-signal must through this
block, it must be in every model file.

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 The blocks of Scicos-HDL 0.4

3) electric level input

Scicos-HDL electric level input high

level1low level0

4) Scicos-HDL Clock

Scicos-HDL clock used in sequential logic

circuit

5) bit converter

Binary bit decimal bit converter -127~+127

6) bit converter

decimal bit Binary bit converter -127~+127

7) bit converter

Binary bit decimal bit converter 0~255

8) bit converter

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 The blocks of Scicos-HDL 0.4

decimal bit Binary bit converter 0~+255

9) bit converter

Binary bit decimal bit converter 0~16

10) bit converter

decimal bit Binary bit converter 0~16

11) Scicos-HDL numerical value

Scicos-HDL numerical value

12) Scicos-HDL VHDL compiler

Scicos-HDL VHDL compiler

decimal bit Binary bit converter 0~16

13) Scicos-HDL VHDL compiler

Scicos-HDL Verilog HDL compiler

Scicos-HDL numerical value

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 The blocks of Scicos-HDL 0.4

Scicos-HDL EMB Compiler

The compiler of Scicos-HDL--EMB Compiler, is the heart of Scicos-HDL, its

main function is to convert Scilab/Scicos model file to standard VHDL /
Verilog RTL code. And you can load these VHDL / Verilog codes to FPGA.

(I) How to operate the compiler

It must be at every model file, when the whole system is finished, click to start compiler, then
follow the dialog box will tell you how to finish..

(II) NOTE

Make sure you have put the block Scicos-HDL IN as the input ports, signals are
transferred in through this block;
Make sure you have put the block Scicos-HDL OUT as the output ports, signals
are transferred out through this block;
Self-connected is not allowed in every block;
If one output port is needed to be connected with many other blocks ,use the block
LineDemux of HDL_Combinational_Lib library;
Make sure the path and name of model file are correct as the rule in Scicos;
Make sure the directory of saving VHDL / Verilog code file is correct, empty or at
least without the same name to the model file you will compile;
Make sure no super block in the model file.

The VHDL / Verilog codes generated by compilers can be used in following EDA tools.
Synplify Pro 7.6, Quartus II,Mux+plus II ,ISE, Modelsim, etc.

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