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Input/OutputOperations
Input / Output Operations
ProgramcontrolledI/O
InterruptdrivenI/O
DirectmemoryaccessI/O
y /
Input/OutputInterface
Parallelinterface
Serialinterface
Input / Output (I/O) Operations ( 1 )
Input/Output(I/O)Operations(1)
Computers
ComputerscanperformI/Ooperationsto
can perform I/O operations to
exchangeinformationwithhumanoperators
and other devices
andotherdevices. Each I/O device is
assigned a unique set
of addresses
1234
1234 Data
Read
I/O Operations ( 2 )
I/OOperations(2)
Usually
Usually,theCPUmerelyactsasan
the CPU merely acts as an
intermediatepathwhenexecutinganI/O
instruction but the actual data transfer is
instructionbuttheactualdatatransferis
betweenmemoryunitandI/Odevices.
MemorymappedI/O
I/Odevicesandthememorysharethesameaddressspace
Anymachineinstructionthatcanaccessmemorycanbe
usedtotransferdatatoorfromanI/Odevice.
I/O Operations ( 3 )
I/OOperations(3)
Address lines
Bus Data lines
C t l lilines
Control
Theaddressdecoderenablesthedevicetorecognize
itsaddress.
Thedataregisterholdsthedatabeingtransferred.
ThestatusregistercontainsinformationfortheI/O
operations.
ThecontrolcircuitscoordinateI/Otransfers.
I/O Operations ( 4 )
I/OOperations(4)
The
ThespeedsofI/Odevicesaremuchslower
speeds of I/O devices are much slower
thanthatoftheprocessor,wemusthave
somemechanismstosynchronizethetransfer
ofdatabetweenthem.
Commonusedmechanismsforimplementing
I/Ooperations:
ProgramcontrolledI/O
InterruptdrivenI/O
DMAI/O
Programcontrolled
Program controlledI/O(1)
I/O ( 1 )
InprogramcontrolledI/O,theCPU
p g / ,
repeatedlychecks(polls)theI/Odevice
statusregistertoachievetherequired
synchronizationbetweentheCPUand
h b h d
theI/Odevice.
Commonly
Commonlyusedinlowend
used in low end
microprocessorssuchasembedded
systemsorinrealtimesystems.
Disadvantage theCPUwastesmostof
itstimebusywaitingforI/O.
Programcontrolled
Program controlledI/O(2)
I/O ( 2 )
Asimpleexample:Readincharacterinputfromakeyboard
A simple example: Read in character input from a keyboard
andproducecharacteroutputonadisplayscreen.
Bus
Processor
DATAIN DATAOUT
SIN SOUT
Keyboard
y Display
p y
Programcontrolled
Program controlledI/O(3)
I/O ( 3 ) Bus
Processor
DATAIN DATAOUT
SIN SOUT
DATAIN /DATAOUT:8bitdataregisters y
Keyboard Display
p y
SIN:astatuscontrolflag,SIN=1meansacharacterisenteredatthe
keyboardandisreadyforprocessortoread.
SOUT:astatuscontrolflag,SOUT=1meansthatthedisplayisready
toreceiveacharacter.
Thedataregistersandthestatusregisters(INSTATUS and
OUTSTATUS)containingthestatuscontrolflagsinbit3canbe
addressed as if they were memory locations
addressedasiftheywerememorylocations.
Programcontrolled
Program controlledI/O(4)
I/O ( 4 )
Aninputoperationfromthekeyboard.
1. iki k h i DATAIN
SStrikingakeystoresacharacterinDATAIN.
2. SIN issetto1.
3. TheprocessorcanmonitorSIN asfollows.
READ BTST.W #3,INSTATUS; wait for a character to be entered in
BEQQ READ ; the keyboard
y buffer DATAIN
MOVE.B DATAIN,D1 ; transfer the character from DATAIN
; into D1
4. WhenSIN issetto1,theprocessortransfersacharacterfromDATAIN toD1.
5. SIN isclearedto0.
6
6. If next character is entered at the keyboard SIN isagainsetto1.
Ifnextcharacterisenteredatthekeyboard,SIN is again set to 1
Programcontrolled
Program controlledI/O(5)
I/O ( 5 )
An output operation to the display
Anoutputoperationtothedisplay
1. TheprocessormonitorsSOUT asfollows.
WRITE BTST.W #3,OUTSTATUS ; wait for the display to become ready
BEQ WRITE
MOVE.B D1,DATAOUT ; move the character from D1 to the
; output buffer DATAOUT
2. WhenSOUT issetto1,theprocessortransfersacharacterfromD1 to
DATAOUT tobedisplayed.
3 SOUT isclearedto0.
3. is cleared to 0
4. Whenthedisplaydeviceisreadytoreceivethenextcharacter,SOUT is
againsetto1.
Interrupts ( 1 )
Interrupts(1)
Interruptisamechanismfordivertingthe
I t ti h i f di ti th
attentionofaprocessorwhenaparticular
eventoccurs,suchasI/Odevicerequests.
Interruptscauseabreakinthenormal
execution of a program
executionofaprogram.
Interrupts ( 2 )
Interrupts(2)
((i)) ExternalInterrupts
te a te upts
I/Odevicesrequesttransferofdata
atimingdeviceindicatesanelapsedtimeofeventor
exceededtimeallocationforanendlessloopingofa
program
externalhardwarecircuitssuchaspowersupply
external hardware circuits such as power supply
failure,systemresetorbuserror
asynchronousinoperationbetweendevices
eventdriven,independentoftheprogramin
execution
Interrupts ( 3 )
Interrupts(3)
(ii) Internal Interrupts (Traps)
arisefromillegalorerroneoususeofaninstructionor
data
examples:dividebyzero,stackoverflow
theinterruptserviceprogram(traphandler)
determines the corrective action to be taken e g
determinesthecorrectiveactiontobetaken,e.g.,
printanerrormessage
internalinterruptsareinitiatedbysomeexceptional
conditionscausedbyprogram
synchronousinoperationwiththeprogram
ifrerunprogram,eventwilloccurinthesameplace
if re run program event will occur in the same place
Interrupts ( 4 )
Interrupts(4)
(iii)SoftwareInterrupts
(iii) Software Interrupts
initiatedbyexecutingaprivilegedinstruction asaspecial
callinstruction(behavesasaninterrupt)
programmersoftenusesoftwareinterruptstoinitiatean
interruptprocedureatadesiredpointintheprogram
e.g.,aswitchfromtheusermode(userprogramexecution)to
supervisormodeforinputoroutputtransferoperationbymeans
ofasupervisorcallinstruction.Theuserprogrampasseddatato
thesystemprogram(supervisormode)tospecifytherequested
I/Otask.
Steps taken to process Interrupt ( 1 )
StepstakentoprocessInterrupt(1)
1. A deviceraisesaninterruptrequest
device raises an interrupt request bysendingahardware
by sending a hardware
signalinoneofthebuscontrollines,calledaninterrupt
requestline,totheprocessor.
2. Theprocessorcompletesexecutionofthecurrent
instruction.
3. Theprocessordetermines thedevicerequestinganinterrupt
andsendsaninterruptacknowledgesignaltothedevice.
4. Thedeviceremovesitsinterruptrequestsignal.
Steps taken to process Interrupt ( 2 )
StepstakentoprocessInterrupt(2)
5. Thestatusoftheprocessor(Statusregister)andthelocationof
thenextinstructiontobeexecuted(ProgramCounter)issavedon
theprocessorstack.
Theamountofinformationsavedautomaticallybythe
processorshouldbekepttoaminimumtoavoidlong
interruptlatency.
6. TheprocessorloadsthePCwiththeaddressofthefirst
instructionofthe InterruptServiceRoutine (ISR)associatedwith
( )
thedevice(causingtheinterrupt).
Steps taken to process Interrupt ( 3 )
StepstakentoprocessInterrupt(3)
7 ProcesstheISR.
7. Process the ISR
Anyadditionalinformationsuchasthecontentsoftheregisters
mustbesavedatthebeginningoftheISRandrestoredattheend
b d h b i i f h ISR d d h d
oftheISR.
8. Restorethestatusregisterandprogramcounter.
9. Resumetheexecutionoftheinterruptedprogram.
Determining Source of Interrupt ( 1 )
DeterminingSourceofInterrupt(1)
Ifanumberofdevicescapableofinitiating
If a number of devices capable of initiating
interruptsareconnectedtotheprocessor,
howcantheprocessorrecognizethedevice
requesting an interrupt?
requestinganinterrupt?
Determining Source of Interrupt ( 2 )
DeterminingSourceofInterrupt(2)
(i)Polling
() g
Whenadeviceraisesaninterruptrequest,itsetsan
interruptrequestbit(IRQ)initsstatusregisterto1.
Wheneveraninterruptisgenerated,alltheI/O
Whenever an interrupt is generated all the I/O
devicesarepolled.
ThefirstdevicewithitsIRQbitsetisthedevicetobe
ser iced
serviced.
Theorderinwhichthedevicesarepolleddetermines
theprioritiesofthedevices.
Advantage:simpleandeasytoimplement
Disadvantage:timeisspenttestingtheIRQbitsofall
the devices that may not be requesting any service.
thedevicesthatmaynotberequestinganyservice.
Determining Source of Interrupt ( 3 )
DeterminingSourceofInterrupt(3)
(ii) Vectoredinterrupts
V t di t t
Adevicerequestinganinterruptidentifiesitself
bysendinga vector totheprocessoruponthe
interrupt acknowledgement
interruptacknowledgement.
ThisvectorisusedasapointertotheISRforthat
device.
Determining Source of Interrupt ( 4 )
DeterminingSourceofInterrupt(4)
Toensureonlyonedeviceisselectedtosenditsvector,
y ,
devicescanbeconnectedtoformadaisychain.
INTR
Processsor
Theinterruptacknowledgesignalpropagatesserially
throughthedevices.
Thedevicewithapendingrequestforinterruptblocks
thesignalandsendsitsvectortotheprocessor.
Interrupt Driven I/O ( 1 )
InterruptDrivenI/O(1)
BetterthanprogrammedI/O,
buttoomanyinterruptsoccur
foreverybyte ofinputand
output.
Processinganinterruptis
expensive.
Interrupt Driven I/O ( 2 )
InterruptDrivenI/O(2)
Bus
Example:InaprogramcalledMAIN,
itreadsalinefromthekeyboard Processor
D ATAIN
IE
andstoreitinthememory,starting KIRQ
SIN
atlocationLINE. KEN
Keyboard
Example:
E l
TakingControl
Control Bus
CPU DMAC
signals
BR BR
BG BG
BGACK BGACK
BR
BG
BGACK
time
time
Legend:
L d
CPU cycle
DMA cycle
BR/BG/BGACK sequence
q
Types of I/O
TypesofI/O
ProgrammedI/O
Programmed I/O
InterruptdrivenI/O
Directmemoryaccess(DMA)
i ( )
CPU
DMAC
Memory
The CPU
prepares the
DMAC
Disk
DMA
Data bus
Address bus
Control bus
CPU
The transfer
DMAC takes place
Memory
Disk
InterruptdrivenI/O(inDMA)
Data bus
Address bus
Control bus
IRQ
CPU
Disk
Input/Output (I/O) Interfaces ( 1 )
Input/Output(I/O)Interfaces(1)
Ci
Circuitrytotransferdatabetweencomputerbus
it t t f d t b t t b
andanI/Odevice.Theinterfaceconnectstothe
bus signals (address data control) on one side
bussignals(address,data,control)ononeside,
withthedatapathandassociatedcontrolforthe
I/O device on the other side
I/Odeviceontheotherside.
Types of I/O interfaces
Parallel Interface
Serial Interface
Input/Output (I/O) Interfaces ( 2 )
Input/Output(I/O)Interfaces(2)
Parallel
Parallelinterfaceissuitablefordevicesthat
interface is suitable for devices that
arephysicallyclosetothecomputerbecause
theproblemoftimingskewlimitsthedata
ratesforlongerdistances.
Ontheotherhand,serial transmissionis
convenientforconnectingdevicesthatare
i tf ti d i th t
physicallyfarawayfromthecomputer
becauseitrequiresfewerwires.
Input/Output (I/O) Interfaces ( 3 )
Input/Output(I/O)Interfaces(3)
I/OInterfacefunctions:
(1)Providesastorage
(1) Provides a storage
(2)Containsstatusflagstobeaccessedbythe
processor
(3)Decodesaddressessentbytheprocessor
(4)Generatestimingsignalsforbuscontrol
(5)Performsformatconversionfordatatransfer
(5) Performs format conversion for data transfer
betweenbusandI/Odevice
Parallel Interface ( 1 )
ParallelInterface(1)
Aparallelinterfacetransfersdataintheform
A ll l i t f t f d t i th f
ofoneormorebytessimultaneouslytoor
fromthedevice.
Theinterfaceallowsdatainput(suchas
keyboard) or output (such as printer)
keyboard)oroutput(suchasprinter)
connectedtotheCPUthroughthebus.
Parallel Interface ( 2 )
ParallelInterface(2)
ParallelInput(Example:Keyboardinput)
Parallel Input (Example : Keyboard input)
Data
Address
DATAIN Data
Encoder
R/W and Keyboard
Processor SIN
debouncing switches
Master-ready circuit
Valid
Input
Slav e-ready
interface
(4) TheI/Ointerfaceisconnectedtotheasynchronousbus
onwhichtransfersarecontrolledusinghandshakesignals
(MasterreadyandSlaveready).
Parallel Interface ( 5 )
ParallelInterface(5)
ParallelOutput(Example:Printeroutput)
Parallel Output (Example : Printer output)
Data
Processor
CPU R/W SOUT Printer
Valid
Master-eady
Output Idle
Slave-ready interf ace
(2)TheI/Ointerfacecanthenplaceanewcharacteronthe
datalinesandactivatetheValidsignal.
(3)Theprinterstartsprintingthecharacterandnegatesthe
Idle signal that causes the interface to deactivate the Valid
Idlesignal,thatcausestheinterfacetodeactivatetheValid
signal.
Parallel Interface ( 7 )
ParallelInterface(7)
(4)TheinterfacecontainsaDATAOUT registerandastatus
flag,SOUT.TheSOUT flagissetto1whentheprinteris
readytoacceptanothercharacter,itisclearedto0whena
newcharacterisloadedintoDATAOUT bytheprocessor.
Serial Interface ( 1 )
SerialInterface(1)
Serial
Serialinterfacecircuit
interface circuit Input shift re gister
Serial
input
communicatesinaserial fashion
DATAIN
onthedevicesideandina
parallel fashiononthebusside.
Thetransformationbetweenthe
D7
parallelandserialformatsis :
D0
achievedwithshiftregistersthat
DATAOUT
haveparallelaccesscapability.
Serial
Output shift re gister output
Serial Interface ( 2 )
SerialInterface(2)
TheinputshiftregisteracceptsbitserialinputfromtheI/O
The input shift register accepts bitserial input from the I/O
device.Whenallbitsofdatahavebeenreceived,the
contents of this shift register are loaded in parallel into the
contentsofthisshiftregisterareloadedinparallelintothe
DATAIN register.
OutputdataintheDATAOUT registerareloadedintothe
outputshiftregister,fromwhichthebitsareshiftedoutand
senttotheI/Odevice.