module RX_FSM(

clock,
reset_n,
SYNC_detected,
EOP_detected,
RXactive,
strip_data,
RXvalid

);
input clock;
input reset_n;
input SYNC_detected;
//input data_en;
input EOP_detected;
//input receive_error;
//input idle;
output reg RXactive;
output reg RXvalid;
output reg strip_data;
//output reg RXerror;

parameter IDLE=2'd0,
strip_SYNC=2'd1,
RXDATA=2'd2,
strip_EOP=2'd3;
reg [1:0]current_state,next_state;
always @(posedge clock or negedge reset_n)
begin
if(!reset_n)
begin
current_state<=0;
end
else
begin
current_state<=next_state;
end
end
always @(*)
begin
case(current_state)
IDLE:
begin
if(reset_n)
next_state=strip_SYNC;
else
next_state=IDLE;
end
strip_SYNC:
begin
if(SYNC_detected)
next_state=RXDATA;
 else
next_state=strip_SYNC;
end
RXDATA:
begin
if(EOP_detected)
next_state=strip_EOP;
else
next_state=RXDATA;
end
strip_EOP:
begin
next_state=IDLE;
end
endcase
end
always @(*)
begin
case(current_state)
IDLE:
begin
RXactive=0;
RXvalid=0;
strip_data=0;
end

strip_SYNC:
begin
RXactive=1;
RXvalid=0;
strip_data=0;
end
RXDATA:
begin
RXactive=1;
RXvalid=1;
strip_data=1;
end
strip_EOP:
begin
RXactive=0;
RXvalid=0;
strip_data=0;
end
endcase
end
endmodule