FOURTH SEMESTER (INTERNAL-II) EXAMINATION, APRIL 2017

EE 204 : Digital Electronics & Logic Design

FOURTH SEMESTER (INTERNAL-II) EXAMINATION, APRIL 2017 Time: 60 mins Max Marks: 20
EE 204 : Digital Electronics & Logic Design
Time: 60 mins Max Marks: 20

1(a). (i) Draw the circuit of a Half Adder along with the truth table (2)
(ii)What is carry look ahead adder (3)
1(a). (i) Draw the circuit of a Half Adder along with the truth table (2)
(iii) Implement a 4:1 MUX (5)
(ii)What is carry look ahead adder (3)
(OR)
(iii) Implement a 4:1 MUX (5)
(OR)
1(b). (i) Explain the data distributor logic circuit (3)
(ii) Draw and explain the Full subtractor circuit(7)
1(b). (i) Explain the data distributor logic circuit (3)
(ii) Draw and explain the Full subtractor circuit(7)

2(a) (i) Differentiate between synchronous & asynchronous latches (2)

(ii) Differentiate between sequential & combinational circuits (3)
2(a) (i) Differentiate between synchronous & asynchronous latches (2)
(iii) what is meant by race around problem? How is it overcome? (5)
(ii) Differentiate between sequential & combinational circuits (3)
(iii) what is meant by race around problem? How is it overcome? (5)
(OR)
(OR)

2(b) (i) Write notes on shift registers. Explain SISO (3)

2(b) (i) Write notes on shift registers. Explain SISO (3)
(ii) Give the applications of flipflops.( 2)
(ii) Give the applications of flipflops. (2)
Write notes on the Conversion of JK to SR Flipflop & SR to D Flipflop (5)
Write notes on the Conversion of JK to SR Flipflop & SR to D Flipflop (5)

FOURTH SEMESTER (INTERNAL-II) EXAMINATION, APRIL 2017

EE 204 : Digital Electronics & Logic Design
 Time: 60 mins Max Marks: 20

FOURTH SEMESTER (INTERNAL-II) EXAMINATION, APRIL 2017

EE 204 : Digital Electronics & Logic Design
1(a). (i) Draw the circuit of a half subtractor along with the truth table (2)
Time: 60 mins Max Marks: 20
(ii)what is a fast adder (3)
(iii) Implement a 1 to 4 line DEMUX (5)

1(a). (i) Draw the circuit of a half subtractor along with the truth table (2)
(OR) (ii)what is a fast adder (3)
(iii) Implement a 1 to 4 line DEMUX (5)
1(b). (i) Explain the data selector logic circuit (3)
(ii) Draw and explain the Full adder circuit (7) (OR)

1(b). (i) Explain the data selector logic circuit (3)

2(a) (i) Differentiate between synchronous & asynchronous latches (2) (ii) Draw and explain the Full adder circuit (7)
(ii) Differentiate between sequential & combinational circuits (3)
(iii) Explain master slave flipflop. List the advantage. (5)

2(a) (i) Differentiate between synchronous & asynchronous latches (2)

(OR) (ii) Differentiate between sequential & combinational circuits (3)
(iii) Explain master slave flipflop. List the advantage. (5)
2(b) (i) What are shift registers. Explain SIPO (3)
(ii) Give the applications of flipflops. (2) (OR)
Write notes on the Conversion of JK to SR Flipflop & SR to D Flipflop (5)

2(b) (i) What are shift registers. Explain SIPO (3)

(ii) Give the applications of flipflops. (2)
Write notes on the Conversion of JK to SR Flipflop & SR to D Flipflop (5)