PD - 97034

IRF4905SPbF
IRF4905LPbF
Features HEXFET Power MOSFET
O Advanced Process Technology
D
O Ultra Low On-Resistance VDSS = -55V
O 150C Operating Temperature
O Fast Switching RDS(on) = 20m
O Repetitive Avalanche Allowed up to Tjmax G
O Some Parameters Are Differrent from
ID = -42A
IRF4905S S
O Lead-Free
Description D D
Features of this design are a 150C junction oper-
ating temperature, fast switching speed and im-
proved repetitive avalanche rating . These features S S
D D
combine to make this design an extremely efficient G G
and reliable device for use in a wide variety of other D2Pak TO-262
applications. IRF4905SPbF IRF4905LPbF

G D S
Gate Drain Source
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25C Continuous Drain Current, VGS @ 10V (Silicon Limited) -70
ID @ TC = 100C Continuous Drain Current, VGS @ 10V (Silicon Limited) -44 A
ID @ TC = 25C Continuous Drain Current, VGS @ 10V (Package Limited) -42
IDM Pulsed Drain Current c -280
PD @TC = 25C Power Dissipation 170 W
Linear Derating Factor 1.3 W/C
VGS Gate-to-Source Voltage 20 V
EAS (Thermally limited) Single Pulse Avalanche Energy d 140 mJ
EAS (Tested ) Single Pulse Avalanche Energy Tested Value h 790
IAR Avalanche Current c See Fig.12a, 12b, 15, 16 A
EAR Repetitive Avalanche Energy g mJ
TJ Operating Junction and -55 to + 150
TSTG Storage Temperature Range C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting Torque, 6-32 or M3 screw i y
10 lbf in (1.1N m) y
Thermal Resistance
Parameter Typ. Max. Units
RJC Junction-to-Case j 0.75
RJA Junction-to-Ambient (PCB Mount, steady state) ij 40
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IRF4905S/L
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage -55 V VGS = 0V, ID = -250A
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient -0.054 V/C Reference to 25C, ID = -1mA
RDS(on) Static Drain-to-Source On-Resistance 20 m VGS = -10V, ID = -42A e
VGS(th) Gate Threshold Voltage -2.0 -4.0 V VDS = VGS, ID = -250A
gfs Forward Transconductance 19 S VDS = -25V, ID = -42A
IDSS Drain-to-Source Leakage Current -25 A VDS = -55V, VGS = 0V
-200 VDS = -44V, VGS = 0V, TJ = 125C
IGSS Gate-to-Source Forward Leakage 100 nA VGS = -20V
Gate-to-Source Reverse Leakage -100 VGS = 20V
Qg Total Gate Charge 120 180 ID = -42A
Qgs Gate-to-Source Charge 32 nC VDS = -44V
Qgd Gate-to-Drain ("Miller") Charge 53 VGS = -10V e
td(on) Turn-On Delay Time 20 VDD = -28V
tr Rise Time 99 ID = -42A
td(off) Turn-Off Delay Time 51 ns RG = 2.6
tf Fall Time 64 VGS = -10V e
LS Internal Source Inductance 7.5 nH Between lead,
and center of die contact
Ciss Input Capacitance 3500 VGS = 0V
Coss Output Capacitance 1250 VDS = -25V
Crss Reverse Transfer Capacitance 450 pF = 1.0MHz
Coss Output Capacitance 4620 VGS = 0V, VDS = -1.0V, = 1.0MHz
Coss Output Capacitance 940 VGS = 0V, VDS = -44V, = 1.0MHz
Coss eff. Effective Output Capacitance 1530 VGS = 0V, VDS = 0V to -44V f
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current -42 MOSFET symbol
(Body Diode) A showing the
ISM Pulsed Source Current -280 integral reverse
(Body Diode) c p-n junction diode.
VSD Diode Forward Voltage -1.3 V TJ = 25C, IS = -42A, VGS = 0V e
trr Reverse Recovery Time 61 92 ns TJ = 25C, IF = -42A, VDD = -28V
Qrr Reverse Recovery Charge 150 220 nC di/dt = -100A/s e
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

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 IRF4905S/L

1000 1000
VGS VGS
TOP -15V TOP -15V
-10V -10V
-ID, Drain-to-Source Current (A)

-ID, Drain-to-Source Current (A)

-8.0V -8.0V
-7.0V -7.0V
-6.0V -6.0V
-5.5V -5.5V
100 -5.0V 100 -5.0V
BOTTOM -4.5V BOTTOM -4.5V

10 10
-4.5V

-4.5V
60s PULSE WIDTH 60s PULSE WIDTH
Tj = 25C Tj = 150C
1 1
0.1 1 10 100 1000 0.1 1 10 100 1000

-VDS , Drain-to-Source Voltage (V) -VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000.0 40
TJ = 25C TJ = 25C
Gfs, Forward Transconductance (S)
-ID, Drain-to-Source Current()

100.0 TJ = 150C
30

TJ = 150C
10.0
20

1.0
10
VDS = -25V
VDS = -10V
60s PULSE WIDTH
0.1 380s PULSE WIDTH
3 4 5 6 7 8 9 10 11 12 13 14 0
0 20 40 60 80
-VGS, Gate-to-Source Voltage (V)
-ID, Drain-to-Source Current (A)

Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance

Vs. Drain Current
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 IRF4905S/L

7000 20
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED ID= -42A

-VGS, Gate-to-Source Voltage (V)

6000 Crss = Cgd VDS = -44V
16 VDS= -28V
Coss = Cds + Cgd
5000 VDS= -11V
C, Capacitance (pF)

Ciss 12
4000

3000 8
Coss
2000
4
1000 Crss

0
0
1 10 100
0 40 80 120 160 200
QG Total Gate Charge (nC)
-VDS , Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000.0 1000
OPERATION IN THIS AREA
LIMITED BY R DS (on)
-ID, Drain-to-Source Current (A)
-ISD , Reverse Drain Current (A)

100.0

TJ = 150C 100 100sec

1msec

10.0
10msec

10 LIMITED BY PACKAGE
TJ = 25C
1.0 DC
Tc = 25C
Tj = 150C
VGS = 0V Single Pulse
0.1 1
0.0 0.4 0.8 1.2 1.6 2.0 0 1 10 100
-VSD , Source-to-Drain Voltage (V) -VDS , Drain-toSource Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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 IRF4905S/L

80 2.0
ID = -42A

RDS(on) , Drain-to-Source On Resistance

LIMITED BY PACKAGE
VGS = -10V

60
-ID , Drain Current (A)

1.5

(Normalized)
40

1.0
20

0
0.5
25 50 75 100 125 150
-60 -40 -20 0 20 40 60 80 100 120 140 160
TC , Case Temperature (C)
TJ , Junction Temperature (C)

Fig 9. Maximum Drain Current Vs. Fig 10. Normalized On-Resistance

Case Temperature Vs. Temperature

D = 0.50
Thermal Response ( Z thJC )

0.20
0.1
0.10
R1 R2 R3
0.05 R1 R2 R3 Ri (C/W) i (sec)
J
J C

0.1165 0.000068
0.02 1 2 3
0.01
1 2 3 0.3734 0.002347
0.01
Ci= i/Ri 0.2608 0.014811
Ci i/Ri

Notes:
SINGLE PULSE
1. Duty Factor D = t1/t2
( THERMAL RESPONSE )
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRF4905S/L
VDS L

600

EAS, Single Pulse Avalanche Energy (mJ)

RG D.U.T ID
VDD
500 TOP -17A
IAS A
DRIVER -30A
-20V
tp 0.01 BOTTOM -42A
400

300
15V

200
Fig 12a. Unclamped Inductive Test Circuit
I AS 100

0
25 50 75 100 125 150

Starting TJ, Junction Temperature (C)

tp
V(BR)DSS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current

QG

10V 3.6
QGS QGD
-VGS(th) Gate threshold Voltage (V)

VG
3.2

Charge
ID = -250A
Fig 13a. Basic Gate Charge Waveform 2.8
Current Regulator
Same Type as D.U.T.

50K
2.4
12V .2F
.3F
-

D.U.T. +VDS
2.0
VGS -75 -50 -25 0 25 50 75 100 125 150
-3mA TJ , Temperature ( C )

IG ID
Current Sampling Resistors

Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage Vs. Temperature
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 IRF4905S/L

1000

Duty Cycle = Single Pulse

100
Allowed avalanche Current vs
Avalanche Current (A)

0.01 avalanche pulsewidth, tav

assuming Tj = 25C due to
0.05 avalanche losses. Note: In no
10 0.10 case should Tj be allowed to
exceed Tjmax

0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 15. Typical Avalanche Current Vs.Pulsewidth

160 Notes on Repetitive Avalanche Curves , Figures 15, 16:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 1% Duty Cycle 1. Avalanche failures assumption:
ID = -42A Purely a thermal phenomenon and failure occurs at a
EAR , Avalanche Energy (mJ)

120 temperature far in excess of Tjmax. This is validated for

every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
80 3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
40
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25C in Figure 15, 16).
0
tav = Average time in avalanche.
25 50 75 100 125 150 D = Duty cycle in avalanche = tav f
Starting TJ , Junction Temperature (C) ZthJC(D, tav) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3BVIav) = DT/ ZthJC

Fig 16. Maximum Avalanche Energy Iav = 2DT/ [1.3BVZth]
Vs. Temperature EAS (AR) = PD (ave)tav
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IRF4905S/L

Driver Gate Drive

P.W.
D.U.T** + P.W.
Period D=
Period

*
VGS=10V
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
- Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
Recovery Body Diode Forward
-
+ Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD

RG dv/dt controlled by RG VDD Re-Applied

Driver same type as D.U.T. + Voltage Body Diode Forward Drop
ISD controlled by Duty Factor "D" - Inductor Curent
D.U.T. - Device Under Test

Ripple 5% ISD

** Reverse Polarity of D.U.T for P-Channel * VGS = 5V for Logic Level Devices

Fig 17. Peak Diode Recovery dv/dt Test Circuit for P-Channel
HEXFET Power MOSFETs

RD
VDS

VGS
D.U.T.
RG -
+ VDD

VGS
Pulse Width 1 s
Duty Factor 0.1 %

Fig 18a. Switching Time Test Circuit

td(on) tr t d(off) tf
VGS
10%

90%
VDS

Fig 18b. Switching Time Waveforms

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 IRF4905S/L

D2Pak Package Outline (Dimensions are shown in millimeters (inches))

D2Pak Part Marking Information

T HIS IS AN IRF530S WIT H PART NUMBER
LOT CODE 8024 INT ERNAT IONAL
AS S EMBLED ON WW 02, 2000 RECT IFIER F530S
IN T HE AS S EMBLY LINE "L" LOGO
DAT E CODE
Note: "P" in assembly line YEAR 0 = 2000
position indicates "Lead-Free" AS S EMBLY
LOT CODE WEEK 02
LINE L

OR PART NUMBER
INT ERNAT IONAL
RECT IFIER F530S
LOGO
DAT E CODE
P = DES IGNAT ES LEAD-FREE
AS S EMBLY PRODUCT (OPT IONAL)
LOT CODE YEAR 0 = 2000
WEEK 02
A = AS S EMBLY S IT E CODE

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IRF4905S/L
TO-262 Package Outline (Dimensions are shown in millimeters (inches))

IGBT
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR

TO-262 Part Marking Information

EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789 PART NUMBER
INT ERNAT IONAL
AS SEMBLED ON WW 19, 1997
RECT IFIER
IN T HE AS SEMBLY LINE "C" LOGO
DAT E CODE
Note: "P" in ass embly line
pos ition indicates "Lead-Free" YEAR 7 = 1997
AS S EMBLY
LOT CODE WEEK 19
LINE C

OR
PART NUMBER
INT ERNAT IONAL
RECT IFIER
LOGO
DAT E CODE
P = DES IGNAT ES LEAD-FREE
AS S EMBLY PRODUCT (OPT IONAL)
LOT CODE YEAR 7 = 1997
WEEK 19
A = AS SEMBLY SIT E CODE

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 IRF4905S/L
D2Pak Tape & Reel Information
TRR

1.60 (.063)
1.50 (.059)
1.60 (.063)
4.10 (.161) 1.50 (.059)
3.90 (.153) 0.368 (.0145)
0.342 (.0135)

FEED DIRECTION 1.85 (.073) 11.60 (.457)

1.65 (.065) 11.40 (.449) 24.30 (.957)
15.42 (.609)
23.90 (.941)
15.22 (.601)
TRL
1.75 (.069)
10.90 (.429) 1.25 (.049)
10.70 (.421) 4.72 (.136)
16.10 (.634) 4.52 (.178)
15.90 (.626)

FEED DIRECTION

13.50 (.532) 27.40 (1.079)

12.80 (.504) 23.90 (.941)

330.00 60.00 (2.362)

(14.173) MIN.
MAX.

30.40 (1.197)
NOTES : MAX.
1. COMFORMS TO EIA-418. 26.40 (1.039) 4
2. CONTROLLING DIMENSION: MILLIMETER. 24.40 (.961)
3. DIMENSION MEASURED @ HUB.
3
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25C, L = 0.16mH This value determined from sample failure population. 100%
RG = 25, IAS = -42A, VGS =-10V. Part not
recommended for use above this value.
Pulse width 1.0ms; duty cycle 2%.
Coss eff. is a fixed capacitance that gives the
same charging time as Coss while VDS is rising
from 0 to 80% VDSS .
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
tested to this value in production.
This is applied to D2Pak, when mounted on 1" square PCB (FR-
4 or G-10 Material). For recommended footprint and soldering
techniques refer to application note #AN-994.
R is measured at TJ approximately 90C

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IRs Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 08/05
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/