Professional Documents
Culture Documents
CLK
MNc1
A B
Mukendra Kumar, Electronics & Telecommunication, C.S.V.T.U
Bhilai/ Shri Shnkaracharya Group Of Institutions(FET) , Raipur, India, Gnd
9753227225. A B
40 www.erpublication.org
Low Power and High Performance Dynamic CMOS XOR/XNOR Gate Design Using Body Bias Technique
B. Dynamic XOR/XNOR using PMOS (DXP) and high speed with smaller layout area as compared to DXN
This dynamic XOR gate replace NMOS evaluation and DXP.
Vdd Vdd
network by PMOS evaluation network. Fig.2 shows the
design of dynamic XOR/XNOR using PMOS (DXP). Here, P keeper
MPc1 MPk
DXP generates output XOR/XNOR signal using pull-up
Vdd
PMOS network in evaluation phase. But DXP offers superior Vn Dynamic node
leakage characteristics as compared to DXN because of the
higher barrier height of holes tunneling from the conduction A MN1 B MN3 MPr1
band than the electron tunneling form the valance band [9,
Hybrid
15]. Therefore, PMOS transistor produces smaller gate network
XOR_out
leakage current. But the evaluation speed of the DXN is
B MP2 A MP4
faster than the DXP due to higher mobility of electron than MNr1
CLK
MNc1
Vdd
XNOR_out
Gnd
Vdd
MPc1
Fig.3 Dynamic XOR/XNOR using Hybrid pull down
network with fixed threshold (DXH)
MPr2
Fig.2 Dynamic XOR/XNOR using PMOS pull-up Objective of work: To improve the performance of SRAM
network (DXP) cell following parameters need to be considered:
1. Smaller read delay
2. Smaller leakage power
C. Dynamic XOR/XNOR using Hybrid network (DXH) 3. Smaller dynamic power
Previously existing DXN and DXP design, either offer 4. Smaller layout area
higher speed or offer smaller leakage power. But, both are
equally important in single design. Therefore, DXH is Design Logic Explanation: fixed body bias offers fixed
designed to obtain this design objective. Fig.3 shows the threshold in precharge and evaluation phase. This may offers
design of dynamic XOR/XNOR using hybrid of NMOS and higher power dissipation or time delay depends on threshold
PMOS (DXH). The hybrid network is placed in the PDN of MOS. Practically, we expect that in evaluation phase
which is designed using NMOS and PMOS [5, 6, and 15]. when dynamic node discharge to ground PMOS offers
This design obtains low leakage power, low dynamic power smaller threshold otherwise PMOS offers higher threshold in
dissipation and high speed with smaller layout area. evaluation network. Therefore, this work is going to design a
XOR gate that offer higher speed and lower power
Here additional inverters are not required to obtain dissipation. This is possible by varying the body to source
inverted input of input vector (A, B). During precharge voltage of PMOS by using input.
phase, dynamic node Vn is charged to supply voltage
through transistor MPc1 and XOR_out set to low voltage. Evaluation Delay: This is the time difference between
During evaluation phase, if input vectors (0, 1) or (1, 0) is changes in the states of the clock to the change in XOR gate
applied, dynamic node is discharged to low voltage and output.
XOR_out is charged to high voltage. While input vector (0,
0) or (1, 1) is applied, dynamic node preserved its high state Leakage Power: whenever device operate in idle state, the
and output node is discharged to low voltage. This design power consume by gate is equivalent to leakage power. This
obtains low leakage power, low dynamic power dissipation is depends on sub threshold leakage, gate leakage and body
leakage.
41 www.erpublication.org
International Journal of Engineering and Technical Research (IJETR)
ISSN: 2321-0869 (O) 2454-4698 (P), Volume-3, Issue-11, November 2015
Dynamic Power dissipation: Total power dissipation is a A. ACTIVE POWER DISSIPATION AND DELAY
sum of static and dynamic power. Whenever, XOR gate in MEASURMENT
running state dynamic power dominate while cell in idle state The active power is evaluated using average power
leakage power dominate. Here, Average power dissipation consumption takes place during 4nSec interval. The delay is
equivalent to dynamic power. defined as the time required changing in output vector
Layout Area: Area occupied on silicon wafer according to XOR_OUT with respect to change in input vector CLK. The
lambda rule, is called layout area. delay estimation of DXGN, DXGP, DXGH and Proposed
are shown in Fig.5, Fig.6, Fig.7 and Fig.8
B. Proposed Circuit respectively
This technique adopt NMOS and PMOS transistor to form
hybrid network as shown in Fig.4. In this design series
combination of transistor pair N1, P2 and transistor pair N3,
P4 is connected in parallel [Ref]. The gate and body terminal
of P2 connected with input A and B respectively while gate
and body terminal of P4 connected with input B and A
respectively. This cross body bias speed up dynamic gate and
reduce dynamic power consumption
Vdd Vdd
P keeper
Pc1 Pk
Vdd
Vn Dynamic node
Hybrid
network
XOR_out
P2 P4
B A A B Nr1
Vc XNOR_out Gnd
CLK
Nc1
Gnd
42 www.erpublication.org
Low Power and High Performance Dynamic CMOS XOR/XNOR Gate Design Using Body Bias Technique
ACKNOWLEDGMENT
The result of this proposed circuit gives us so much
pleasure. I would like to express my sincere gratitude to my
project guide Mr. Khemraj Deshmukh for giving me the
opportunity and guideline to work on that. It would never be
possible for us to take this project to this level without his
innovative ideas and his relentless support and
encouragement.
REFERENCES
0
Fig.8 Delay Measurement of Proposed at 25 C [1] B., Stackhouse, S., Bhimji, C., Bostak, A 65 nm 2-Billion Transistor
Quad-Core Itanium Processor, IEEE Journal of Solid-State Circuits,
44 (1) (2009) 1831.
[2] H. Kaul, M.A. Anders, S.K. Mathew, A 320 mV 56 W 411
Design DXGN DXGP DXGH Proposed
GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65
Parameters nm CMOS, IEEE Journal of Solid-State Circuits, 44 (1) (2009)
Delay(psec) 28.8 28.16 32.4 33.5 107-114.
Power 7.2538 12.171 6.4123 5.9452 [3] Ying.-Haw. Shu, S. Tenqchen, Ming.-Chang. Sun, Wu.-Shiung. Feng,
XNOR-based double-edge-triggered flip-flop for two-phase
Dissipation( pipelines, IEEE Transactions on Circuits and Systems, 53 (2) (2006)
uW) 138142.
14
Power Dissipation(uW)
[4] Goel. Sumeer, Design methodologies for high-performance
Power Dissipation(uW)
43 www.erpublication.org