Microprocessing

and
Microprogramming
EISEVIER Microprocessing and Microprogramming 41 (1996) 68 I-689

Modelling and performance assessment of large ATM switching

networks on loosely-coupled parallel processors
W. Liu a, E. Dirkx a, G. Petit b, J. Tiberghien a**
a Vrije Universiteit Brussel, Dept. INFO, Pleinhan 2, B-1050 Brussel, Belgium
b Trajic Technology Dept., Research Centre, Bell Telephone Co., F. Wellesplein I, B-2018 Antwerpen, Belgium

Received 22 February 1995; revised 6 April 1995; accepted IO October 1995

Abstract

A parallel simulation tool has been developed with the aim of evaluating the performance of a class of ATM switching
systems. In this paper, the class of ATM switching networks of interest and the corresponding modelling are addressed. An
appropriate decomposition scheme is revealed with respect to the model being built. The performance of the parallel tool is
examined, based on a scalable ATM switching network, by means of a loosely-coupled parallel computer system. A
combination of general purpose and problem specific algorithms results in a high computational efficiency, portability and
scalability.

Keywords: Parallel simulation; Performance evaluation; Asynchronous transfer mode

1. Introduction Telecommunications Union (ITU). The performance

Many architectures of the Asynchronous Transfer
Mode (ATM) switching system have been proposed
in literature since ATM is chosen as the transfer
mode for implementing Broadband Integrated Ser-
vices Digital Networks (BISDN) by the International
l Communicating author. Email: jgtiberg@info.vub.ac.be
of such a switching network should be evaluated in
order to make sure that the design and implementa-
tion will satisfy the future communication require-
ments. Two general approaches are available to eval-
uate the performance of digital switching systems:
analytic and simulation techniques. The former anal-
yses the model of a system design mathematically or
with computer-aided numerical methods. The latter
simulates the system behaviour by means of com-
puter(s), and global performance parameters are

0165~6074/96/$15.00 0 1996 Elsevier Science B.V. All rights reserved

SD/ 0165-6074(96)00029- 1
682 W. Liu et al./Microprocessing
measured during simulated operation of the system
under study.
Analytic techniques are able to reflect the rela-
tionships of system-characteristic parameters intu-
itively over a wide variety of operating conditions.
Its functional range is however restricted to a high
degree of abstraction due to unrealistic assumptions,
and many approximations are necessary to keep a
model tractable. It proves to be very difficult to
analyse complex systems such as large-scale multi-
stage ATM switching networks at a very low level
(i.e. highly detailed) with the current analytic ap-
proach. Simulation techniques on the contrary are
more flexible and can be applied to a wide area of
applications in arbitrary degree of detail. A disadvan-
tage is that a simulation consumes a large amount of
CPU time, even for a modest problem. Hence, with-
out strong enough computing power, simulation
techniques are also not applicable to a complicated
system. The only cost-effective solution to this
dilemma is to partition the system under study into a
number of components and execute them in parallel
on a multicomputer system.
To implement a parallel simulation, it is necessary
to decompose the system under study to a set of
executable components that can be simulated concur-
rently. The decomposition of an application can be
done according to parallel heuristics such as pipelin-
ing [1,2], farming [3] and/or data level techniques
for Parallel Discrete Event Simulation (PDES) such
as the Chandy-Misra algorithm [4,5] and the Time-
Warp algorithm 161.
In the following, the modelling of a class of ATM
switching networks of interest is first addressed in
Section 2. Section 3 then approaches the appropriate
algorithms for the model under study. The imple-
mentation of the strategy on a MIMD parallel com-
puter resulted in a general purpose, yet highly effi-
cient software tool. The performance of the parallel
tool implemented is examined, in Section 4, based
on a scalable ATM switching network. At last, some
remarks are given in Section 5 to conclude the paper.
and Microprogramming 41 (1996) 681-689
2. System modelling
An ATM switch will be capable of handling a
minimum of several hundreds of thousands of cells
per second at every input line [8,9]. Such a switch is
designed to be able to route all cells from their input
lines to their requested output lines with low enough
possibility for cell loss and unbearable cell delay,
while preserving the correct cell order for individual
virtual connections. The switches, having been pro-
posed in the literature, take various architectures,
with the size ranging from a few ports to thousands
of ports. Each switch port will typically work with
the transmission rate of 155 Mbit/s or higher. The
technology used in implementing the switch places
certain limitations on the size of the switch and line
speed; thus to build large switches, many modules
are interconnected in a multistage configuration [lo].
The time-division switches [9] allow several in-
put-output connections to share the same physical
resource, say a conducting medium or memory, based
on discrete time slot. A memory module is a typical
example for implementing connections based on time
division. Such a memory module is the repository in
which cells are supplied by input ports and removed
by output ports. The switching principle is similar to
the Time Slot Interchange (TSI) mechanism [l 11 for
synchronous Time Division Multiplexing (TDM). A
controller is required to sequentially process all in-
coming cells and select all outgoing cells in each
time cycle. This class of switches, with buffer mem-
ory in basic switching blocks to solve cell output
conflict, is intended to construct large switching
systems. Many proposed architectures fall into this
class in order to construct a scalable ATM switch
(e.g. [13-161).
2.1. Fabrics with shared memory
It is our intention to develop a simulation tool to
evaluate the performance of a class of ATM switch
architectures with shared memory. The previous work
 W. Liu et al./ Microprocessing and Microprogramming 41 (1996) 681-689
has proven that output buffer can achieve better
switch performance, e.g. higher throughput, than in-
put buffer, and shared output buffer will utilise
buffer memory more efficient than separate output
buffers for all traffic patterns [ 13,171. Shared buffer
type switches are very attractive and many imple-
mented prototypes use them as the building blocks
for large switch fabrics. The building blocks, or
Switching Elements @Es), are organised in ‘stages’,
with interconnection restricted to adjacent stages. In
a k-stage network, the inputs are connected to SEs in
stage 0, while the outputs are connected to SEs in
stage k-l.
Besides adopting shared memory within SEs, the
class of ATM switch systems have the following
characteristics:
(1) The switch fabrics are scalable with Clos topol-
ogy Dl;
(2) multipaths are available for cells;
(3) cells are synchronised with the certain interval of
each time cycle;
(4) cells are routed with respect to the self-routing
tag in the fabrics.
The simulation model for the class of ATM switch
architectures involves a series of modules: the source,
the interface, the SEs, the queueing and routing
management, and the analysis.
2.2. Data flow
ATM cells are generated at the source and flow
towards the switch fabric via external links. How-
ever, the internal packet format is required in order
to support the self-routing protocol within a switch
fabric. At the switch interface, a self-routing tag is
added to each ATM cell according to its VP1 and
VCI. This tag points out the appropriate outlet to-
wards the cell’s destination. Together with the tag
and other control information, an ATM cell is con-
verted to an internal packet. Such a packet will
traverse the switch fabric one stage at a time until it
683
reaches the requested outlet. Thus, the cell traffic
forms a unidirectional data flow.
When arriving at an SE, an internal cell will be
buffered in the shared memory. The cell may be sent
out immediately if the requested output link is free at
the time cycle; otherwise, it has to stay in the
corresponding logical queue and wait for its turn to
go. Each logical queue is applied with First-In First-
Out (FIFO) discipline, even though the buffer is
shared by several of such queues. An SE at different
stages may have a different routing mode, which
results in a different number of output links in a
routing group. An incoming cell would be lost if the
buffer had been fully occupied in an SE.
At the output side of the switch interface, internal
cells may stay in a resequencing buffer with an
engineerable constant delay in order to compensate
for distinct cell transfer delay due to multiple paths.
When a cell has waited long enough, it will be
delivered to the output buffer, where the internal
cells are depacketized into ATM cells.
2.3. Performance indices
The performance indices of ATM switching net-
works involve throughput, connection blocking prob-
ability, cell loss probability, cell insertion probabil-
ity, bit error rate, switching delay, and jitter on the
delay [ 121. We concentrate mainly on two perfor-
mance indices in the model of the ATM switching
systems: the cell loss probability and the switching
delay, though other parameters are also measured
(throughput, average link load, packet resequence
mechanism, etc.>.
Cells may be lost due to the resource shortage
inside an ATM switch fabric. Cells entering from
different input ports can compete the same output
port at the same cycle in an SE, i.e., a cell outputs
conflict. For the ATM switch fabric to be modelled,
buffers are used to relieve the cell contention at
routing spots. However, severe congestion may cause
buffer memory overflow, and thus result in the loss
684 W. Liu et al. / Microprocessing and Microprogramming 41 (1996) 681-689
of the incoming cells at the moment. The cell loss
probability is an important performance metric for an
ATM switch because it must be restricted to a
certain quantity for a class of communication ser-
vices. In fact, it is the key parameter for determining
the buffer memory size of the individual SEs. If the
size is too large, precious network resources would
be wasted and the implementation becomes more
complicated; if it is too small, cell loss ratio would
increase so that the network could not guarantee the
Quality Of Service (QOS> requirements for user
applications. A satisfactory size of the buffer mem-
ory can only be determined by means of very de-
tailed evaluation of the internal operation of the
switching network.
Switching delay and delay jitter are other impor-
tant performance indices for ATM switching net-
works. The ATM techniques multiply a diverse mix
of sources on a single transmitting medium. Real-time
messages such as voice are very sensitive to the
delay and delay variation. Cell switching delay can
be affected by many factors: link load, cell arrival
patterns, cell congestion, and so on. Again a mea-
surement can be made based on very detailed evalua-
tion of the internal operation of the switching net-
work.
3. Distributed simulation architecture
In order to obtain details about the performance of
the ATM switch under study, a very small time unit
should be used to describe the simulation progress.
With large quantities of high-speed cells being han-
dled inside, huge computing power and large mem-
ory space are required when simulating a large scale
switching network. The conventional event-driven
mechanism is not suitable for this kind of simulation
because of the global event-list. Although techniques
for performing event-list manipulation and event
simulation in parallel have been suggested [ 181, large
scale performance increases seem unlikely [ 191. The
strategy of the distributed event-list is also unpromis-
ing as the potential parallelism and resulting speedup
with the network model are significantly less than
anticipated [20].
To achieve results with a reasonable computing
period, the model should be partitioned, with suitable
decomposition and process-processor mapping meth-
ods, into concurrent processes that can be distributed
over a network of processors of a MIMD machine.
3.1. Process partition
As there are inherent dependent relationships
among data and switching blocks, the farming
heuristic will not be applicable properly to the model.
No matter which way is used to partition the model,
the processes could not work independently as the
algorithm required. In other words, communications
are necessary between the processes. Therefore, the
corresponding simulation would not be efficient.
The PDES techniques look attractive for the simu-
lation of communication networks. Indeed, these ap-
proaches are based on the principle of using a net-
work of logical processes to simulate the correspond-
ing physical processes in the system to be modelled.
Nevertheless, the topology of interactions among
components of the system is the key to determine
whether an approach is reasonable [7].
Significant differences exist between the ATM
switch fabric and a conventional communication net-
work. The conventional communication network car-
ries variable (large generally) packets with relatively
low transmission rate. The network topology is more
flexible with relatively less interaction among the
nodes of the system. The packets may be sent from
any node with the destination of any other node.
Therefore, the routing algorithm and communication
protocols need to be designed with more efforts.
On the other hand, the ATM switch fabric has
regular arrangements of the building blocks, and will
be used to switch short fixed-size cells in high speed.
The cell movements are unidirectional and synchro-
nised with the certain time interval within the fabric.
As ATM switches handle very high speed and high
 W. Liu et al./ Microprocessing
density traffic, the arrival and departure events occur
almost in every simulation cycle, even for a moder-
ate-size switching system. The components of the
ATM switch fabric are tightly-coupled with high
frequent interactions among them. The simulation
time becomes a more crucial factor when evaluating
the performance of ATM switches. With highly regu-
lar configurations of switching blocks and fixed-
length packets, the implementation of routing and
protocol algorithms becomes simple in contrast to
the simulation of classical communication networks.
Based on the above comparisons, it can be seen
that it is unlikely to achieve high performance of the
model of the ATM switching system with the PDES
approaches. Even though the conservative approach
is suitable for the networks with static interconnec-
tion, the overhead, such as the Chandy-Misra dead-
lock avoidance algorithm, is too high for implement-
ing the simulation of the ATM switches. A large
ATM switch fabric may involve several hundreds (or
thousands) of SEs, while each SE may have several
dozens of inputs/outputs. If one process emulates
one SE, it must exchange messages with all its
predecessors and successors. Even with a light load
in the network, the sending of one useful cell means
that corresponding null messages will be sent to all
other outputs. In addition, the data priorities result in
poor lookahead for cell streams. The conservative
algorithms appear to be poorly suited for the applica-
tions with poor lookahead properties, even if there is
a healthy amount of parallelism available [21]. For
the optimistic approach such as the Time Warp
algorithm, consider individual switching block(s) of
a fabric as a process running on a processor with its
local simulation time. The clock of the process is
seldom faster than that of its predecessors, due to the
unidirectional traffic. Thus, there is no chance for a
node to have some spare periods to schedule specula-
tive events. In case the chance exists with the ap-
proach, the cost of roll-back would be excessive for
a model of the ATM switch due to the large quanti-
ties of cells being processed.
and Microprogramming 41 (1996) 681-689 685
According to the characteristics of the system, a
time-driven mechanism is adopted by the simulation
tool. We think that the asynchronous simulation with
local clocks is more applicable to the system of
interest. When clocks are local and simulation is
asynchronous a process can begin simulating the
next tick as soon as its predecessors have finished
the last tick. Synchronisation for local clocks is
implicitly provided by sending a message from a
processor to its successors [7]. The restricted com-
munication overhead is the main benefit derived
from this choice. The synchronisation has been hid-
den in the necessary data flow of the model. To save
the transmission and setup time, the communicating
data between processors are organised as a single
message at a given simulation clock time.
A drawback of time-driven simulation is that the
statistical results would be erroneous if the variance
of event arrival is large. However, the simulation of
ATM switches will not suffer it due to the operating
behaviour. An ATM cell may occupy a number of
time slots on a TDM transmission medium. Before
entering a switch fabric, cells will be aligned with
the time slot for delineation. This implies that cells
are synchronised with time slot boundary within the
switch fabric. The slot interval can therefore be used
as basic unit of simulation time, which reflects the
very detail of cell movement.
3.2. Process assignment
A large ATM switch fabric may involve a dozen
stages with respect to the switching blocks, and each
stage may have several tens or hundreds of such
blocks. With the regular arrangement of these
switching blocks, it is possible to partition such a
switch fabric in horizontal direction, vertical direc-
tion or a mix of both. To the model under study, the
vertical partitioning has several advantages in con-
trast with the other two. First, the vertical partition-
ing coincides naturally with the traffic flowing. In
the model, packets enter the switch from the external
links, traverse the switch fabric stage by stage, and
686 W. Liu et al. / Microprocessing
finally leave the switch via the respective output
ports. Thus, the switch fabric is just like a pipeline;
the SEs in a column form a stage of the pipe, and
arrival packets are flowing data to be handled. With
this partitioning, the communication relationships are
clear among those concurrent components.
Second, it is easier to achieve the granularity
balance among the concurrent components divided.
The activating time of each component depends on
the amount of data to be processed. For a multi-path
self-routing ATM switch, in general, the quantity of
arrival packets on individual links (thus stages) is
statistically equivalent. The balanced load in differ-
ent stages hence means the balanced execution time
among processes on behalf of different stages. How-
ever, this load balance is ensured with the promise of
identical processors.
Third, it is natural for collecting statistics. The
SEs of the same stage within a switching network
play identical functions for the traffic. The SEs of a
stage will either distribute incoming packets, or route
incoming packets under a specific routing mode.
Thus, this partitioning makes the relationship of
concurrent processes very logical.
Forth, furthermore decomposition still can simply
go on to result in balanced partitioning. With more
available processors, each partitioned component, i.e.
a stage, can be further partitioned in horizontal direc-
tion so as to invite more processors to deal with the
simulation. The balanced load can still be kept if the
same number of identical processors is used for each
individual stage. However, speedup may not be
achieved by introducing more processors to join the
simulation if the communicatidn time dominates the
computation time in the simulation.
3.3. Parallel simulation tool
The simulation tool is developed under a UNIX-
like environment, programmed in C language, on a
transputer based multicomputer. The processors used
are INMOS T800 with one or two Mbytes memory
and Microprogramming 41 (1996) 681-689
each. The processors can be constructed as a recon-
figurable processing network by software through a
network configuration unit.
To execute concurrent processes on MIMD paral-
lel machines, much attention should be paid on two
important aspects. One is to avoid load unbalance on
different processors, and the other is to try to de-
crease the communication overhead among different
processors.
Due to the unidirectional packet flow, the model
has been partitioned according to the individual
stages, which reflects the packet flow naturally and
simplifies the communication relationships among
processes. With a small size switch fabric of interest,
one stage can be mapped to one process on a pro-
cess. When the switch fabric grows, each stage can
be mapped to more processes, thus more processors,
to speedup the simulation. Each process will spawn
some child processes at execution time dynamically.
All processes will be executed on a single processor.
The child processes are responsible for receiving/
sending packets from/to the processes on other pro-
cessors respectively.
The time-driven mode is adopted, and the simula-
tion is asynchronous with local clocks of individual
processes. Process’ local times are synchronised
through message passing among processors. The
large quantities of dependent data in the system are
the main reason to choose time-driven mode in the
simulation.
However, the time-driven mechanism also has a
negative effect on the simulation. Empty cells have
to be inserted into cell streams in order to maintain
the time continuation. T’his means spending extra
CPU time in checking the links on which no packets
are carried at the time unit.
4. Simulation experiment and performance
A series of simulations has been carried out for a
scalar ATM switching network, proposed in [22], by
 W. Liu et al./ Microprocessing
means of the simulation tool on a transputer based
multicomputer. The traffic sources generate ATM
cell streams on external links of the switching sys-
tem. In the interface module, a self-routing tag and
control information are added to each ATM cell, thus
introducing an overhead. The simulation tick corre-
sponds one eighth of transmission time of an internal
packet on the link operating at 155,52 Mbit/s. This
implies that an internal packet needs eight simulation
ticks to be processed, while a tick is about 0,437
microseconds. The fine time cycle may produce
precise results for performance metrics, but with the
cost of long simulation time.
In order to achieve reliable results, all the follow-
ing simulation runs extend five million ticks. Inde-
pendent uniform traffic pattern [lo] is assumed with
80 percent load on each external links. Unfortu-
nately, it is not possible to run the following versions
on a single transputer due to the memory require-
ment. Thus, the speedup obtained is deduced based
on the idea that simulation time taken on one trans-
puter is approximately equal to the sum of the useful
time spent by all transputers involved.
Table 1 gives the simulation performance about
three specific ATM switches with six, ten, and twelve
stages respectively. The mapping strategy of a single
processor for each stage is applied to the first two
simulations, whereas that of two processors for a
single stage is used for the third simulation. The
simulation run for the middle size switch is more
efficient than the small in that the packet communi-
cation cost is decreased due to the large size mes-
Table 1
Simulation Performance
Int. Stages Running SpeedUP Efficiency
links time
256 6 44 hours 4.5 75%
512 10 79 hours 8.7 87%
4096 12 301 hours 18.76 72%
and Microprogramming 41 (1996) 681-689 687
sages. The simulation of the large size switch is not
so efficient as that of other two because the commu-
nication relationships become more complex be-
tween stages. We achieved the statistical results about
cell loss ratio and cell queueing delay in the quantity
less than 10m6 from all three simulation runs.
Eventhough these simulations spend a large
amount of time, the speedups are significant. It was
also found that during execution of the simulation,
the computation time dominates the communication
time. This implies that the efforts to reduce the
communication cost to a minimum by overlapping
the communications on different physical links on
each processor with computation have been very
successful.
5. Conclusions
The integration of simulation and parallel process-
ing techniques can provide strong enough computing
power for the simulation of large scale ATM switch
networks. A parallel simulation tool to evaluate the
performance of a class of ATM switching networks
has been developed and implemented. First, the sim-
ulation model is built based on a class of ATM
switching systems. In order to implement an efficient
simulation tool, various parallel processing tech-
niques are then approached together with the system
model under study. Through this approach, the model
has been decomposed into a set of processes for a
loosely-coupled parallel computer. With a very high
level of detail in the simulation, the benefits from
parallelism are significant (and necessary). From the
experiments, we can conclude that MIMD multicom-
puters are quite suitable to the problems of evaluat-
ing performance for large high-speed ATM switch-
ing systems.
Even though we emphasise that the simulation
tool is used to assess performance for a class of
ATM switching systems, the tool can be generalised
to the packet switch architectures for variable length
688 W. Liu et al./Microprocessing
packets. Because it is written in C language and
developed under UNIX-like environment, the simula-
tion tool can be ported to other loosely-coupled
MIMD computers without much difficulty. However,
attention should be paid to the communication cost
of the target machine. For example, distributing pro-
cesses on a set of processors interconnected with a
busy LAN would result in a very poor simulation
performance.
Although large gain has been achieved through
the parallelization of the model, reliable statistics
still require huge computing power for a simulation
of the large scale ATM switching network at a
detailed level. The progress of semiconductor tech-
nology is another aspect that can help in shortening
the simulation run time for such applications. For
example, new generation processors and parallel ma-
chines offer significant improvements in both com-
putation and communication performance. No doubt
the combination of advanced microprocessors with
suitable algorithms will provide a more cost-effec-
tive environment for the simulations requiring large
quantities computing power, such as large ATM
switching networks.
Acknowledgement
The authors would like to thank the anonymous
referees for their helpful suggestions on an earlier
version of this paper.
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 W. Liu et al./ Microprocessing and Microprogramming 41 (1996) 681-689 689

Weixin Liu received the B.S. degree in
computer science from Changsha Insti-
tute of Technology, Changshu, China, in
1982.
He is currently working towards the Ph.J.
degree at the Free Universitv of BNS-
sel’; (Vtije Universiteit B&el), BNS-
sels, Belgium. His current research in-
terests include parallel computation,
ATM switching networks, and perfor-
mance evaluation techniques.
G.H. Petit is traffic technology manager
at the Alcatel Corporate Research Cen-
ter in Antwerp (Alcatel-Bell). He is an
IEEE member and since 1992 part-time
lecturer at the University of Antwerp.
He is active in the area of B-ISDN
traffic and flow control, resource man-
agement strategies and performance
evaluation of large ATM switching sys-
tems and networks.

E. Dirkx has an M.Sc. Electronic Engi-

neering 1984, M.Sc. Computer Science
1986, Ph.D. Computer Science 1990,
I and an M.Sc. Management 1990. Dr.
Dirkx has been a research scientist at
I.B.M. T.J. Watson Research Centre
(Yorktown Heights, 1992) and Elec-
trotechnical Laboratorv (Tsukuba. 1993).
Since 1995, he is lecturer at the VriJe
Universiteit Brussel. His research inter-
ests are parallel computer architecture,
distributed computing, (discrete) simula-
tion and telecommunication networks.