SEMICONDUCTOR TECHNICAL DATA








HighPerformance SiliconGate CMOS
The MC54/74HC161A and HCI63A are identical in pinout to the LS161
and LS163. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs. J SUFFIX
The HC161A and HC163A are programmable 4bit binary counters with CERAMIC PACKAGE
asynchronous and synchronous reset, respectively. 16 CASE 62010
Output Drive Capability: 10 LSTTL Loads 1

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2.0 to 6.0 V N SUFFIX
Low Input Current: 1.0 A 16 PLASTIC PACKAGE
High Noise Immunity Characteristic of CMOS Devices CASE 64808
1
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 192 FETs or 48 Equivalent Gates D SUFFIX
16 SOIC PACKAGE
1 CASE 751B05

LOGIC DIAGRAM
ORDERING INFORMATION
MC54HCXXXAJ Ceramic
3 14 MC74HCXXXAN Plastic
P0 Q0
MC74HCXXXAD SOIC
PRESET 4 13 BCD OR
P1 Q1
DATA BINARY
5 12
INPUTS P2 Q2 OUTPUT
6 11 PIN ASSIGNMENT
P3 Q3

RIPPLE RESET 1 16 VCC

2 15
CLOCK CARRY RIPPLE
CLOCK 2 15
OUT CARRY OUT
P0 3 14 Q0
1 P1 4 13 Q1
RESET
9 P2 5 12 Q2
LOAD
7 P3 6 11 Q3
ENABLE P

COUNT
PIN 16 = VCC ENABLE P 7 10 ENABLE T
ENABLES 10

ENABLE T PIN 8 = GND
GND 8 9 LOAD

Count

Device Mode Reset Mode FUNCTION TABLE

Inputs Output
HC161A Binary Asynchronous

Clock Reset* Load Enable P Enable T Q
HC163A Binary Synchronous L X X X Reset
H L X X Load Preset Data
H H H H Count
H H L X No Count
H H X L No Count

* HC163A only. HC161A is an Asynchronous Reset Device

H = high level
L = low level
X = dont care

10/95

Motorola, Inc. 1995 31 REV 6



MC54/74HC161A MC54/74HC163A

MAXIMUM RATINGS*

Symbol Parameter Value Unit This device contains protection

VCC DC Supply Voltage (Referenced to GND) 0.5 to + 7.0 V circuitry to guard against damage

due to high static voltages or electric

Vin DC Input Voltage (Referenced to GND) 1.5 to VCC + 1.5 V fields. However, precautions must

Vout DC Output Voltage (Referenced to GND) 0.5 to VCC + 0.5 V be taken to avoid applications of any

voltage higher than maximum rated

Iin DC Input Current, per Pin 20 mA voltages to this highimpedance cir-

Iout DC Output Current, per Pin 25 mA cuit. For proper operation, Vin and

Vout should be constrained to the

ICC DC Supply Current, VCC and GND Pins 50 mA v
range GND (Vin or Vout) VCC. v

Unused inputs must always be

PD Power Dissipation in Still Air, Plastic or Ceramic DIP 750 mW

tied to an appropriate logic voltage

SOIC Package 500
level (e.g., either GND or VCC).

Tstg Storage Temperature 65 to + 150 _C Unused outputs must be left open.

TL Lead Temperature, 1 mm from Case for 10 Seconds _C

(Plastic DIP or SOIC Package) 260

(Ceramic DIP) 300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
Ceramic DIP: 10 mW/_C from 100_ to 125_C

SOIC Package: 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

_C

TA Operating Temperature, All Package Types 55 + 125

tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V 0 1000 ns
VCC = 4.5 V 0 500

VCC = 6.0 V 0 400

DC ELECTRICAL CHARACTERISTICS (Voltages referenced to GND)

Guaranteed Limit

v v
VCC 55 to

Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

VIH Minimum HighLevel Input Vout = 0.1 V or VCC 0.1 V 2.0 1.5 1.5 1.5 V
v
Voltage |Iout| 20 A 4.5 3.15 3.15 3.15

6.0 4.2 4.2 4.2

VIL Maximum LowLevel Input Vout = 0.1 V or VCC 0.1 V 2.0 0.50 0.50 0.50 V
v 20 A

Voltage |Iout| 4.5 1.35 1.35 1.35

6.0 1.80 1.80 1.80

VOH Minimum HighLevel Output

v
Vin = VIH or VIL 2.0 1.9 1.9 1.9 V

v
Voltage |Iout| 20 A 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9

v Vin = VIH or VIL |Iout| 4.0 mA 4.5 3.98 3.84 3.7 V

|Iout| 5.2 mA 6.0 5.48 5.34 5.2

VOL Maximum LowLevel Output Vin = VIH or VIL 2.0 0.10 0.10 0.10 V
v |Iout| 20 A 4.5 0.10 0.10 0.10

v
Voltage
6.0 0.10 0.10 0.10

v
Vin = VIH or VIL |Iout| 4.0 mA 4.5 0.26 0.33 0.40 V

|Iout| 5.2 mA 6.0 0.26 0.33 0.40

0.1 1.0 1.0 A

Iin Maximum Input Leakage Current Vin = VCC or GND 6.0

ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4 40 160 A

Current (per Package) Iout = 0 A

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

MOTOROLA 32 HighSpeed CMOS Logic Data

DL129 Rev 6


MC54/74HC161A MC54/74HC163A

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

v
v
VCC 55 to

Symbol Parameter Fig. V 25_C 85_C 125_C Unit

fmax Maximum Clock Frequency (50% Duty Cycle)* 1, 7 2.0 6 5 4 MHz

4.5 30 24 20
6.0 35 28 24

tPLH Maximum Propagation Delay, Clock to Q 1, 7 2.0 120 160 200 ns

4.5 20 23 28

6.0 16 20 22

tPHL 1, 7 2.0 145 185 320 ns

4.5 22 25 30

6.0 18 20 23

tPHL Maximum Propagation Delay, Reset to Q (HC161A Only) 2, 7 2.0 145 185 220 ns

4.5 20 22 25
6.0 17 19 21

tPLH Maximum Propagation Delay, Enable T to Ripple Carry Out 3, 7 2.0 110 150 190 ns

4.5 16 18 20

6.0 14 15 17

tPHL 3, 7 2.0 135 175 210 ns

4.5 18 20 22

6.0 15 16 20

tPLH Maximum Propagation Delay, Clock to Ripple Carry Out 1, 7 2.0 120 160 200 ns

4.5 22 27 30
6.0 18 22 25

tPHL 1, 7 2.0 145 185 220 ns

4.5 22 28 35

6.0 20 24 28

tPHL Maximum Propagation Delay, Reset to Ripple Carry Out 2, 7 2.0 155 190 230 ns
(HC161A Only) 4.5 22 26 30

6.0 18 22 25

tTLH, Maximum Output Transition Time, Any Output 2, 7 2.0 75 95 110 ns

tTHL 4.5 15 19 22
6.0 13 16 19

Cin Maximum Input Capacitance 1, 7 10 10 10

* Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Out
pF

propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine fmax. However,
if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the fmax in the table above is applicable. See
Applications information in this data sheet.
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High
Speed CMOS Data Book (DL129/D).

Typical @ 25C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Gate)* 30 pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).

HighSpeed CMOS Logic Data 33 MOTOROLA

DL129 Rev 6


MC54/74HC161A MC54/74HC163A

TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

v
v
VCC 55 to

Symbol Parameter Fig. V 25_C 85_C 125_C Unit

tsu Minimum Setup Time, 5 2.0 40 60 80 ns

Preset Data Inputs to Clock 4.5 15 20 30

6.0 12 18 20

tsu Minimum Setup Time, 5 2.0 60 75 90 ns

Load to Clock 4.5 15 20 30

6.0 12 18 20

tsu Minimum Setup Time, 4 2.0 60 75 90 ns

Reset to Clock (HC163A Only) 4.5 20 25 35

6.0 17 23 25

tsu Minimum Setup Time, 6 2.0 80 95 110 ns

Enable T or Enable P to Clock 4.5 20 25 35

6.0 17 23 25

th Minimum Hold Time, 5 2.0 3 3 3 ns

Clock to Load or Preset Data Inputs 4.5 3 3 3

6.0 3 3 3

th Minimum Hold Time, 4 2.0 3 3 3 ns

Clock to Reset (HC163A Only) 4.5 3 3 3

6.0 3 3 3

th Minimum Hold Time, 6 2.0 3 3 3 ns

Clock to Enable T or Enable P 4.5 3 3 3

6.0 3 3 3

trec Minimum Recovery Time, 2 2.0 80 95 110 ns

Reset Inactive to Clock (HC161A Only) 4.5 15 20 26

6.0 12 17 23

trec Minimum Recovery Time, 5 2.0 80 95 110 ns

Load Inactive to Clock 4.5 15 20 26

6.0 12 17 23

tw Minimum Pulse Width, 1 2.0 60 75 90 ns

Clock 4.5 12 15 18
6.0 10 13 15

tw Minimum Pulse Width, 2 2.0 60 75 90 ns

Reset (HC161A Only) 4.5 12 15 18

6.0 10 13 15

tr, tf Maximum Input Rise and Fall Times 2.0 1000 1000 1000 ns

4.5 500 500 500

6.0 400 400 400

MOTOROLA 34 HighSpeed CMOS Logic Data

DL129 Rev 6
 MC54/74HC161A MC54/74HC163A

FUNCTION DESCRIPTION
The HC161A/163A are programmable 4bit synchronous CONTROL FUNCTIONS
counters that feature parallel Load, synchronous or asynch-
Resetting
ronous Reset, a Carry Output for cascading and count
enable controls. A low level on the Reset pin (Pin 1) resets the internal flip
The HC161A and HC163A are binary counters with flops and sets the outputs (Q0 through Q3) to a low level.
asynchronous Reset and synchronous Reset, respectively. The HC161A resets asynchronously, and the HC163A resets
with the rising edge of the Clock input (synchronous reset).
INPUTS Loading
Clock (Pin 2) With the rising edge of the Clock, a low level on Load (Pin
9) loads the data from the Preset Data input pins (P0, P1, P2,
The internal flipflops toggle and the output count ad- P3) into the internal flipflops and onto the output pins, Q0
vances with the rising edge of the Clock input. In addition, through Q3. The count function is disabled as long as Load is
control functions, such as resetting and loading occur with low.
the rising edge of the Clock input.
Count Enable/Disable
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6) These devices have two countenable control pins: En-
able P (Pin 7) and Enable T (Pin 10). The devices count
These are the data inputs for programmable counting. when these two pins and the Load pin are high. The logic
Data on these pins may be synchronously loaded into the in- equation is:
ternal flipflops and appear at the counter outputs. P0 (Pin 3)
is the leastsignificant bit and P3 (Pin 6) is the mostsignifi- Count Enable = Enable P Enable T Load
cant bit. The count is either enabled or disabled by the control in-
puts according to Table 1. In general, Enable P is a count
OUTPUTS enable control: Enable T is both a countenable and a
RippleCarry Output control.
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
Table 1. Count Enable/Disable
These are the counter outputs. Q0 (Pin 14) is the least
significant bit and Q3 (Pin 11) is the mostsignificant bit. Control Inputs Result at Outputs
Load Enable P Enable T Q0 Q3 Ripple Carry Out
Ripple Carry Out (Pin 15) H H H Count High when Q0Q3
When the counter is in its maximum state 1111, this output L H H No Count are maximum*
goes high, providing an external lookahead carry pulse that
may be used to enable successive cascaded counters. Rip- X L H No Count High when Q0Q3
are maximum*
ple Carry Out remains high only during the maximum count
state. The logic equation for this output is: X X L No Count L
Ripple Carry Out = Enable T Q0 Q1 Q2 Q3 * Q0 through Q3 are maximum when Q3 Q2 Q1 Q0 = 1111.

OUTPUT STATE DIAGRAMS

0 1 2 3 4

15 5

14 6

13 7

12 11 10 9 8

Binary Counters

HighSpeed CMOS Logic Data 35 MOTOROLA

DL129 Rev 6
MC54/74HC161A MC54/74HC163A

SWITCHING WAVEFORMS

tr tf tw
VCC VCC
CLOCK 90%
50% RESET 50%
10% GND GND
tw tPHL
1/fmax
ANY 50%
tPLH tPHL
OUTPUT
ANY 90% trec
50%
OUTPUT 10% VCC
CLOCK 50%
tTLH tTHL GND

Figure 1. Figure 2.

tr tf
VCC 50%
ENABLE T 90% RESET
50%
10% GND
tPLH tPHL tsu th
RIPPLE 90%
50% VCC
CARRY 10% CLOCK 50%
OUT
tTLH tTHL GND

Figure 3. Figure 4. HC163A Only

VALID

INPUTS VCC
P0, P1, 50%
P2, P3 GND

tsu th
VALID
VCC
LOAD 50% ENABLE T VCC
GND OR 50%
ENABLE P GND
tsu th trec tsu th
VCC
VCC 50%
CLOCK
CLOCK 50% GND
GND
Figure 5. Figure 6.

TEST CIRCUIT

TEST POINT

OUTPUT
DEVICE
UNDER
TEST CL*

* Includes all probe and jig capacitance

Figure 7.

MOTOROLA 36 HighSpeed CMOS Logic Data

DL129 Rev 6
 T0 14
R Q0 Q0
C
C

DL129 Rev 6
LOAD
3 LOAD Q0
P0 P0

HighSpeed CMOS Logic Data

T1 13
R Q1 Q1
C
C
LOAD
LOAD Q1
P1 4 P1

T2 12
R Q2 Q2
C
C
LOAD
5 LOAD Q2
P2 P2

37
T3 11
R Q3 Q3

(MC54/74HC161A)
C
C
LOAD
6 LOAD
P3 P3
15 RIPPLE
CARRY
OUT
7
ENABLE P

Figure 8. 4Bit Binary Counter with Asynchronous Reset

VCC = PIN 16
10 GND = PIN 8
ENABLE T

1
RESET R
The flipflops shown in the circuit diagrams are ToggleEnable flipflops. A Toggle
Enable flipflop is a combination of a D flipflop and a T flipflop. When loading data from
9 LOAD
LOAD Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
LOAD the flipflop. The logic level at the Pn input is then clocked to the Q output of the flipflop
2 on the next rising edge of the clock.
CLOCK C A logic zero on the Reset device input forces the internal clock (C) high and resets the Q
C output of the flipflop low.

MOTOROLA
MC54/74HC161A MC54/74HC163A
MC54/74HC161A MC54/74HC163A

Sequence illustrated in waveforms:

1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one and two.
4. Inhibit.

RESET (HC161A)
(ASYNCHRONOUS)
RESET (HC163A)
(SYNCHRONOUS)
LOAD

P0

PRESET P1
DATA
INPUTS P2

P3
CLOCK (HC161A)

CLOCK (HC163A)

ENABLE P
COUNT
ENABLES
ENABLE T

Q0

Q1
OUTPUTS
Q2

Q3
RIPPLE
CARRY
OUT 12 13 14 15 0 1 2
COUNT INHIBIT
RESET LOAD

Figure 9. Timing Diagram

MOTOROLA 38 HighSpeed CMOS Logic Data

DL129 Rev 6
 T0 14
R Q0 Q0
C
C

DL129 Rev 6
LOAD
3 LOAD Q0
P0 P0

HighSpeed CMOS Logic Data

T1 13
R Q1 Q1
C
C
LOAD
4 LOAD Q1
P1 P1

T2 12
R Q2 Q2
C
C
LOAD
5 LOAD Q2
P2 P2

39
T3 11
R Q3 Q3

(MC54/74HC163A)
C
C
LOAD
6 LOAD
P3 P3
15 RIPPLE
CARRY
OUT
7
ENABLE P

Figure 10. 4Bit Binary Counter with Synchronous Reset

VCC = PIN 16
10 GND = PIN 8
ENABLE T

1
RESET R
The flipflops shown in the circuit diagrams are ToggleEnable flipflops. A Toggle
Enable flipflop is a combination of a D flipflop and a T flipflop. When loading data from
9 LOAD
LOAD Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
LOAD the flipflop. The logic level at the Pn input is then clocked to the Q output of the flipflop
2 on the next rising edge of the clock.
CLOCK C A logic zero on the Reset device input forces the internal clock (C) high and resets the Q
C output of the flipflop low.

MOTOROLA
MC54/74HC161A MC54/74HC163A
MC54/74HC161A MC54/74HC163A

TYPICAL APPLICATIONS CASCADING

LOAD

INPUTS INPUTS INPUTS

LOAD P0 P1 P2 P3 LOAD P0 P1 P2 P3 LOAD P0 P1 P2 P3

H = COUNT
ENABLE P ENABLE P ENABLE P
L = DISABLE
RIPPLE RIPPLE RIPPLE TO
H = COUNT MORE
ENABLE T CARRY ENABLE T CARRY ENABLE T CARRY
L = DISABLE SIGNIFICANT
OUT OUT OUT
STAGES
CLOCK CLOCK CLOCK

R Q0 Q1 Q2 Q3 R Q0 Q1 Q2 Q3 R Q0 Q1 Q2 Q3

RESET

OUTPUTS OUTPUTS OUTPUTS

CLOCK

NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on
number of stages. This limitation is due to set up times between Enable (Port) and Clock.

Figure 11. NBit Synchronous Counters

INPUTS INPUTS INPUTS

LOAD
ENABLE P
ENABLE T

LOAD P0 P1 P2 P3 LOAD P0 P1 P2 P3 LOAD P0 P1 P2 P3

ENABLE P ENABLE P ENABLE P

TO
RIPPLE RIPPLE RIPPLE
MORE
ENABLE T CARRY ENABLE T CARRY ENABLE T CARRY
SIGNIFICANT
OUT OUT OUT
STAGES
CLOCK CLOCK CLOCK CLOCK

R Q0 Q1 Q2 Q3 R Q0 Q1 Q2 Q3 R Q0 Q1 Q2 Q3

RESET

OUTPUTS OUTPUTS OUTPUTS

Figure 12. Nibble Ripple Counter

MOTOROLA 310 HighSpeed CMOS Logic Data

DL129 Rev 6
 MC54/74HC161A MC54/74HC163A

TYPICAL APPLICATIONS VARYING THE MODULUS

HC163A HC163A
OTHER OTHER
Q0 OPTIONAL BUFFER Q0 OPTIONAL BUFFER
INPUTS INPUTS
Q1 FOR NOISE REJECTION Q1 FOR NOISE REJECTION

Q2 OUTPUT Q2 OUTPUT

Q3 Q3

RESET RESET

Figure 13. Modulo5 Counter Figure 14. Modulo11 Counter

The HC163A facilitates designing counters of any modulus with minimal external logic. The output is glitchfree due to the
synchronous Reset.

HighSpeed CMOS Logic Data 311 MOTOROLA

DL129 Rev 6
MC54/74HC161A MC54/74HC163A

OUTLINE DIMENSIONS

J SUFFIX
A CERAMIC PACKAGE
CASE 62010
NOTES:
16 9 ISSUE V 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
B 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
1 8 FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
C L THE LEAD ENTERS THE CERAMIC BODY.

INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
T B 0.240 0.295 6.10 7.49

SEATING N K C 0.200 5.08
PLANE D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
E M G 0.100 BSC 2.54 BSC
J 0.008 0.015 0.21 0.38
F G J 16 PL K 0.125 0.170 3.18 4.31
D 16 PL 0.25 (0.010) M T B S L 0.300 BSC 7.62 BSC
M 0 15 0 15
0.25 (0.010) M T A S N 0.020 0.040 0.51 1.01

N SUFFIX
A PLASTIC PACKAGE NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
CASE 64808 Y14.5M, 1982.
ISSUE R 2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
F DIM MIN MAX MIN MAX
C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.070 1.02 1.77
T PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
K M J
H J 0.008 0.015 0.21 0.38
G K 0.110 0.130 2.80 3.30
D 16 PL L 0.295 0.305 7.50 7.74
M 0 10 0 10
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

D SUFFIX
PLASTIC SOIC PACKAGE
A CASE 751B05
ISSUE J NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
B MOLD PROTRUSION.
P 8 PL 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

1 8 0.25 (0.010) M B M PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
G MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45 B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
T

SEATING M J J 0.19 0.25 0.008 0.009
PLANE K 0.10 0.25 0.004 0.009
D 16 PL M 0 7 0 7
0.25 (0.010) M T B S A S P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

MOTOROLA 312 HighSpeed CMOS Logic Data

DL129 Rev 6
 MC54/74HC161A MC54/74HC163A

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different
applications. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. Motorola does
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*MC54/74HC161A/D*
CODELINE MC54/74HC161A/D
HighSpeed CMOS Logic Data 313 MOTOROLA
DL129 Rev 6