Professional Documents
Culture Documents
IDU
+
MODEM
EM Propagation conditions in the mmW band
Communications between
nomadic devices (such as
pocket HD, )
Communications between/with
mobile devices such as: digital
(still) cameras, mobile phones,
PDAs
HD video transmission on
home TVs
60GHz Bands Licensing
US FCC Allowance:
3 Allowed Bands:
71-76 GHz; 81-86 GHz ; 92-95 GHz
Emitted Isotropic Radiated Power:
55 dBW EIRP at 50 dB antenna gain
41 dBW EIRP at 43 dB antenna gain
77-81 GHz
From 77 to 81 GHz, oxygen
absorption is negligible less
than 1 dB/km
www.millivision.com/images/HandHeldNew.jpg
SiGe-C HBT:
130nm HBT mmW technology.
SOI CMOS :
65 nm CMOS LP HR SOI technology.
SiGe-C HBT Technology
SEM Pictures
130nm node SiGe:C HBT devices RF performances
fmax (GHz)
fT BVCEO
fT (GHz)
SOI STI
Buried Oxide
Bulk ~ 10 Ohm-cm
> 1kOhm-cm Si
65nm LP SOI technology 65nm LP Bulk technology
STMicroelectronics
STMicroelectronics
LP 65nm HP 65nm
Lg (nm) ~ 60 ~ 32
max Jg(A/cm2) ~ 0.025 ~ 40
Istandby SRAM bitcell @ Vdd ~ 0.6V <10pA/m > 1nA/m
High Performance (HP) processes optimizations=>for increased speed:
Lower nominal gate length
Gate oxide much thinner for HP higher gate leakage
Consequences for HP:
Large Standby power
a mixed HP/LP process ? A two nominal gate lengths and Double Gate Oxide
Process would increase too much the cost for portable products.
250
225 TOX = 23A TOX = 21A
CMOS transistor architecture down to
200 TOX = 18A TOX = 16A 65nm node: still uses poly gate, n,p
175 TOX = 13A f 1 / LG
0.86
increased using several technology
150 solutions
fT (GHz)
125
100 Devices developed for digital
75 applications and then fairly optimized
50 for analog/RF
25
0
40 50 60 70 80 90 100 110 120 130 In 65nm node, fT values reaches
Physical Gate Length (nm) 150GHz for LP devices and 200GHz
for GP ones
LP and GP devices Bulk AND SOI devices show similar
HF performances:
fT 1/Lg ( ~ 1) SOI FB CMOS suffers from Kink effect,
but in HF has same characteristics as a
identical layout bulk device
SOI BC CMOS is penalized in HF by
their specific layout (Rg/ and Cgs /)
Evolution of fT through CMOS technology
nodes several foundries
450 ITRS roadmap 2006
250
CMOS SOI HP 65 IBM
200
CMOS 65 Intel
150
CMOS SOI LP 65 ST
100
CMOS LP 65 ST
50
CMOS SOI HP 65 IBM
0
CMOS LP 45 ST
0 20 40 60 80 100
Physical Gate Length (nm) CMOS 45 IBM
Deep submicron technologies
Limitations to gm increase
gm 1/Lg Lg
Reduced tox
gm 1/tox
Thinner LDD
gm Gate tunneling current
Doping
tox does not decrease as expected for a good scaling with Lg, due to
gate leakage
Source and drain resistances increase due to thinner Low Doped Drain
regions (same LDD depth for bulk and PD SOI technologies thinner for
ultra-thin FD SOI!)
Courtesy to C. Raynaud, STMicroectronics & CEA
Deep submicron technologies
Techniques to increase gm
ultra thin SOI film to reduce doping level (vT definition by metal
gate work-function) but gate material issue to get low vT and high
vT at the same time and influence of ultra thin SOI film + high k on
mobility and low frequency noise not yet well known
400
CMOS SOI HP 90 IBM
300
CMOS SOI HP 65 IBM
200
CMOS 65 Intel
0 CMOS LP 65 ST
0 20 40 60 80 100
Physical Gate Length (nm) CMOS 45 IBM
Influence of MOS transistor layout
over fT and fmax parameters
f T (GHz) NMOS, Lpoly 90nm fm ax (GHz) 130nm SOI process
200 200 STMicroelectronics
fmax with 2 gate access, Wf = 5m Ft 8*(2*5*0.12) 2GA
160 160 Ft 8*(2*5*0.12)
Ft 2*(2*20*0.12)
120 120
Ft 8*(1*10*0.12)
80 fmax with different Wf 80 Fmax 8*(2*5*0.12) 2GA
Wf=5m
Fmax 8*(2*5*0.12)
40 Wf=10m 40 Fmax 2*(2*20*0.12)
Wf=20m Fmax 8*(1*10*0.12)
0 0
10 Ids(m A) 100
Source
Source
Source
Source
NFmin (dB)
0,8
bulk 45nm, IBM,
0,6 VLSI07
0,4
ITRS L = 45nm
0,2 @5GHz
0
ITRS L = 65nm
0 10 20 30 @5GHz
f (GHz)
NFmin (dB)
fT & fmax (GHz)
250
1.5
5
200 1.2
4
150 0.9
3
100 0.6
2
50 0.3 VCE = VDS = 1.2 V
1
0.0
0 0 0 10 20 30 40 50 60 70 80
0.01 0.1 1
IC / LE [HBT] & IDS / WG [NMOS] (mA/m)
Frequency (GHz)
Consequences:
Lumped elements (inductors): larger ohmic and substrate losses
Distributed elements (Tlines): attenuation constant degradation
Possible solutions:
Use mmW dedicated BEOL (e.g. 3 thick Me layers + thick IMD)
drawback: application dedicated process
Use digital BEOL with max number of Me layers (e.g. 10 Me layers)
drawback: cost
Increase the substrate resistivity (e.g SOI HR)
drawback: cost & specific process
mmW Tlines in CMOS deep submicron BEOL
BEOL
CMOS90 (7M2T) M7+Al / M1+M2
1.2 MS: w=6.0m/h=4.06m
CMOS65 SOI (6M1T) M6+Al
1.0 CPW: w=12m/s=5m
mmW dedicated
CPW: w=26m/s=22m
0.6
0.4 BiCMOS9MW (6M3T) M6+Al / M1+M2
MS: w=12m/h=7m
0.2
Above IC BCB Cu (t=2m)
BEOL
MS: w=24m/h=10m
0.0
0 20 40 60 80 100 120 140 160 180
Frequency (GHz)
HR SOI performances up to 100 GHz
Specific HR SOI CPW stacking all the metallizations
has been realized and characterised up to 110 GHz
1
InP
0.8 SOI (stacked)
Attenuation (dB)
SOI (top level)
0.6
0.4
0.2
0
0 20 40 60 80 100
GUI
Results: S parameters
ADS dataset output format
Generate a symbol for
PSF output format Agilent GoldenGate simulation
Metal Fills
mmW State of the art LNA Solutions
G IIP3 f
FOM LNA =
( NF 1) PDC
Example 2: 65nm LP SOI CMOS 80GHz LNA
B. Martineau, et al., ESSCIRC 2007
Vdd=1V Vdd=1V Vdd=1V
Vg bias1 Vg bias2 Vg bias3
Ro Ro Ro
Ri Ri Ri
Co Co Co
Ci Ci Ci
mm-wave
PAD OUT
mm-wave
PAD IN 1 pF
M1 M2 M3
1 pF
1 pF 1 pF gnd Vg1 Vdd Vg2 Vdd Vg3 Vdd gnd
Area = 0.98mm
IN OUT
(incl. pads)
mmW State of the art LNA Solutions
G IIP3 f
FOM LNA =
( NF 1) PDC
Example 3: 90nm CMOS 60GHz lumped LNA
E. Cohen et al., RFIC 2008
mmW State of the art LNA Solutions
G IIP3 f
FOM LNA =
( NF 1) PDC 90nm CMOS
SiGe HBT
FOM LNA
40
38
35 33.7
30
FOM (GHz)
25
20
16.9
FOM LNA SOI CMOS
15 15.7
13.5
10 8.9 9.31
5 5.71
3.28
0
0 20 40 60 80 100
Frequency (GHz)
The LNA design performances depends on the NFmin, (Ft) of the process
and the Matching network:
mmW LNA is Designer dependent.
CMOS and SiGe performances are similar.
mmW Down-conversion Mixers Design
Considerations
Active mixers topologies:
NMOS or HBT devices, Gilbert cells, Gm-cells, single or balanced inputs
for RF and LO
Pros: high conversion gain value, need for reduced LO power, good
noise figure
Cons: important power consumption, limited linearity, wide-band LO and
RF ports matching sometimes difficult to obtain
RF power: -25dBm
IF: diff, 2GHz, 50
Mixer area = 1.6X1.7 mm
mmW State of the art Down-conversion
Mixers Solutions
Example 2: Digital 90nm CMOS
passive (resistive) gate-pumped mixer
B.M. Motlagh, et al., IEEE M&W Comp. Letters, Jan. 2006
IF: DC to 10GHz, 50
Mixer area < 0.2mm
Area=0.3X0.25mm
Std resistivity substrate (15.cm)
Very large frequency tuning range by:
-Large varactor size (thick oxyde MOS caps)
-Small transistor size
mmW State of the art VCO Solutions
Example 2: 65nm CMOS 54GHz
cross-coupled LC VCO with I-MOS varactor
S. Bozzola, et al., RFIC 2008
mmW State of the art VCO Solutions
Example 3: 65nm CMOS 60GHz
cross-coupled LC DCO
62
000
56
VDD Out Out+
b[2]
54
VBIAS Digital control
MP1 Cf
varactor bank 52
Continuous tuning b[1]
7 units of 1x1
W=2.0 m
111
analog control varactor
L=0.235 m
50
5x5 islands
(see Figs.2,3) 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8
b[2:0]
W=1.10 m
L=0.28 m b[0]
(see Fig.2) Vc (V)
3
VDD_BUFF VDD_BUFF -9
TL3
011 000
Vdd Vdd_BUFF
* VBW 300 kHz -38.99 dB
Ref -7 dBm * Att 0 dB * SWT 2.5 ms 1.009615385 MHz
b2
Short stub
-60
Vbias
3DB
350m
TL -70
195
193
190 190.9
185 184184.95
FOM (dB)
165
0 20 40 60 80 100 120
Fequency (GHz)
Cascoded stages:
Pros: higher gain, larger output impedance, flat Ids/Vds characteristic
Common source/emitter stages:
Pros: lower supply voltage higher efficiency, better linearity
Cons: reduced reverse bias complicates the input/output matching
FOM PA
4
Bulk CMOS
Log(10)(FOM ) (W.GHz)
3.5
3
2.5
2 FOM PA
1.5
1
0.5
0
0 20 40 60 80 100
Frequency (GHz)
Ref: J.Laskar & all 60GHz CMOS 90nm Radio with Integrated signal processor Proceeding IEEE ISSCC 08
DONT FORGET!
The Package and the Antenna could participate to the global performance up
to 50%.
The Antenna strategy will define the needed PA output power and the
requirement or not of a Beam forming architecture.
The Package will include the Circuit and the Antenna.
mmW Substrate coupling seems to forbid robust solutions in ZIF architecture.
STRENGTH WEAKNESS
OPPORTUNITIES THREATS
41. M. Tanomura, et al., TX and RX Front-Ends for 60GHz Band in 90nm Standard
Bulk CMOS, IEEE ISSCC 2008, San Francisco, Feb 2008
42. D. Chowdhury, et al., A 60GHz 1V +12.3dBm Transformer-Coupled Wideband
PA in 90nm CMOS , IEEE ISSCC 2008, San Francisco, Feb 2008
43. T. Suzuki, et al., 60 and 77GHz Power Amplifiers in Standard 90nm CMOS,
IEEE ISSCC 2008, San Francisco, Feb 2008
44. E. Cohen, et al., An ultra low power LNA with 15dB gain and 4.4dB NF in 90nm
CMOS process for 60GHz phase array radio , IEEE RFIC 2008, Atlanta, June
2008
45. T. LaRocca, et al., 60GHz CMOS Differential and Transformer-Coupled Power
Amplifier for Compact Design , IEEE RFIC 2008, Atlanta, June 2008
46. B. Wicks, et al., A 60GHz Fully-Integrated Doherty Power Amplifier Based on
0.13m CMOS Process, IEEE RFIC 2008, Atlanta, June 2008
47. J. Borremans et al., VCO design for 60Ghz applications using differential
shielded inductors in 0.13m CMOS, IEEE RFIC 2008, Atlanta, June 2008
48. C. Cao and K. K. O, Millimeter-wave voltage-controlled oscillators in 0.13-mm
technology, IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 12971304, Jun.
2006.
49. D. Huang, W. Hant, N.-Y.Wang, T. W. Ku, Q. Gu, R.Wong, and M.-C. F. Chang,
A 60 GHz CMOS VCO using on-chip resonator with embedded artificial
dielectric for size, loss and noise reduction, in IEEE Int. Solid-State Circuits
Conf. (ISSCC) Dig. Tech. Papers, 2006, pp. 314315
References (VI)
50. D. D. Kim, J. Kim, J. Plouchart, C. Cho, W. Li, D. Lim, R. Trzcinski, M. Kumar, C. Norris and D.
Ahlgren, A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm
SOI CMOS, IEEE ISSCC Dig. Tech. Papers, pp. 540-541, February 2007.
51. S. Bozzola, D. Guermandi, A. Manzzanti, F. Svelto, An 11.5% frequency tuning, -184 dBc/Hz noise
FOM 54 GHz VCO, IEEE Radio Frequency Integrated Circuits Symposimum (RFIC), 2008, pp. 657-
660.
52. J-C Chien and L-H Lu, Design of Wide-Tuning-Range Millimeter Wave CMOS VCO With a
Standing-Wave Architecture, IEEE Journal of Solid-State Circuits, vol. 42, no 9, pp. 1942-1952,
September 2007.
53. Jos Luis Gonzlez Jimnez et al. A 56GHz LC-Tank VCO with 17% Tuning Range in 65nm Bulk
CMOS for Wireless HDMI Applications RFIC2009, Boston, June 09
54. E. Afshari, et al, Electrical funnel: A broadband signal combining method, IEEE International Solid-
State Circuits Conference, pp. 206207, Feb. 2006
55. A. Komijani, et al, A Wideband 77-GHz, 17.5-dBm Fully Integrated Power Amplifier in Silicon, IEEE
Journal of Solid State Circuits, Vol. 41, No. 8, Aug. 2006
56. S.T. Nicolson, et al, A Low-Voltage 77-GHz Automotive Radar Chipset, 2007 IEEE MTT-S Digest,
IMS 2007
57. Ullrich R. Pfeiffer, A 20dBm Fully-Integrated 60GHz SiGe Power Amplifier with Automatic Level
Control, IEEE 2006 ESSCIRC, Montreux, Sept. 2006
58. B. Floyd et al., SiGe Bipolar Transceiver Circuits Operating at 60GHz , IEEE Journal of Solid-State
Circuits, pp. 156-167, Jan. 2005
59. J. Alvarado, et al., 60-GHz LNA using a Hybrid Transmission Line and Conductive Path to Ground
Technique in Silicon, RFIC2007, Honolulu, June 2007
60. E. Laskin, et al., 80/160-GHz Transceiver and 140-GHz Amplifier in SiGe Technology , RFIC2007,
Honolulu, June 2007
61. S.T. Nicolson, et al, Design and Scaling of SiGe BiCMOS VCOs Above 100GHz, IEEE BCTM
2006
62. S. Pruvost, et al., A 40GHz Superheterodyne Receiver Integrated in 0.13m BiCMOS SiGe:C HBT
Technology, BCTM 2005
63. M. Bao, et al., A 21.5/43 GHz Dual-Frequency Balanced Colpitts VCO in SiGe Technology, IEEE
Journal of Solid State Circuits, Vol. 39, No. 8, Aug. 2004