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Printed Circuit Board Design Techniques for EMC ComplianceA Handbook for Designers, Second Edition
Printed Circuit Board Design
Techniques for EMC Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
ComplianceA Handbook
for Designers, Second by Mark I. Montrose
Edition
IEEE Press 2000
Wiley-Interscience-IEEE
ISBN 0-7803-5376-5
10 9 8 7 6 5 4 3 2
Montrose, Mark I.
Printed circuit board design techniques for EMC compliance: a handbook
for designers / Mark I. Montrose.--2nd ed.
p. cm.--(IEEE Press series on electronics technology)
"IEEE Electromagnetic Compatibility Society, sponsor."
Includes bibliographical references and index.
ISBN 0-7803-5376-5
J. B. Anderson
P. M. Anderson
J. E. Brewer
M. Eden
M. E. El-Hawary
R. F. Hoyt
S. V. Kartalopoulos
D. Kirk
M. S. Newman
M. Padgett
W. Reeve
G. Zobrist
EMC AND THE PRINTED CIRCUIT BOARD: Design, Theory, and Layout
Made Simple
Mark I. Montrose
MAGNETIC HYSTERESIS
To my Family
Acknowledgments
Those associated with the development of this edition are world-class
experts in PCB design and layout related to EMC. They scrutinized every
detail of this book for technical accuracy, format, and style of writing.
Mark I. Montrose
Santa Clara, California
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Table of Contents
Preface
Preface
Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
by Mark I. Montrose
IEEE Press 2000
Preface
Printed Circuit Board Design Techniques for EMC Compliance: A
Handbook for Designers, Second Edition, is a significant enhancement to
the first edition. The first edition was well received within the engineering
community worldwide and was translated into international languages. The
intent of the present volume is to expand upon concepts presented in the
earlier edition, to justify why a specific design technique works, and to
show when it is appropriate for use. Additional techniques based on
technological changes within the last few years are also incorporated.
These techniques and enhancements are based on questions, comments,
and discussions received from engineers around the world.
Printed Circuit Board Design Techniques for EMC Compliance will help
minimize the emission or reception of unwanted radio frequency (RF)
energy generated by components and circuits, thus achieving acceptable
levels of electromagnetic compatibility (EMC) for electrical equipment. The
field of EMC consists of two distinct areas:
1. Emissions: Propagation of electromagnetic interference (EMI) from
noncompliant devices (culprits) and, in particular, radiated and
conducted electromagnetic interference.
The companion book, EMC and the Printed Circuit Board: Design, Theory,
and Layout Made Simple explains in engineering terms how and why EMC
exists. The target audience for this edition is degreed engineers.
The main differences between my first and second books are as follows:
EMC and the Printed Circuit Board: Design, Theory, and Layout Made
Simple. This is a companion book for designers who want to know how
and why EMI is developed within a PCB. Although these designers may
not be directly accountable for the actual PCB layout, they may be
responsible for the end product. Engineers generally want to
understand technical concepts. This book elucidates a subject that is
generally not taught in universities or other educational environments,
again using a minimal amount of math.
Why worry about EMC compliance? After all, isn't speed the most
important design parameter as mandated by a marketing specification?
Internationally, legal requirements dictate the maximum permissible
interference potential of digital products. These requirements are based on
experience in the marketplace and are related to emission and immunity
complaints. Often, these same techniques will help improve signal quality
and signal-to-noise ratio performance.
This text discusses both high- and low-speed designs that require new and
expanded layout techniques for EMC suppression at the PCB level. Most
techniques used several years ago are now less effective for proper signal
functionality and compliance. Components have become faster and more
complex. Use of custom gate array logic, application-specific integrated
circuits (ASICs), ball grid arrays (BGAs), multichip modules (MCMs), flip
chip technology, and other digital devices operating in the sub-nanosecond
range present new and challenging opportunities for EMC engineers.
Technology is progressing at an incredible rate. It is becoming impossible
for an engineer to keep up with the technical details and aspects of various
logic devices available for use. Even if an engineer learns everything about
a new type of logic family, implementation of these devices on the PCB
may be overshadowed by other concerns. These concerns include
Input/Output (I/O) interconnects, mixed logic families, different voltage
levels, analog and digital components, and packaging requirements. The
design and layout of a PCB for EMI suppression at the source must always
be optimized, while maintaining systemwide functionality. This is a job for
both the electrical design engineer and the PCB designer.
Significant changes have been made in the second edition of this book,
including:
Addition of subject headers to various sections within the text for ease
of identification of the topic being discussed. In various places, two
items that were blended together in the first edition are now separated
to facilitate understanding.
Information in this edition will assist in PCB design and layout, with the
intent of meeting North American and international EMC compliance
requirements. Many different layout design methodologies exist. This book
illustrates generally applicable layout methods for EMC compliance, along
with a justification of why the technique works. The concepts presented will
vary for each particular PCB design.
Not only must a design work properly, it must also comply with international
regulatory requirements. Engineers who specialize in regulatory issues
must evaluate products based on different standards. The present guide
describes techniques that will alleviate existing conflicts among various
layout methods.
Mark I. Montrose
Santa Clara, California
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Table Of Contents
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Table of Contents
Chapter 1 - Introduction
Chapter 1
1.1: FUNDAMENTAL Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
DEFINITIONS
1.2: ELEMENTS OF THE by Mark I. Montrose
ELECTROMAGNETIC
IEEE Press 2000
ENVIRONMENT
1.3: NATURE OF
INTERFERENCE Recommend this title?
1.4: REGULATORY
REQUIREMENTSNORTH
AMERICA
1.5: REGULATORY
REQUIREMENTS
WORLDWIDE
1.6: STANDARDS
1.7: EMISSION
REQUIREMENTS
Chapter 1: Introduction
1.8: IMMUNITY
REQUIREMENTS
1.9: ADDITIONAL
REGULATORY
REQUIREMENTSNORTH
AMERICA
1.10: SUPPLEMENTAL
INFORMATION 1.1 FUNDAMENTAL DEFINITIONS
REFERENCES
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Table of Contents
Chapter 1 - Introduction
Chapter 1
1.1: FUNDAMENTAL Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
DEFINITIONS
1.2: ELEMENTS OF THE by Mark I. Montrose
ELECTROMAGNETIC
IEEE Press 2000
ENVIRONMENT
1.3: NATURE OF
INTERFERENCE Recommend this title?
1.4: REGULATORY
REQUIREMENTSNORTH
AMERICA
1.5: REGULATORY
REQUIREMENTS
WORLDWIDE
1.6: STANDARDS
1.7: EMISSION
REQUIREMENTS
1.2 ELEMENTS OF THE ELECTROMAGNETIC
1.8: IMMUNITY
REQUIREMENTS
ENVIRONMENT
1.9: ADDITIONAL
REGULATORY
REQUIREMENTSNORTH When an EMI problem occurs, the engineer needs to approach the
AMERICA
1.10: SUPPLEMENTAL situation logically. A simple EMI model has three elements:
INFORMATION
REFERENCES 1. There must be a source of energy.
3. There must be a coupling path between the source and receptor for
the unwanted energy transfer.
Figure 1.1: Items associated with the three elements of the EMI
environment.
The propagation path is the medium that carries the RF energy, such as
free space or interconnects (common impedance coupling).
Receptors are devices that easily accept interference from I/O cables,
or by radiated means, transferring this harmful energy to circuits and
devices susceptible to disruption.
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Table of Contents
Chapter 1 - Introduction
Chapter 1
1.1: FUNDAMENTAL Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
DEFINITIONS
1.2: ELEMENTS OF THE by Mark I. Montrose
ELECTROMAGNETIC
ENVIRONMENT IEEE Press 2000
1.3: NATURE OF
INTERFERENCE Recommend this title?
1.4: REGULATORY
REQUIREMENTSNORTH
AMERICA
1.5: REGULATORY
REQUIREMENTS
WORLDWIDE
1.6: STANDARDS
1.7: EMISSION
REQUIREMENTS 1.3 NATURE OF INTERFERENCE
1.8: IMMUNITY
REQUIREMENTS
1.9: ADDITIONAL
REGULATORY
EMC is grouped into two categories: internal and external. The internal
REQUIREMENTSNORTH
AMERICA
category is the result of signal degradation along a transmission path,
1.10: SUPPLEMENTAL including parasitic coupling between circuits in addition to field coupling
INFORMATION
REFERENCES between internal subassemblies, such as a power supply to a disk drive.
Stated more specifically, the problems are signal losses and reflections
along the path, along with crosstalk between adjacent signal traces.
2. Amplitude. How strong is the source energy level, and how great is its
potential to cause harmful interference?
When designing a PCB, we are concerned with current flow within the
assembly. Current is preferable to voltage for a simple reason: current
always travels around a closed-loop circuit following one or more paths. It
is to our advantage to direct or steer this current in the manner that is
desired for proper system operation. To control the path that the current
flows, we must provide a low-impedance, RF return path back to the
source of the energy. We must also divert interference current away from
the load or victim circuit. For those applications that require a high-
impedance path from source to the load, consider all possible paths
through which the return current may travel.
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Table of Contents
Chapter 1 - Introduction
Chapter 1
1.1: FUNDAMENTAL Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
DEFINITIONS
1.2: ELEMENTS OF THE by Mark I. Montrose
ELECTROMAGNETIC
ENVIRONMENT IEEE Press 2000
1.3: NATURE OF
INTERFERENCE Recommend this title?
1.4: REGULATORY
REQUIREMENTSNORTH
AMERICA
1.5: REGULATORY
REQUIREMENTS
WORLDWIDE
1.6: STANDARDS
1.7: EMISSION
REQUIREMENTS
1.8: IMMUNITY
1.4 REGULATORY REQUIREMENTSNORTH
REQUIREMENTS
1.9: ADDITIONAL AMERICA
REGULATORY
REQUIREMENTSNORTH
AMERICA
1.10: SUPPLEMENTAL
Electrical and electronic products generate RF energy. Electromagnetic
INFORMATION
REFERENCES
emission levels are set by rules and regulations mandated by domestic and
international governments or agencies. In the United States, the Federal
Communications Commission (FCC) regulates the use of radio and wire
communications. The FCC is an independent government agency,
responsible for ensuring interstate and international communication by
radio, television, satellite, and cable.
Digital computing products are classified into two categories: Class A and
B. The FCC and IC use the same definitions.
Class A: A digital device that is marketed for use in a commercial,
industrial, or business environment, exclusive of a device which is
marketed for use by the general public or is intended to be used in the
home.
If a product contains digital circuitry and has a clock frequency greater than
9 kHz, it is defined as a digital device and is subject to the rules and
regulations of the FCC and IC. Electromagnetic Interference (EMI) may
occur as a result of both digital and analog circuits. These products are
subject to domestic and international regulatory requirements.
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Table of Contents
Chapter 1 - Introduction
Chapter 1
1.1: FUNDAMENTAL Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
DEFINITIONS
1.2: ELEMENTS OF THE by Mark I. Montrose
ELECTROMAGNETIC
ENVIRONMENT IEEE Press 2000
1.3: NATURE OF
INTERFERENCE Recommend this title?
1.4: REGULATORY
REQUIREMENTSNORTH
AMERICA
1.5: REGULATORY
REQUIREMENTS
WORLDWIDE
1.6: STANDARDS
1.7: EMISSION
REQUIREMENTS 1.5 REGULATORY REQUIREMENTSWORLDWIDE
1.8: IMMUNITY
REQUIREMENTS
1.9: ADDITIONAL
REGULATORY
Test requirements, standards, and procedures have been harmonized on a
REQUIREMENTSNORTH worldwide basis. The principles discussed herein will allow regulatory
AMERICA
1.10: SUPPLEMENTAL compliance to be achieved with minimal development cost and shorter
INFORMATION
REFERENCES design cycles. The harmonization process is based on the work of expert
technical committees reporting to the International Electrotechnical
Commission (IEC).
The IEC works closely with the International Standards Organization (ISO),
which is chartered by the United Nations. Many countries throughout the
world are members. The IEC oversees the work of technical committees
working on a particular product sector. The IEC's objectives are to
"promote international co-operation on all questions of standardization ...
achieved by issuing publications including recommendations in the form of
international standards."
Two IEC technical committees work on EMC standards. The first is TC77,
Electromagnetic compatibility between equipment including networks. The
second committee is International Special Committee on Radio
Interference (Comit International Spcial des Perturbations
Radiolectriques or CISPR). CISPR publications deal primarily with limits
and measurements of the radio interference characteristics of potentially
disturbing sources or emissions. CISPR and IEC standards coexist to
define most technical aspects related to EMC compliance.
Although this book focuses on products that fall within the category of ITE,
many other product categories can use the information herein. For
emission requirements, conducted limits exist from 150 kHz to 30 MHz.
Radiated emissions are generally measured from 30 MHz to 1000 MHz, or
up to 100 GHz for special products and applications. Immunity tests differ,
based on product category, intended end-use environment, and
constructional details.
The most commonly referenced CISPR and IEC test publications for
products that incorporate printed circuit boards are listed in this section.
Appendix B repeats this information with greater detail. Many other test
publications and requirements also exist. This list is subject to periodic
changes owing to continuing developments in standards writing, along with
harmonization within the European Union (EU). The EU was formerly
known as the European Community (EC) or the European Economic
Community (EEC). This list is current at date of publication and is subject
to change without notice. The reader is urged to verify the applicable and
current requirements in force at the time of product design and release. For
this reason, the year of publication in the Official Journal of the European
Union (OJ), the date of withdrawal, amendment updates, and other
supporting information relating to date of publication or implementation are
not provided in this book.
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Table of Contents
Chapter 1 - Introduction
Chapter 1
1.1: FUNDAMENTAL Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
DEFINITIONS
1.2: ELEMENTS OF THE by Mark I. Montrose
ELECTROMAGNETIC
ENVIRONMENT IEEE Press 2000
1.3: NATURE OF
INTERFERENCE Recommend this title?
1.4: REGULATORY
REQUIREMENTSNORTH
AMERICA
1.5: REGULATORY
REQUIREMENTS
WORLDWIDE
1.6: STANDARDS
1.6.1: Basic Standards
1.6.2: Generic Standards
1.6 STANDARDS
1.6.3: Product Family
Standards
1.6.4: Classification of ITE Three tiers of standards have been generated: basic standards, generic
Products
1.7: EMISSION standards, and product family standards.
REQUIREMENTS
1.8: IMMUNITY
REQUIREMENTS
1.9: ADDITIONAL
REGULATORY
REQUIREMENTSNORTH
1.6.1 Basic Standards
AMERICA
1.10: SUPPLEMENTAL
INFORMATION
Basic standards are referenced within generic and product family
REFERENCES standards as a basis for performing a particular test. The standards include
most IEC and CISPR standards and are dedicated to aspects of EMC that
are of general interest to what all committees are working on, creating, or
developing other standards. This development work includes product
family standards. It is common for a product family standard to take the
appearance of a generic standard. Specific operational modes and
configurations are detailed in the standard, including performance criteria
and test levels.
Class A ITE. Class A ITE is a category of all other ITE that satisfies the
Class A ITE limits but not the Class B ITE limits. Such equipment should
not be restricted in its sale, but the following warning shall be included in
the instructions for use:
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Table of Contents
Chapter 1 - Introduction
Chapter 1
1.1: FUNDAMENTAL Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
DEFINITIONS
1.2: ELEMENTS OF THE by Mark I. Montrose
ELECTROMAGNETIC
ENVIRONMENT IEEE Press 2000
1.3: NATURE OF
INTERFERENCE Recommend this title?
1.4: REGULATORY
REQUIREMENTSNORTH
AMERICA
1.5: REGULATORY
REQUIREMENTS
WORLDWIDE
1.6: STANDARDS
1.7: EMISSION
REQUIREMENTS
1.7 EMISSION REQUIREMENTS
Product Family Standards
(sample list)
1.8: IMMUNITY The following list deals with emission requirements for the European
REQUIREMENTS
1.9: ADDITIONAL
Union. These standards are identified as product family standards.
REGULATORY
REQUIREMENTSNORTH
AMERICA
1.10: SUPPLEMENTAL
Product Family Standards (sample list)
INFORMATION
REFERENCES
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Table of Contents
Chapter 1 - Introduction
Chapter 1
1.1: FUNDAMENTAL Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
DEFINITIONS
1.2: ELEMENTS OF THE by Mark I. Montrose
ELECTROMAGNETIC
ENVIRONMENT IEEE Press 2000
1.3: NATURE OF
INTERFERENCE Recommend this title?
1.4: REGULATORY
REQUIREMENTSNORTH
AMERICA
1.5: REGULATORY
REQUIREMENTS
WORLDWIDE
1.6: STANDARDS
1.7: EMISSION
REQUIREMENTS
1.8 IMMUNITY REQUIREMENTS
1.8: IMMUNITY
REQUIREMENTS
Comprehensive List of To be able to certify compliance to the EMC Directive, 89/336/EEC,
Immunity Standards
1.9: ADDITIONAL manufacturers must construct products that meet not only emissions
REGULATORY
REQUIREMENTSNORTH requirements, but also immunity levels, or protection against harmful
AMERICA
1.10: SUPPLEMENTAL
disruption from other electronic equipment. Currently, only Europe requires
INFORMATION
REFERENCES
immunity testing. Since the IEC and CISPR are international organizations,
the scope of their work is used throughout the world. CENELEC adopts
basic standards developed by both IEC and CISPR, and publishes them as
harmonized standards to meet the EMC Directive. The European
harmonized document and IEC publication numbers are similar. The IEC
standard is prefixed with IEC 1000-4-X. When referenced as a European
harmonized document, this number is changed to EN 61000-4-X.
International IEC standards for immunity are provided in the IEC 1000-4-X
series. This series of standards describes the test and measurement
methods detailed within the basic standards. Basic standards are specific
to a particular type of EMI phenomenon, not a specific type of product. This
series covers the following:
Terminology
Instrumentation
The international IEC 1000-X series of standards, the most commonly used
immunity standards adopted or recommended by CENELEC, were
reissued using an EN 61000-X specification number. The EN 61000-4-X
series of immunity specifications are as follows:
Standard Description
EN 61000- Electrostatic discharge (ESD)
4-2
EN 61000- Radiated electromagnetic field
4-3
EN 61000- Electrical Fast Transient (EFT)/Burst
4-4
EN 61000- Surge
4-5
EN 61000- Conducted disturbance by RF fields
4-6
EN 61000- General guide on harmonics and interharmonics
4-7 measurements and instrumentation (not a
standard; procedure only)
EN 61000- 50/60 Hz magnetic field
4-8
EN 61000- Pulsed magnetic field
4-9
EN 61000- Oscillatory magnetic field
4-10
EN 61000- Voltage dips and interruption
4-11
EN 61000- Oscillatory waves "ring wave"
4-12
EN 61000- Oscillatory waves 1 MHz
4-13
EN 61000- Harmonics, interharmonics, and main signaling
4-14
EN 61000- Voltage fluctuations
4-15
EN 61000- Unbalance in three-phase mains
4-27
EN 61000- Variation of power frequency
4-28
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Table of Contents
Chapter 1 - Introduction
Chapter 1
1.1: FUNDAMENTAL Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
DEFINITIONS
1.2: ELEMENTS OF THE by Mark I. Montrose
ELECTROMAGNETIC
ENVIRONMENT IEEE Press 2000
1.3: NATURE OF
INTERFERENCE Recommend this title?
1.4: REGULATORY
REQUIREMENTSNORTH
AMERICA
1.5: REGULATORY
REQUIREMENTS
WORLDWIDE
1.6: STANDARDS
1.7: EMISSION
REQUIREMENTS
1.9 ADDITIONAL REGULATORY REQUIREMENTS
1.8: IMMUNITY
REQUIREMENTS NORTH AMERICA
1.9: ADDITIONAL
REGULATORY
REQUIREMENTSNORTH Other agency requirements in North America include those listed in Table
AMERICA
1.10: SUPPLEMENTAL 1.1. These standards are very specific and beyond the scope of this design
INFORMATION
REFERENCES guideline. A sample list is presented, given that printed circuit boards are
used in products covered by these standards.
Table 1.1: Additional North American Standards
Open table as spreadsheet
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Table of Contents
Chapter 1 - Introduction
Chapter 1
1.1: FUNDAMENTAL Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
DEFINITIONS
1.2: ELEMENTS OF THE by Mark I. Montrose
ELECTROMAGNETIC
ENVIRONMENT IEEE Press 2000
1.3: NATURE OF
INTERFERENCE Recommend this title?
1.4: REGULATORY
REQUIREMENTSNORTH
AMERICA
1.5: REGULATORY
REQUIREMENTS
WORLDWIDE
1.6: STANDARDS
1.7: EMISSION
REQUIREMENTS
1.10 SUPPLEMENTAL INFORMATION
1.8: IMMUNITY
REQUIREMENTS
1.9: ADDITIONAL In addition to EMC compliance, requirements exist for product safety.
REGULATORY
REQUIREMENTSNORTH These requirements include energy hazards and flammability. All printed
AMERICA
1.10: SUPPLEMENTAL
circuit boards are subject to high voltage and current levels that pose a
INFORMATION
REFERENCES
possible shock hazard to the user. In addition, extensive current flow on
traces generates heat, which can cause the fiberglass material used in the
construction of the printed circuit board to burn or melt with an associated
risk of fire. Components and interconnects placed on a printed circuit board
also provide a source of fuel (combustionable material) that may contribute
to a fire hazard under abnormal fault conditions.
The Appendixes of this book are an important part of this design guideline.
Much technical information is contained in all chapters. To assist during the
design and layout of a PCB, Appendix A, Summary of Design Techniques,
provides a brief overview of items discussed, cross-referenced to their
respective chapter. This summary may be used for quick review during the
layout and design stage.
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Table of Contents
Chapter 1 - Introduction
Chapter 1
1.1: FUNDAMENTAL Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
DEFINITIONS
1.2: ELEMENTS OF THE by Mark I. Montrose
ELECTROMAGNETIC
ENVIRONMENT IEEE Press 2000
1.3: NATURE OF
INTERFERENCE Recommend this title?
1.4: REGULATORY
REQUIREMENTSNORTH
AMERICA
1.5: REGULATORY
REQUIREMENTS
WORLDWIDE
1.6: STANDARDS
1.7: EMISSION
REQUIREMENTS
1.8: IMMUNITY
REQUIREMENTS
1.9: ADDITIONAL
REGULATORY
REQUIREMENTSNORTH REFERENCES
AMERICA
1.10: SUPPLEMENTAL
INFORMATION
REFERENCES
[1] Gerke, D., and W. Kimmel. 1994. "The Designer's Guide to
Electromagnetic Compatibility." EDN (January 20).
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Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
ASSIGNMENT
2.6: RADIAL MIGRATION
2.7: COMMON-MODE AND
DIFFERENTIAL-MODE
Chapter 2: Printed Circuit Board Basics
CURRENTS
2.8: RF CURRENT DENSITY
DISTRIBUTION
2.9: GROUNDING OVERVIEW
METHODOLOGIES
2.10: GROUND AND SIGNAL
LOOPS (EXCLUDING EDDY
CURRENTS)
Developing products that will pass legally required EMC tests is not as
2.11: ASPECT RATIO difficult as one might expect. Engineers often strive to design elegant
DISTANCE BETWEEN
GROUND CONNECTIONS products. However, elegance sometimes must be redefined to include
2.12: IMAGE PLANES
2.13: SLOTS WITHIN AN
product safety, manufacturing, cost, and, of course, regulatory compliance.
IMAGE PLANE
2.14: FUNCTIONAL
Such abstract problems can be challenging, particularly if engineers are
PARTITIONING
2.15: CRITICAL
unfamiliar with design or manufacturing procedures outside their
FREQUENCIES (/20) specialized field of engineering. This chapter examines only EMC-related
2.16: LOGIC FAMILIES
REFERENCES
aspects of a PCB and areas of concern during the design cycle.
6. Radial migration.
8. Grounding methodologies.
12. Partitioning.
Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
ASSIGNMENT
2.6: RADIAL MIGRATION
2.7: COMMON-MODE AND 2.1 HIDDEN RF CHARACTERISTICS OF PASSIVE
DIFFERENTIAL-MODE
CURRENTS
2.8: RF CURRENT DENSITY
COMPONENTS
DISTRIBUTION
2.9: GROUNDING
METHODOLOGIES
Traditionally, EMC has been considered "the art of black magic." In reality,
2.10: GROUND AND SIGNAL
LOOPS (EXCLUDING EDDY
EMC can be explained by complex mathematical concepts. Some of the
CURRENTS) relevant equations and formulas are complex and are beyond the scope of
2.11: ASPECT RATIO
DISTANCE BETWEEN this book. Even if mathematical analysis is applied, the equations become
GROUND CONNECTIONS
2.12: IMAGE PLANES too complicated for practical applications. Fortunately, simple models can
2.13: SLOTS WITHIN AN
IMAGE PLANE
be formulated to describe how, but do not directly explain why EMC
2.14: FUNCTIONAL
PARTITIONING
compliance can be achieved. We must remove the mystery from the
2.15: CRITICAL "Hidden Schematic" syndrome [2].
FREQUENCIES (/20)
2.16: LOGIC FAMILIES
REFERENCES Many variables exist that cause EMI because EMI is often the result of
exceptions to the normal rules of passive component behavior. A resistor
at high frequency acts as a series combination of inductance within the
leads of the resistor, in parallel with a capacitor across the two terminals. A
capacitor at high frequency acts as an inductor with a resistor in a series
combination on each side of the capacitor plates. An inductor at high
frequency performs as an inductor with a capacitor across the two
terminals, along with some resistance in the leads. The expected behavior
of passive, discrete components for both high and low frequencies is
illustrated in Fig. 2.1.
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Personal account | University of Southern Queensland
Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
ASSIGNMENT
2.6: RADIAL MIGRATION
2.7: COMMON-MODE AND 2.2 HOW AND WHY RF ENERGY IS DEVELOPED
WITHIN THE PCB
DIFFERENTIAL-MODE
CURRENTS
2.8: RF CURRENT DENSITY
DISTRIBUTION
2.9: GROUNDING
METHODOLOGIES Since hidden behavioral characteristics of passive components exist, we
2.10: GROUND AND SIGNAL
LOOPS (EXCLUDING EDDY
now investigate how RF energy is developed within the PCB. Both passive
CURRENTS)
2.11: ASPECT RATIO
and active digital components develop unwanted RF energy. The field of
DISTANCE BETWEEN
GROUND CONNECTIONS
EMC is described by a series of complex mathematical formulas identified
2.12: IMAGE PLANES as Maxwell's equations. These equations are based on the physics of
2.13: SLOTS WITHIN AN
IMAGE PLANE electromagnetics. Maxwell's four equations describe the relationship of
2.14: FUNCTIONAL
PARTITIONING
both electric and magnetic fields. These equations are derived from
2.15: CRITICAL Ampere's law, Faraday's law, and two from Gauss's law. The formulas are
FREQUENCIES (/20)
2.16: LOGIC FAMILIES complex and beyond the scope of this book, and are taught as an upper-
REFERENCES division course in electrical engineering at colleges and universities.
Excellent reference material is provided in the References section; these
works discuss how these integral and differential equations (calculus) are
derived, as well as their relationship to both static and time-varying fields.
(2.1)
Get MathML
For the standard impedance equation, various forms exist. For a wire, or a
PCB trace, Eq. (2.2) is the most applicable impedance equation. Within this
equation, we see both inductive and capacitive reactance.
(2.2)
Get MathML
(2.3)
Get MathML
For frequencies greater than a few kHz, the value of inductive reactance
typically exceeds R. Current takes the path of least impedance, Z. Below a
few kHz, the path of least impedance is resistive; above a few kHz, the
path of least reactance is dominant. Because most circuits operate at
frequencies above a few kHz, the belief that current takes the path of least
resistance provides an incorrect concept of how RF current flow occurs
within a transmission line structure or PCB trace.
Each trace has a finite impedance value. Trace inductance is only one
reason RF energy is developed within a PCB. Even the lead-bond wires
that connect a silicon die to its mounting pads may be sufficiently long to
cause RF potentials to exist. Traces routed on a board can be highly
inductive, especially traces that are electrically long. Electrically long traces
are those physically long in routed length such that the time for the round
trip of the signal does not return to the source driver before the next edge-
triggered event occurs, when viewed in the time domain. In the frequency
domain, an electrically long transmission line (trace) is one that exceeds
approximately /10 of the frequency that is present within the trace. If a RF
voltage travels through an impedance, we end up with RF current, per
Ohm's law. This RF current propagates and can cause noncompliance to
emission requirements. These examples help us to understand Maxwell's
equations and PCBs in extremely simple terms.
Figure 2.2 presents a simplified circuit. There is both a signal path and a
return path. Without a closed-loop circuit, a signal would never travel
through the transmission line (PCB trace) from source to load. When the
switch is closed, the circuit is complete.
Figure 2.3 is another representation of Fig. 2.2. The circuit on the left
represents a low-frequency network with a direct path for both signal and
return current. Every transmission line has a finite impedance value, which
consists of both resistance and inductance. For this circuit, the total
impedance value is small. Current will return without difficulty. For the
circuit on the right, the return path is not the same physical length as the
source path. Additional impedance has been added to the transmission line
due to this longer path. The longer the trace, the greater inductance
becomes. Using the impedance equation, Z = R + j2fL, as the frequency
of the circuit increases, the value of impedance, Z, will increase. With
additional inductance, total impedance, Z, will also increase. Resistance is
negligible for most applications and is usually ignored. For a very high-
frequency signal with a significant amount of inductance, the value of Z can
become very large. The impedance of free space is 377 ohms. It takes
very little inductance, in the frequency range between 100 kHz and 1 MHz,
to exceed 377 ohms. Because current (the DC element of the circuit) must
return to its source to satisfy Ampere's law, the RF energy (the AC current
element) will return through the lowest impedance path available. When
the impedance of the return path is greater than 377 ohms, free space
becomes the return and is observed as radiated EMI. The illustrations in
Fig. 2.3 show both high and low in frequency applicatons.
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Personal account | University of Southern Queensland
Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX
AND CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
Use of content on this site is expressly subject to the restrictions set forth in the Membership Agreement.
Books24x7 and Referenceware are registered trademarks of Books24x7, Inc.
Copyright 1999-2008 Books24x7, Inc. - Feedback | Privacy Policy (updated 03/2005)
Personal account | University of Southern Queensland
Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.4.1: Microstrip
2.4.2: Stripline
2.5: LAYER STACKUP
ASSIGNMENT
2.6: RADIAL MIGRATION
2.4 ROUTING TOPOLOGY CONFIGURATIONS
2.7: COMMON-MODE AND
DIFFERENTIAL-MODE
CURRENTS Two primary topologies are used when designing PCBs: microstrip and
2.8: RF CURRENT DENSITY
DISTRIBUTION
stripline; variations on each type exist. Figure 2.4 presents an illustrative
2.9: GROUNDING
METHODOLOGIES
overview of these topologies.
2.10: GROUND AND SIGNAL
LOOPS (EXCLUDING EDDY
CURRENTS)
2.11: ASPECT RATIO
DISTANCE BETWEEN
GROUND CONNECTIONS
2.12: IMAGE PLANES
2.13: SLOTS WITHIN AN
IMAGE PLANE
2.14: FUNCTIONAL
PARTITIONING
2.15: CRITICAL
FREQUENCIES (/20)
2.16: LOGIC FAMILIES
REFERENCES
2.4.1 Microstrip
Microstrip refers to traces located on the top and bottom, or outer layers of
a PCB. Microstrip provides minimal suppression of RF energy that may be
created within the PCB. Faster clock and logic signal propagation exists
over that of the stripline configuration. These faster signals are due to less
capacitive coupling and a lower unloaded propagation delay between
source and load. Capacitors are sometimes used on clock signals to slow
edge transitions of digital signals. With less capacitive coupling between
two solid planes, signals can propagate faster. The drawback of using
microstrip is that the outer layers of the PCB can occasionally radiate RF
energy to the environment, without the protection of a plane on both sides
of this outer circuit layer (Faraday shielding of both the top and bottom
sides of the routed traces).
2.4.2 Stripline
Stripline refers to placement of a signal layer between two solid planes: at
either voltage or ground potential. Stripline provides for enhanced noise
immunity against the propagation of radiated RF emissions, at the expense
of slower propagation speeds. Since the circuit (signal) plane is located
between solid planes, potential being irrelevant, capacitive coupling will
exist. Capacitive coupling between planes slows the edge transition rate of
high-speed signals. Capacitive coupling effects within the stripline topology
is observed on signals with edge transitions faster than 1 ns. The main
benefit of using stripline is complete shielding of RF energy generated from
internal traces radiating into free space.
One item to note is that radiation may still occur due to components
located on the outer layers of the assembly. Although internal signal traces
may not radiate RF energy, bond wires (internal to the component
package), lead frames, sockets, cables, and other interconnects still pose
significant problems for the design engineer. Depending on the impedance
between interconnects, a mismatch may exist within the transmission line
structure. This impedance mismatch may couple RF energy from internal
traces to other circuits, or free space, by radiated or conducted means,
including crosstalk. Minimizing lead inductance from components on the
top layers of the PCB will reduce radiated emissions effects.
A PCB is, in general, a dielectric structure with both internal and external
wiring that allows components and interconnects to be mechanically
supported and electrically connected together. In addition to providing a
mechanism for interconnecting components and connectors, a PCB also
provides a medium for component placement. A PCB is a composite of
organic and inorganic dielectric material with multiple layers assembled
together. Interconnects between layers are by passages, identified as vias.
These vias can be plated and filled with metal to provide electrical
connection between layers. Solid planar structures provide power and
ground to components. Signal lines are distributed among various layers to
provide interconnects. An important consideration in the design and
specification of a PCB includes both the propagation delay of a transmitted
signal and crosstalk between circuits, traces, and interconnects [3].
Board material has become more than just physical support for conductors.
Materials used form part of the circuit, dictating length, width, and spacing
of traces. It is important to remember that at frequencies above 500 MHz,
signal traces become part of the circuit which includes distributed
resistance, capacitance, and inductance. At higher frequencies, the
dimensions of the transmission line play an important role in defining
performance. Changing any dimension can dramatically alter board
performance.
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Books24x7 and Referenceware are registered trademarks of Books24x7, Inc.
Copyright 1999-2008 Books24x7, Inc. - Feedback | Privacy Policy (updated 03/2005)
Personal account | University of Southern Queensland
Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
ASSIGNMENT
2.5.1: Single-Sided
Assembly
2.5 LAYER STACKUP ASSIGNMENT
2.5.2: Double-Sided
Assembly
2.5.3: Four-Layer Stackup When designing a printed circuit board, a primary consideration is to determine how many routing layers and
2.5.4: Six-Layer Stackup
2.5.5: Eight-Layer Stackup power planes are required for functionality (within the context of acceptable costs). The number of layers is
2.5.6: Ten-Layer Stackup
2.6: RADIAL MIGRATION determined by functional specification, noise immunity (use of power planes), signal category separations, number
2.7: COMMON-MODE AND of nets (traces) to be routed, impedance control, component density of individual circuits, routing of buses, and the
DIFFERENTIAL-MODE
CURRENTS like. Proper use of stripline and microstrip topology is required not only for radio frequency (RF) suppression within
2.8: RF CURRENT DENSITY
DISTRIBUTION the PCB, but also for signal integrity purpose. If signal integrity is ensured, no reflections and ringing will result.
2.9: GROUNDING
METHODOLOGIES Thus, emissions will subsequently be reduced, too.
2.10: GROUND AND SIGNAL
LOOPS (EXCLUDING EDDY
CURRENTS) It is desirable to suppress RF energy on the PCB rather than to rely on containment by a metal chassis or
2.11: ASPECT RATIO
DISTANCE BETWEEN conductive plastic enclosure. The use of planes (voltage and ground) embedded in the PCB is one of the most
GROUND CONNECTIONS
2.12: IMAGE PLANES important methods of suppressing common-mode RF energy developed internal to the board. The advantage over
2.13: SLOTS WITHIN AN
IMAGE PLANE
most other design techniques is that these planes intrinsically contribute to reducing high-frequency power
2.14: FUNCTIONAL
PARTITIONING
distribution impedance.
2.15: CRITICAL
FREQUENCIES (/20)
2.16: LOGIC FAMILIES
The following stackup assignments are provided only as a guide to determining how to design a multilayer PCB for
REFERENCES optimal performance. These assignments are not cast in stone and must be modified as appropriate for
functionality reasons, based on the number of routing layers and power/ground planes required. The important
thing to notice is that each and every routing layer is adjacent to a reference (image) plane (power or ground), with
the exception of the outer microstrip layer and single-sided designs. The outer microstrip layer must contain only
slower speed traces without periodic signals or clocks rich in RF spectral energy. A summary of stackup
assignments is provided in Table 2.1, at the end of this section.
Table 2.1: Example of Stackup Assignments
Open table as spreadsheet
Stackup 1 2 3 4 5 6 7 8 9 10
2 layers S1 & S2 &
ground power
4 layers S1 ground power S2
two
routing
two
planes
4 layers ground S1 S2 power
two
routing
two
planes
6 layers S1 S2 groumd power S3 S4
four
routing
two
planes
6 layers S1 ground S2 S3 power S4
four
routing
two
planes
6 layer S1 power ground S2 ground S3
three
routing
three
planes
8 layers S1 S2 ground S3 S4 power S5 S6
six
routing
two
planes
8 layers S1 ground S2 ground power S3 ground S4
four
routing
four
planes
10 layers S1 ground S2 S3 ground power S4 S5 ground S6
six
routing
four
planes
10 layers S1 S2 power ground S3 S4 ground power S5 S6
six
routing
four
planes
S = signal routing layer
For the following stackup examples, observe that where three or more reference planes are provided (e.g., one
power and two ground planes), optimal performance of high-speed signal traces may be achieved when routed
adjacent to a plane at 0V-reference, not adjacent to the power plane. The reason for this statement is one of the
basic fundamental concepts of performing EMI suppression techniques within a PCB.
A plane at 0V-potential is generally screw secured to a metal chassis, thus causing this reference plane to be
forced at ground potential. If the reference plane is also at ground potential, this reference plane will be unable to
change voltage potential levels, which is one cause of ground bounce and board-induced noise voltage. If the 0V-
reference plane is tied hard to ground, common in many designs, only the power plane will modulate at switching
frequencies of the assembled PCB; thus, this is one less item to worry about.
Research [4] has shown that known IC sources switch significant current within a PCB, relative to the location of
the reference planes within a PCB stackup. Capacitive coupling from IC packages to significant metal structures,
including heatsinks and nearby shielding enclosures walls, can lead to significant radiated EMI from switching
components. This coupling can be exacerbated or minimized by different choices of layer stackup. A ground plane
incorporated as the first layer within a multilayer stackup (Layer 2), instead of the power plane, may provide for
enhanced suppression of RF energy owing to reduced parasitic capacitive coupling to the enclosure. This
consideration must be remembered when assigning a stackup methodology.
It is recommended that use of single-sided PCBs be reserved for circuits operating below a few hundred kHz. This
low-frequency value is due to various design aspects related to high-frequency circuit requirements, including the
applicability of skin effect on traces (traces become highly inductive at high frequencies), the lack of a proper RF
return path related to closed-loop circuit requirements, and the need for optimal ground loop control to prevent
development of magnetic fields and loop antennas. In addition, single-sided PCBs are highly susceptible to
external RF influences such as ESD, fast transient, and radiated/conducted RF susceptibility. The need for
termination and layout techniques for signal integrity is not a primary concern, as the edge transition rate is usually
not very fast and the physical dimensions of the PCB usually exceed transmission line lengths. In addition, any I/O
interconnects will perform beautifully as a radiating antenna, owing to the lack of a RF return path and the need for
flux cancellation.
The easiest approach to the design and layout of a single-sided PCB is to begin by developing the power and
ground structure (traces). Next come high-threat signals (clocks), which must be routed adjacent to the ground
traces as close as physically possible. After these two steps are completed, the rest of the design can be finalized.
The following requirements are mandatory:
1. Identify all power and ground sources, along with critical signal nets.
2. Partition the layout into functional subsections. Take into consideration requirements of sensitive components
and their physical relationship to I/O ports and interconnects.
3. Position all components with critical signal nets adjacent to each other.
4. If different ground nodes are required, determine if they are to be connected together, and if so, where.
5. Route the rest of the board, keeping in mind the need for flux cancellation for traces rich in RF spectral
energy, along with the need for ensuring that a RF return path is available at all time.
Figure 2.6 is the worst type of layout for single-sided designs and should "never" be implemented. This is because
excessive loop areas are present within the power and ground distribution network. In addition, no provisions exist
for a RF return path for critical traces. Note that this figure shows use of dual-in-line components with the same
physical dimensions. In real practice, this type of configuration does not exist, as components with different
package sizes and the number and type of traces will always be used. The important item to note is the concept
behind why this configuration is a very poor layout.
For single-sided PCBs, only one conceptual design technique provides for suppression of RF energy.
Asymmetrically placed component package sizes, along with unique power requirements, are becoming standard
with today's products. With use of these components, Fig. 2.7 becomes applicable during the design cycle. The
layout topology of Fig. 2.7 is commonly found in analog systemsless than 1 kHzand in nearly all low-speed,
low-technology digital products. Note the use of radial routing of the power and ground traces in the figure versus
that of Fig. 2.6.
Figure 2.7: Single-layer stackup with radial structure for power routing and flow migration.
Radial routing means that all traces emanate from a single-source location. Signal trace routing becomes easier,
as direct-line routing is possible, in addition to ease of connection between radial points. The important item to
note is that one must not connect the power and ground traces together on the top part of the PCB in the figure.
The reason for this requirement is easy to visualize. A ground loop would be created, thus defeating use of radial
routing, making this layout appear similar to the one that was shown in Fig. 2.6. The only problem with this layout
is to determine how to optimally make the connection to the power connector with different radial structures. The
PCB designer must be creative in learning how to implement this technique while maintaining the following for
optimal performance:
1. Route all power and ground traces in a radial fashion from the power supply. Minimize total routed length of
traces.
2. Route all ground and power traces adjacent (parallel) to each other. This minimizes loop currents that may
be created by high-frequency switching noise (internal to the components) from corrupting other circuits and
control signals. Ideally, these traces should be separated by a distance greater than the width of any
individual trace only when they must be separated for connection to the decoupling capacitor. Signal flow
should parallel these return paths.
3. Prevent loop currents by not tying different branches of a tree to another branch.
In Fig. 2.7, the following is to be noted. For a high-frequency application, control the surface impedance (Z) of all
signal traces and their return current path. When used in a low-frequency application, instead of attempting to
control the impedance of the traces, one must control the topology layout.
Figure 2.8: Two-layer PCB with power and ground grid structure.
Run power and circuit traces at 90-degree angles to each other, power on one layer, ground on the other.
Place ground traces on one layervertical polarization; place power traces on the other layerhorizontal
polarization, or vice versa.
Locate decoupling capacitors between the power and ground traces at all connectors and at each IC.
For Fig. 2.9, a return trace must be placed as physically close to the high-threat signal trace as possible to permit
RF energy to complete its return path back to the source. The power and return trace must also be routed parallel
to each other, with decoupling capacitors provided for each and every component that injects switching energy
into the power distribution system. With this topology, difficulties in routing may occur. However, significant
benefits will be achieved, related to EMC compliance.
Figure 2.9: Enhanced double-sided routing to accommodate RF return currents.
When a gridded power and ground layout methodology is used, care must be taken to guarantee that the grids are
tied together in as many places as possible. If a grid is not provided, RF loop currents from components will not
find a low-impedance return path by any reliable means, thus exacerbating emissions. Routing power and return
traces adjacent to each other, using parallel routes, allows for a low-impedance, small-loop area transmission line
structure or antenna to exist. With a small-loop area, the RF energy developed will be at such a high frequency
that the signals measured may be in the upper MHz range and thus may not pose problems for EMC compliance.
The signal traces referenced to the 0V-return can still create significant current loops, if the distance spacing
between the trace and 0V-reference is excessively large.
A problem with double-sided PCBs is how traces are routed between components when a power and ground grid
exists. In almost every application, it becomes impractical to fully grid a double-sided board. The most optimal
layout technique is to use ground fill to substitute as an alternative return path for loop area control and reduced
impedance for RF return currents. This ground fill must be connected to the 0V-reference point in as many
locations as possible.
The second layout methodology (Fig. 2.9) for double-sided PCBs is identical to that in Fig. 2.8. The only difference
lies in routing of the power and ground traces on both the top and bottom layers. By having two layers available,
routing becomes easier to achieve, with loop areas remaining as small as possible.
It is important to note, especially for EMC compliance, that there is no such thing as a double-sided PCB, although
they physically exist. For example, when analyzing a double-sided stackup related to EMC compliance, with
standard thickness of 0.062 in. (1.6 mm), the physical distance spacing between the top layer (with components)
and bottom layer (with a ground plane or 0V-reference) is often assumed to provide a return path for RF currents
present within the top layer. This is illustrated in Fig. 2.10. In reality, the distance spacing between the signal trace
and the return plane is physically large compared to the distance spacing between traces. This large physical
distance between trace and plane does not allow for optimal flux cancellation. For this example, the field
distribution within the signal trace is approximately one trace width. The physical distance of the field distribution
between traces is magnitudes less than the physical distance between trace and reference plane on the opposite
side of the PCB. This means that any RF return path that is greater than one trace width distance from the signal
source is too far away to perform for optimal return flux cancellation, related to the development of RF energy.
Figure 2.10: Example why two-layer stackups are not efficient for removing RF energy.
The best way to approach a double-sided PCB design is to think of the board as two single-sided designs. Route
both the top and bottom layers of the PCB using design rules and techniques appropriate for single-sided designs.
Ground loop control must be maintained at all times, along with a provision for RF return current to exist.
Fill material
Symmetrical Stackup
Signal traces will have a higher impedance, somewhere between 105 and 130 ohms.
Interplane decoupling to remove switching energy from the power and ground planes is moderate (some
benefit).
RF return currents do not have the ability to return to their source uninterrupted, unless a ground trace is
routed on the signal layer adjacent to the power plane.
Asymmetrical Stackup
Impedance of the routing layers can be specified and set to a desired value.
Interplane decoupling benefits are basically nonexistent. Extensive use of discrete decoupling capacitors is
now required.
RF return currents do not have the ability to return to their source uninterrupted, unless a ground trace is
routed on the signal layer adjacent to the power plane.
The fill layer (prepreg in this case) is difficult to manufacture at this thickness level.
A second stackup configuration is shown in Fig. 2.12, with the outer layers at power and ground potential, and
signal traces routed internally. Use of fill material to make an asymmetrical stackup is also possible, as shown in
Fig. 2.11.
The PCB is difficult to manufacture, as the outer planes function as one large heatsink during the wave-solder
process, causing possible cold solder joints to develop. If both layers are at ground potential, then power must
be routed as a trace on a signal plane. No decoupling will exist. Extensive use of discrete capacitors is now
required.
RF energy associated with the traces is prevented from radiating to the environment. However, this energy will
be transferred to the lead-bond wires of the components located on the outer layers. These components will
radiate all internal RF energy, if a proper RF return path is not designed into the assembly.
This configuration gives a lower power/ground plane impedance than a four-layer assembly. Having this lower
impedance improves overall decoupling for components. The routing plane (Layer 2) adjacent to the ground plane
is preferred for routing traces rich with RF spectral energy. Although the alternative routing layer for other high-
threat signals, Layer 5, is available, provisions must be made to ensure that a RF return path exists for all traces
routed on Layer 5. The two outer microstrip layers are inappropriate for routing any traces susceptible to an
externally induced RF event (e.g., electrostatic discharge, electrical fast transient).
The following is a list of trace impedance values for a PCB stackup with overall thickness of 62 mils (0.062 in. or
1.6 mm) and dielectric constant of 4.3. The routing layers use a symmetrical stackup. Symmetrical stackup means
that the distance spacing between all layers is 0.010 in. (10.0 mils or 0.25 mm). The weight of the copper is 1 oz.
The impedance values listed are approximate and subject to 5% tolerance, since different parameters may be
used for calculating trace impedance from that shown in the following list. If impedance-controlled transmission
lines are required, jumping traces between the outer microstrip and embedded microstrip layers are not advised
owing to the extensive impedance mismatch present. Chapter 4 presents the equations that allow us to calculate
trace impedance.
Trace Width
5.0 mils0.005 in. (0.13mm): Outer microstrip110 , embedded microstrip79 .
The advantages and disadvantages of this stackup assignment depend on how the design is to be implemented,
along with signal integrity concerns. The advantages include a lower impedance value between routing layers
(enhanced signal integrity), along with a shielding effect of the planes from allowing RF energy to propagate to the
environment. One disadvantage is that there is practically no decoupling between the power and ground plane.
Consequently, a significant number of discrete capacitors will be required, adding material cost along with taking
up real estate during placement. Although self-shielding occurs owing to the stripline planes, component radiation
will still be present.
An alternative version of Configuration 2 is to provide fill material between Layers 3 and 4 (Signal 2 and 3). By
keeping the overall outside dimension constant, the distant spacing between layers must become smaller. A
smaller distant spacing between routing layers and a reference plane will reduce the impedance of the
transmission line, allowing us to have more closely matched impedance for the transmission lines when jumping
layers. The disadvantage of applying fill material is that this extra distance spacing minimizes any benefit from
planar decoupling.
The impedance values for Configuration 2, using the same constraints detailed in Configuration 1, are as follows:
Trace Width
5.0 mils0.005 in. (0.13mm): Outer microstrip84 , stripline68 .
Configuration 3 is a different type of layer stackup, with three routing planes and three reference planes. This
configuration is not realistic owing to the large overhead of solid copper layers (50%). This stackup assignment is
far from optimal. It is common practice to construct PCBs with symmetry between layers. The purpose of
discussing this stackup arrangement is to illustrate a concept.
Two of the planes in Configuration 3 are at ground potential. One would use this type of topology because there
are too many traces to be routed on a four-layer board but not enough to justify four routing layers. With this
situation, converting one signal plane to a ground plane has significant advantages, especially enhanced
decoupling capabilities and lower transmission line impedance. With two ground planes (Layers 3 and 5), high-
threat signals (clocks) must be routed on Layer 4. With this configuration, a coaxial transmission line structure is
present, which is optimal for signal integrity and suppression of EMI energy.
If Layers 2 and 3 were swapped, with the power plane in the middle of the board, one feature would become
noticeable. Two different sets of decoupling capacitor are now present, each with a different self-resonant
frequency and level of performance. The disadvantage of this configuration lies in having the routing layer
sandwiched between two planes of different polarities, which minimizes optimal RF return current flow. RF current
can now only jump layers at a location where decoupling capacitors are located. Component radiation still occurs.
Impedance values for Configuration 3, using the same constraints detailed in Configuration 1, are presented in the
following list. Notice that the impedance of all routing layer is less, which is desired for signal integrity concerns, if
layer jumping occurs or signal integrity issues are important.
Trace Width
5.0 mils0.005 in. (0.13mm): Outer microstrip84 , stripline59 .
This configuration is not an optimal stackup for several reasons. Designers who need six routing layers will use
this methodology because it is the only one available. Disadvantages lie in very poor decoupling, layer jumping
between reference planes with different polarities, and two microstrip layers on each side which can radiate RF
energy. The optimal layers to route clock and high-threat signals are Layers 2 and 4 (Signal 2 and Signal 3). This
is required is because traces rich with RF spectral energy will have a continuous RF return path to complete the
closed-loop requirements against the same reference plane. Although one can route clocks on Layer 5 (Signal 4),
RF return current will bounce between the power and ground planes, which may exacerbate development of RF
energy. Because flux cancellation occurs between a signal plane and reference plane, an embedded microstrip
layer will not radiate any more than a trace routed stripline with RF energy transferred through vias. Transference
of RF energy through vias allows components to pick up the energy and radiate as EMI.
Impedance values for this eight-layer stackup are listed in the following, with the exception that the distance
spacing between layers is 7.0 mils (0.007 in. or 0.028 mm) in order to maintain an overall thickness of 62 mils
(0.062 in. or 1.6 mm). Notice that the impedance of the embedded microstrip and stripline layers is closer in value,
which enhances signal integrity. The impedance of the outer microstrip layer is very high, and should not be used
for routing impedance-controlled or high-threat signal traces, including clocks.
Trace Width
5.0 mils0.005 in. (0.13mm): Outer microstrip99 , embedded microstrip68 , stripline58 .
The next stackup assignment is excellent for both signal integrity and EMC.
The advantages of using this stackup assignment lie in excellent decoupling (low power/ground impedance) and
enhanced flux cancellation (minimization). The fill material is extra thickness added to the assembly. This
separation distance forces magnetic flux on Layer 6 (Signal 3) to be captured by the ground plane and not the
power plane; it allows for an optimal RF return path to exist. The disadvantage of this stackup is that various
impedance values are present, which may be harmful for signal integrity concerns if layer jumping occurs between
the microstrip and stripline layers. As detailed in the figure, Layers 3 and 6 (Signals 2 and 3) have almost the
same impedance. Hence, both routing layers are excellent for signal integrity and RF flux cancellation; it is the
best possible configuration.
Impedance values for this eight-layer stackup, using the same constraints detailed in Configuration 1, are
presented in the following list, with the exception that the distance spacing between layers has to be modified.
Distance spacing between layers is now at 7.0 mils (0.007 in. or 0.028 mm). The fill material between the power
plane (Layer 5) and Signal 3 (Layer 6) is 10.0 mils thick0.010 in., or 0.25 mm. With this additional thickness,
distance spacing between the power and ground plane is reduced to 4 mils0.006 in. (0.13 mm). This distance
modification allows us to maintain an overall thickness of 62 mils (0.062 in. or 1.57 mm).
Trace Width
5.0 mils0.005 in. (0.13mm): Signals 1 and 472 , Signal 250 , Signal 354 .
6.0 mils0.006 in. (0.15mm): Signals 1 and 468 , Signal 246 , Signal 350 .
8.0 mils0.008 in. (0.20mm): Signals 1 and 460 , Signal 240 , Signal 344 .
10.0 mils0.010 in. (0.25mm): Signals 1 and 454 , Signal 235 , Signal 339 .
Two sample configurations are detailed for a ten-layer stackup. These two assignments have the same number of
routing and reference planes, except for the physical placement of the planes. The important item to note is the
physical location of the routing plane relative to a reference plane (at 0-V potential), along with enhanced
impedance control.
Impedance values for this ten-layer stackup is shown in the following listing. Distance spacing between all layers
is 5.0 mils0.005 in. (0.13 mm), while the fill is 8.0 mils (0.008 in. or 0.20 mm). The distance between the power
and ground plane pair is 4.0 mils0.004 in. (0.10 mm). This stackup is based on a 62 mil (0.062 in. or 1.6 mm)
thick PCB. Ten-layer PCBs are generally built at the next standard thickness of 93 mils (0.093 in. or 2.4 mm).
Impedance calculations for a 93 mil thick PCB is not provided for this particular stackup example. The fill material
in Fig. 2.15 illustrates a concept, although use of fill is usually not required, or desired, for this particular example.
Trace Width
5.0 mils0.005 in. (0.13mm): Outer microstrip99 , embedded microstrip68 , stripline58 .
The advantage of this stackup assignment lies in having two optimal routing layers for clock and other high-threat
signal traces. By locating the power and ground planes in the order shown, Layers 5 and 6 are surrounded by two
ground planes. This structure simulates a coaxial cable. Decoupling effects are now available for two separate
voltage sources.
Impedance values for this ten-layer stackup is shown in the following list. Distance spacing between all layers is
5.0 mils0.006 in. (0.13 mm). This stackup is based on a 62 mil (0.062 in. or 1.57 mm) thick PCB. Ten-layer PCBs
are generally built at the next standard thickness of 93 mils (0.093 in. or 2.4 mm).
Trace Width
5.0 mils0.005 in. (0.13mm): Outer microstrip88 , embedded microstrip58 , stripline50 .
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Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
ASSIGNMENT
2.6: RADIAL MIGRATION
2.7: COMMON-MODE AND
2.6 RADIAL MIGRATION
DIFFERENTIAL-MODE
CURRENTS
2.8: RF CURRENT DENSITY
Radial migration deals with the transfer of electromagnetic energy from a
DISTRIBUTION
2.9: GROUNDING
high-bandwidth section, such as a central processing unit (CPU) or
METHODOLOGIES
2.10: GROUND AND SIGNAL
frequency-generating circuits, to lower speed sections, which include I/O
LOOPS (EXCLUDING EDDY interconnects (Fig. 2.16). Radial migration signifies that as the energy from
CURRENTS)
2.11: ASPECT RATIO one circuit progress from a high-bandwidth area to a low-bandwidth area,
DISTANCE BETWEEN
GROUND CONNECTIONS the signal will observe an intrinsic propagation delay. This slowing of signal
2.12: IMAGE PLANES
2.13: SLOTS WITHIN AN
propagation occurs because all components have input capacitance along
IMAGE PLANE
2.14: FUNCTIONAL
with an internal propagational delay. Each device thus slows the edge rate
PARTITIONING transition (tr) of the propagated signal. In addition, slower speed
2.15: CRITICAL
FREQUENCIES (/20) components are generally provided for I/O interconnects. With high-
2.16: LOGIC FAMILIES technology products, including networking and graphical interfaces, the
REFERENCES
concept of radial migration is generally ignored, as high-bandwidth
components are required everywhere, especially in the I/O section. As
circuits cascade from the CPU area to I/O, one can sum up delays (like a
filter) until the high-bandwidth spectral components are slowly decreased
from the system and I/O circuits.
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Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
ASSIGNMENT
Differential-mode signals
1. Convey desired information, since most signal traces are a single-
ended route (source-to-load). This is the differential mode of data
transmission.
In Fig. 2.18, current source, I1, represents the flow of current from voltage
source, E, to load, Z. Current flow, I2, is current that is observed in the
return system, usually identified as an image plane, ground plane, or 0V-
reference. The measured radiated electric field of the common-mode
current is caused by the summed contribution of both I1 and I2.
A simple analogy that helps explain one way that common-mode energy is
developed is to analyze Fig. 2.18 in very simple terms. Assume 1 watt of
power is sent from the source to the load. The load dissipates one-half watt
of power. This means that current in path I2 is one-half watt. Under this
situation, violation of Ampere's law occurs, which states that the sum of the
current in a circuit must equal zero. Visualize now that one-half watt travels
toward the source. At the same time, one-half watt travels back from
source to load. Mathematically, if we take the limit of the current to zero at
any particular point of time, we observe that half of the energy is traveling
left, while the other half is traveling right. The summation of these two
currents at any particular point of time equals the source current, I1; hence
Ampere's law is satisfied. This residual one-half watt of power is added to
the 1 watt in the source trace. This means that a total of 1-1/2 watts of
power is present across the load. This energy is common-mode and is
significantly greater than differential-mode current.
An RF current return path is best achieved with a solid plane for multilayer
PCBs or a ground trace for single- and double-sided boards. The RF
current in the return path will couple with RF current in the source path
(magnetic flux lines traveling in opposite direction to each other). This
coupling provides for flux cancellation or minimization, as seen in Fig. 2.19.
Figure 2.19: RF current return path and distance
spacing.
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Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
ASSIGNMENT
2.6: RADIAL MIGRATION
2.7: COMMON-MODE AND
DIFFERENTIAL-MODE
2.8 RF CURRENT DENSITY DISTRIBUTION
CURRENTS
2.8: RF CURRENT
DENSITY DISTRIBUTION
A 0V-reference or return plane allows RF current to return to its source
2.9: GROUNDING
METHODOLOGIES
from a load. This return plane completes the closed-loop circuit
2.10: GROUND AND SIGNAL requirements for functionality. Current distribution in traces tends to spread
LOOPS (EXCLUDING EDDY
CURRENTS) out within the return structure, as illustrated in Fig. 2.20. This distribution
2.11: ASPECT RATIO
DISTANCE BETWEEN will exist in both the forward direction and the return path. Current
GROUND CONNECTIONS
2.12: IMAGE PLANES distribution shares a common impedance between trace and plane (or
2.13: SLOTS WITHIN AN
IMAGE PLANE
trace-to-trace), which results in mutual coupling due to the current spread.
2.14: FUNCTIONAL The peak current density lies directly beneath the trace and falls off sharply
PARTITIONING
2.15: CRITICAL from each side of the trace into the ground plane structure.
FREQUENCIES (/20)
2.16: LOGIC FAMILIES
REFERENCES
When the distance spacing is far apart between trace and plane, the loop
area between the forward and return path increases. This return path
increase raises the inductance of the circuit where inductance is
proportional to loop area. The current distribution as described in Eq. (2.4)
also minimizes the total amount of energy stored in the magnetic field
surrounding the signal trace [7].
(2.4)
Get MathML
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Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
ASSIGNMENT
2.6: RADIAL MIGRATION
2.7: COMMON-MODE AND
2.9 GROUNDING METHODOLOGIES
DIFFERENTIAL-MODE
CURRENTS
2.8: RF CURRENT DENSITY Different types of grounding methods are commonly used. The word
DISTRIBUTION
2.9: GROUNDING "ground," by itself is vague and does not represent any specific function
METHODOLOGIES
2.9.1: Single-Point
within electrical engineering. An adjective must precede the word "ground"
Grounding
2.9.2: Multipoint Grounding
to distinguish the type of ground referenced for a particular application.
2.10: GROUND AND SIGNAL
LOOPS (EXCLUDING EDDY
Different types of grounding methodologies include the following. All can be
CURRENTS) present simultaneously or only one at a time: digital, analog, signal,
2.11: ASPECT RATIO
DISTANCE BETWEEN common, noisy, quiet, isolated, earth, single-point, multipoint, hybrid,
GROUND CONNECTIONS
2.12: IMAGE PLANES chassis, safety, frame, and so on. One grounding topology always
2.13: SLOTS WITHIN AN
IMAGE PLANE
forgotten is RF ground.
2.14: FUNCTIONAL
PARTITIONING
2.15: CRITICAL Figures 2.22 through 2.24 illustrate three grounding methods: single-point,
FREQUENCIES (/20)
2.16: LOGIC FAMILIES
multipoint, and hybrid.
REFERENCES
Single-point grounds are usually formed with signal radials and are
commonly found in audio circuits, analog instrumentation, and 60-Hz and
dc power systems, along with products packaged in plastic enclosures.
Although single-point grounding is commonly used for low-frequency
products, it is occasionally found in extremely high-frequency circuits and
systems.
10 MHz 2.1 10
-3 0.00082
1 GHz 2.1 10
-4 0.0082
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Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
ASSIGNMENT
2.6: RADIAL MIGRATION
2.7: COMMON-MODE AND
2.10 GROUND AND SIGNAL LOOPS (EXCLUDING
DIFFERENTIAL-MODE
CURRENTS
EDDY CURRENTS)
2.8: RF CURRENT DENSITY
DISTRIBUTION
2.9: GROUNDING Ground loops are a major contributor to the development and propagation
METHODOLOGIES
2.10: GROUND AND of RF energy. RF current will attempt to return to its source through any
SIGNAL LOOPS
(EXCLUDING EDDY
available path or medium: components, wire harnesses, power or ground
CURRENTS) planes, adjacent traces via crosstalk, and so forth. RF current always
2.11: ASPECT RATIO
DISTANCE BETWEEN exists between source and load. This presence is due to the need to have
GROUND CONNECTIONS
2.12: IMAGE PLANES a closed loop for the signal and return path. This loop develops a voltage
2.13: SLOTS WITHIN AN
IMAGE PLANE
potential difference between two devices, regardless of whether inductance
2.14: FUNCTIONAL
PARTITIONING
exists between these points. Inductance in a transmission line causes
2.15: CRITICAL magnetic coupling of RF current to occur between a source and victim
FREQUENCIES (/20)
2.16: LOGIC FAMILIES circuit, increasing RF losses in the return path [1].
REFERENCES
One of the most important design considerations for incorporating EMI
suppression techniques within a PCB is to provide optimal ground or signal
return loop control. Engineering analysis must be made for every ground
stitch connection (mechanical securement between the PCB ground and
chassis ground) to the 0V-reference structure, related to RF return currents
developed by RF noisy electrical circuits. To minimize ground voltage
potential, high-speed logic and frequency generating components must be
located as close as possible to a ground stitch. Placing RF generating
components near or adjacent to ground stitch locations will minimize RF
current loops, which will develop into the form of eddy currents within the
chassis structure. It is imperative that all unwanted RF energy be diverted
into the 0V-reference structure.
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Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
ASSIGNMENT
2.6: RADIAL MIGRATION
2.7: COMMON-MODE AND
DIFFERENTIAL-MODE 2.11 ASPECT RATIODISTANCE BETWEEN GROUND
CURRENTS
2.8: RF CURRENT DENSITY
DISTRIBUTION
CONNECTIONS
2.9: GROUNDING
METHODOLOGIES
2.10: GROUND AND SIGNAL Aspect ratio is a term commonly used to define the ratio of width to height.
LOOPS (EXCLUDING EDDY
CURRENTS)
The term also refers to the ratio of a longer dimension to a shorter one.
2.11: ASPECT RATIO
DISTANCE BETWEEN
With this definition, how does aspect ratio relate to EMC and PCBs? When
GROUND CONNECTIONS providing ground stitch connections in a PCB using multipoint grounding to
2.12: IMAGE PLANES
2.13: SLOTS WITHIN AN
a metallic enclosure, the distance spacing between ground stitch location
IMAGE PLANE
2.14: FUNCTIONAL
must be determined in all directions: x- and y-axis [1].
PARTITIONING
2.15: CRITICAL
FREQUENCIES (/20) RF currents that exist within the power and ground plane network tend to
2.16: LOGIC FAMILIES couple to components, cables, peripherals, or other electronic items within
REFERENCES
the assembly. This undesirable coupling may cause improper operation,
functional signal degradation, or EMI. When using multipoint grounding to a
metal chassis, by providing a third wire ground connection to the AC
mains, RF ground loops become a significant design concern. This
configuration is typical with personal computers. An example of a single-
point ground connection for a personal computer is shown in Fig. 2.26.
How can we minimize RF loops that may occur within a PCB assembly?
The easiest way is to design the PCB with many ground stitch locations to
chassis ground, if chassis ground is provided within a multilayer assembly.
The question that arises is, How far apart do we make the ground
connections from each other, assuming the designer has the option of
specifying where the ground stitch location will occur when implementing
this design technique?
The distance spacing between ground stitch locations should not exceed
/20 of the highest frequency, or harmonic of concern, not just the primary
frequency of interest. If many high-bandwidth components are used,
multiple ground stitch locations are typically required. If the unit is a slow
edge rate device, connection to chassis ground may be minimized, or
distance spacing between ground locations may be increased. This
separation should be related not to the clock rate but to the highest
harmonic frequency of the circuit.
For example, /20 of a 64-MHz oscillator is 9.2 in. (23.4 cm). If the straight-
line distance between two ground stitch connections to a 0V-reference in
either the x- or y-axis is greater than 9.2 in. (23.4 cm), a potential efficient
RF loop exists. This loop could be the source of RF energy propagation,
which could cause noncompliance with international EMI emission limits.
Unless other design techniques are implemented, suppression of RF
currents caused by poor loop control is not possible and containment
measures, such as sheet metal must be implemented. Sheet metal is an
expensive cost that might not work for RF containment. Aspect ratio is
illustrated in Fig. 2.27, where the distance spacing between ground
locations is less than /20 in all directions.
This chapter deals with the basics of EMC related to printed circuit boards.
Implementation of layout concepts has not yet been discussed. Since the
subject of aspect ratio using a multiground methodology has been covered,
we now consider a design technique for use on a PCB with multipoint
grounding.
With many chassis ground connections, how does one incorporate a cost-
effective technique for making numerous ground points without use of
screws for mechanical securement? Alternative techniques and material
are available, with an overall cost less than the screw-secured connection,
once labor costs are factored in. An example of a creative technique for
providing numerous ground stitch locations, using only several screws for
mechanical securement, is shown in Fig. 2.28. The material illustrated is an
EMI-conducted cloth gasket on a neoprene sponge core. Other material
may be used, such as beryllium copper fingers. Many manufacturers
provide conductive material in any size, shape, and configuration
imaginable. This technique has been applied numerous times with extreme
success.
Once all ground connections are determined and the PCB is installed into
the enclosure, screws are provided to mechanically secure the PCB to the
chassis. The PCB presses down on the conductive gasket. The gasket will
spread out on both the top and bottom side of the mylar sheet, thus
assuring a low-impedance bond connection between PCB and chassis. If a
different PCB layout is required with this same chassis, but component
placement and ground point requirements become different, hole locations
in the mylar sheet can be redefined, thus preventing a redesign of the
enclosure. This is where cost savings become significant. It is cheaper to
punch holes in a mylar sheet than to retool a sheet metal chassis or re-
layout a PCB.
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Personal account | University of Southern Queensland
Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
ASSIGNMENT
2.6: RADIAL MIGRATION
2.7: COMMON-MODE AND
DIFFERENTIAL-MODE
2.12 IMAGE PLANES
CURRENTS
2.8: RF CURRENT DENSITY
DISTRIBUTION An image plane is a layer of copper or similar conductive internal to a PCB.
2.9: GROUNDING
METHODOLOGIES This layer may be identified as a voltage plane, ground plane, or 0V-
2.10: GROUND AND SIGNAL
LOOPS (EXCLUDING EDDY reference plane physically adjacent to a circuit or signal routing layer.
CURRENTS)
2.11: ASPECT RATIO
Image planes provide a low-impedance path for RF currents to return to
DISTANCE BETWEEN
GROUND CONNECTIONS
their source (flux cancellation or minimization). A complete return path
2.12: IMAGE PLANES must be present for the circuit to function. This return path is for both signal
2.13: SLOTS WITHIN AN
IMAGE PLANE and RF current. With an optimal RF return path, the development of EMI is
2.14: FUNCTIONAL
PARTITIONING reduced. The term "image plane" was popularized by Ref. [8] and is now
2.15: CRITICAL
FREQUENCIES (/20)
used as industry standard terminology.
2.16: LOGIC FAMILIES
REFERENCES RF currents must return to their source one way or another. This path may
be a mirror image of its original trace route or through another trace located
in the near vicinity (crosstalk). This return path may be a power plane,
ground plane, or free space. RF currents will capacitively or inductively
couple themselves to any transmission line that has a lower impedance
than the previously defined path.
For image planes to be effective, no traces can be located within this solid
planar structure. Exceptions are possible when a moat, isolation, or
absence of copper occurs. If a signal route, or a power trace (e.g., +12 V),
is located within a solid +5V plane, this +5V plane becomes fragmented.
Provisions have now been made for a ground or signal return loop to be
present for signal traces routed on the adjacent layer across this violation.
This loop area occurs because RF return currents cannot seek a straight-
line path back to its source. Split planes can no longer function as a low-
impedance, solid return path for RF currents to complete the trip in an
efficient manner for optimal flux cancellation.
Figure 2.32 illustrates the effect of loop areas when vias are incorporated
within image planes. Excessive through-hole pin clearance, or poor pin
assignment strategies during connector assignment, can lead to an
excessive loop area for return currents, exacerbating the development of
common-mode RF energy. When signal and return traces are separated,
the loop area can become significant, radiating RF energy. It is important
for the design engineer to know and understand where the return signal
path is and to guarantee that the loop area defined is as small as possible.
Figure 2.32: Loop areas with vias in the image plane.
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Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
ASSIGNMENT
2.6: RADIAL MIGRATION
2.7: COMMON-MODE AND
DIFFERENTIAL-MODE
2.13 SLOTS WITHIN AN IMAGE PLANE
CURRENTS
2.8: RF CURRENT DENSITY
DISTRIBUTION A concern associated with image plane discontinuity is use of through-hole
2.9: GROUNDING
METHODOLOGIES
components. An excessive number of through-holes within a power or
2.10: GROUND AND SIGNAL
LOOPS (EXCLUDING EDDY
ground plane structure creates a situation identified as the Swiss cheese
CURRENTS)
2.11: ASPECT RATIO
syndrome [10]. The copper between through-hole pins is reduced because
DISTANCE BETWEEN many holes overlap each other, leaving large areas of discontinuity. This
GROUND CONNECTIONS
2.12: IMAGE PLANES occurs because during the manufacturing process, oversized through-
2.13: SLOTS WITHIN AN
IMAGE PLANE
holes are drilled. Oversized holes are drilled because they reduce the cost
2.14: FUNCTIONAL of manufacturing by allowing a greater tolerance for the manufacturer of
PARTITIONING
2.15: CRITICAL the bare board assembly. An example of oversized drilled holes is provided
FREQUENCIES (/20)
2.16: LOGIC FAMILIES
in Fig. 2.33. The return current flows in the image plane adjacent to the
REFERENCES signal route. The RF return current cannot mirror image to the signal trace
on the adjacent layer due to this discontinuity. As seen in the figure, return
currents in the ground plane must travel around the through-hole slots.
This extra RF return path length creates a loop antenna, developing a
magnetic field between the signal trace and the return path. Additional
inductance in the return path also means less flux cancellation. For
through-hole components that have copper between pins (nonoversized
holes), reduction of signal and return current of magnetic flux is achieved.
This flux reduction is due to less inductance in the signal return path owing
to the solid image plane.
Generally, slots in a PCB with oversized or overlapping holes will not cause
RF problems for the majority of signal traces routed between through-hole
device leads. This observation is valid for traces that do not carry high
levels of RF energy or static level signals, not clock or period traces. For
high-speed, high-threat signals, alternative methods of routing traces
between through-hole component vias must be devised. For applications in
which a trace must traverse across a slot or partition within the PCB
assembly, Fig. 2.34 provides a simple design technique. This design
technique guarantees that RF current has the ability to achieve a direct-line
return path back to the source.
A continuous image plane is still the best choice when splits or moats are
provided. This is especially true when both analog and digital circuitry is
provided. Attempting to isolate analog and digital ground planes sometimes
provides enhanced performance by not allowing RF energy from one
functional area to corrupt other functional areas. Problems develop when a
trace must cross this moat or there is an absence of copper area. The
trace will see a large impedance discontinuity. If several similar signals
cross the same boundary and simultaneous switching occurs, a significant
amount of common-mode energy may be developed, especially when all
signals attempt to switch logic state at the same time, in the same
direction: logic HIGH or LOW. If several bypass capacitors are provided
across the boundary violation to eliminate the problem, as shown in Fig.
2.34, a continuous RF return path should have been provided to begin
with.
One concern relating to image planes centers on the issue of skin effect.
Skin effect refers to high-frequency current flow that resides in the first skin
depth of the material. Current does not, and cannot, significantly flow in the
center of traces, wires, or planes, and it is predominantly observed on the
outer surface of conductive media. Different materials have different skin
depth values. The skin depth of copper, for example, is extremely shallow
above 30 MHz. Typically, this is observed, for example, as 0.0000066 in.
(0.0017 mm) at 100 MHz. RF current therefore cannot penetrate a 1-oz.
copper layer that is beyond 0.0014 in. (0.036 mm) thick. As a result, both
common-mode and differential-mode currents flow only on the top (skin)
layer of the plane. No significant current flows internal to the image plane
or on its bottom. Placing a second image plane adjacent to a primary
reference plane would not provide additional EMI reduction. If the second
reference plane is at voltage potential (the primary plane at ground
potential), a decoupling capacitor is created between these two planes.
These two planes can now be used for both decoupling and imaging [1].
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Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
ASSIGNMENT
2.6: RADIAL MIGRATION
2.7: COMMON-MODE AND
DIFFERENTIAL-MODE
2.14 FUNCTIONAL PARTITIONING
CURRENTS
2.8: RF CURRENT DENSITY
DISTRIBUTION
Proper placement of components for optimal functionality and EMC
2.9: GROUNDING
METHODOLOGIES
suppression is important in any layout. Most designs incorporate functional
2.10: GROUND AND SIGNAL
LOOPS (EXCLUDING EDDY
subsections or areas by logical function. Grouping functional areas
CURRENTS) minimizes signal trace length, routing, and creation of antennas. Proper
2.11: ASPECT RATIO
DISTANCE BETWEEN component placement also makes trace routing easier, thus enhancing
GROUND CONNECTIONS
2.12: IMAGE PLANES signal integrity. Figure 2.35 illustrates functional grouping of subsections,
2.13: SLOTS WITHIN AN
IMAGE PLANE
or areas, on a complex motherboard design.
2.14: FUNCTIONAL
PARTITIONING
2.15: CRITICAL
FREQUENCIES (/20)
2.16: LOGIC FAMILIES
REFERENCES
Proper partitioning also allows for optimal signal functionality and ease of
routing traces while minimizing overall trace lengths. Partitioning permits
smaller RF loop areas to exist, optimizing signal quality. The design
engineer must specify to the PCB designer which components are
associated with each functional subsection. The information provided by
component manufacturers and design engineers can be used to optimize
component placement prior to routing any traces.
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Personal account | University of Southern Queensland
Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
ASSIGNMENT
2.6: RADIAL MIGRATION
2.7: COMMON-MODE AND
2.15 CRITICAL FREQUENCIES (/20)
DIFFERENTIAL-MODE
CURRENTS
2.8: RF CURRENT DENSITY
DISTRIBUTION
Throughout this book, reference is made to critical frequencies or high-
2.9: GROUNDING
METHODOLOGIES
threat clock and periodic signal traces that have a wavelength greater than
2.10: GROUND AND SIGNAL
LOOPS (EXCLUDING EDDY
/20. The following equations show how to calculate the wavelength of a
CURRENTS)
2.11: ASPECT RATIO signal and the corresponding critical frequency. A summary of
DISTANCE BETWEEN
GROUND CONNECTIONS
miscellaneous frequencies and their respective wavelength distance is
2.12: IMAGE PLANES presented in Table 2.3 based on these equations.
2.13: SLOTS WITHIN AN
IMAGE PLANE
2.14: FUNCTIONAL
PARTITIONING
Table 2.3: /20 Wavelength at Various Frequencies
2.15: CRITICAL
FREQUENCIES (/20)
Open table as spreadsheet
2.16: LOGIC FAMILIES
REFERENCES Frequency Distance /20 Wavelength Distance
(2.5)
Get MathML
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Personal account | University of Southern Queensland
Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
ASSIGNMENT
2.6: RADIAL MIGRATION
2.7: COMMON-MODE AND
DIFFERENTIAL-MODE
2.16 LOGIC FAMILIES
CURRENTS
2.8: RF CURRENT DENSITY
DISTRIBUTION When selecting a component for a particular application, design engineers
2.9: GROUNDING
METHODOLOGIES are generally interested only in functionality, operating speed, and
2.10: GROUND AND SIGNAL
LOOPS (EXCLUDING EDDY propagation delay of the internal logic gates as published by the
CURRENTS)
2.11: ASPECT RATIO
manufacturer. Consideration of electromagnetic effects is seldom
DISTANCE BETWEEN
GROUND CONNECTIONS
considered.
2.12: IMAGE PLANES
2.13: SLOTS WITHIN AN
IMAGE PLANE
As components become faster (decrease in internal propagation delay), an
2.14: FUNCTIONAL
PARTITIONING
increase in RF current, crosstalk, and ringing will occur, based on the
2.15: CRITICAL inverse relationship between speed and EMI. A device is generally chosen
FREQUENCIES (/20)
2.16: LOGIC FAMILIES
based on the propagation time from input to output, along with the setup
2.16.1: Edge Rate
Transitions
time of the input signal. Almost all components have internal logic that
REFERENCES operate at a faster edge rate than the propagation delay required for
functionality. Consequently, slower logic families (internal gates) are
preferred. Figure 2.37 illustrates the relationship between the internal
switching speed of a basic inverter gate compared to propagation delay.
Various logic families are available with different design features. These
features vary between CMOS, TTL, and ECL, to name a few. Some of
these features include input power consumption, package outline, speed-
power combinations, voltage swing level, and edge transition rates. Certain
logic devices are available with clock skew circuitry to control the internal
edge transitions of the internal logic gates, while maintaining accurate
propagation delay through the component.
Crossover currents are developed when digital devices change logic state.
For a finite time period, the voltage to the component is shorted to ground
when the output transistors switch. This short is usually in the low
picosecond range and is generally too fast to be measured with most
instrumentation. This spike is sometimes observed on a spectrum analyzer
as a walking transition that is difficult to trigger on.
The frequently heard statement, "Use the slowest logic family possible,"
goes back to the component manufacturers' failure to specify or publish
this minimum edge rate parameter in their data books. The edge rates of
digital components are the source of most RF energy developed within a
PCB. Table 2.4 illustrates published, not actual edge rate transition levels.
Table 2.4: Sample Chart of Logic Families, Illustrating Spectral
Bandwidth of RF Energy
Open table as spreadsheet
Typical
Principal Frequencies
Published Observed as EMI
Rise/Fall Harmonic
th
Time Content f = 1/ (10 harmonic)
Logic [a] [a]
(Approx.) t /t ( t ) f = 10 f
Family r f r max
74L xxx 3135 ns 10 MHz 100 MHz
74C xxx 2560 ns 13 MHz 130 MHz
74HC xxx 1315 ns 24 MHz 240 MHz
74 xxx 1012 ns 32 MHz 320 MHz
(flip-flop) 1522 ns 21 MHz 210 MHz
74LS xxx 9.5ns 34 MHz 340 MHz
(flip-flop) 1315 ns 24 MHz 240 MHz
74H xxx 46 ns 80 MHz 800 MHz
74S xxx 34 ns 106 MHz 1.1 GHz
74HCT 515 ns 64 MHz 640 MHz
xxx
74ALS 210 ns 160 MHz 1.6 GHz
xxx
74ACT 25 ns 160 MHz 1.6 GHz
xxx
74F xxx 1.51.6 ns 212 MHz 2.1 GHz
ECL 10K 1.5 ns 212 MHz 2.1 GHz
ECL 100K 0.75 ns 424 MHz 4.2 GHz
BTL 1.0 ns
[a] 318 MHz 3.2 GHz
LVDS 0.3 ns
[a] 1.1 GHz 11 GHz
GaAs 0.3 ns
[a] 1.1 GHz 11 GHz
GTL+ 0.3 ns
[a] 1.1 GHz 11 GHz
(Pentium)
[a]
These are minimum edge rate values.
For maximum edge rate transition time, multiply the typical value by 1.2.
For minimum edge rate transition time, multiply the typical value by 0.6.
This calculation will get one in the ballpark for design purposes related to
actual edge rate values. The vendor of the device should be consulted for
the real edge rate transition value, if not specified within the data sheet.
The vendors themselves may not know the actual value.
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Copyright 1999-2008 Books24x7, Inc. - Feedback | Privacy Policy (updated 03/2005)
Personal account | University of Southern Queensland
Table of Contents
Chapter 2 - Printed Circuit Board Basics
Chapter 2
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
2.1: HIDDEN RF
by Mark I. Montrose
CHARACTERISTICS OF
PASSIVE COMPONENTS IEEE Press 2000
2.2: HOW AND WHY RF
ENERGY IS DEVELOPED
WITHIN THE PCB Recommend this title?
2.3: MAGNETIC FLUX AND
CANCELLATION
REQUIREMENTS
2.4: ROUTING TOPOLOGY
CONFIGURATIONS
2.5: LAYER STACKUP
ASSIGNMENT
2.6: RADIAL MIGRATION
2.7: COMMON-MODE AND
REFERENCES
DIFFERENTIAL-MODE
CURRENTS
2.8: RF CURRENT DENSITY [1] Montrose, M. 1999. EMC and the Printed Circuit Board Design
DISTRIBUTION
2.9: GROUNDING
Design, Theory and Layout Made Simple. Piscataway, NJ: IEEE Press.
METHODOLOGIES
2.10: GROUND AND SIGNAL
LOOPS (EXCLUDING EDDY [2] Gerke, D., and W. Kimmel. 1994. "The Designer's Guide to
CURRENTS)
2.11: ASPECT RATIO Electromagnetic Compatibility." EDN (January 20).
DISTANCE BETWEEN
GROUND CONNECTIONS
2.12: IMAGE PLANES
2.13: SLOTS WITHIN AN
[3] Whitaker, J. 1996. The Electronics Handbook. Boca Raton, FL: CRC
IMAGE PLANE Press.
2.14: FUNCTIONAL
PARTITIONING
2.15: CRITICAL
FREQUENCIES (/20)
[4] Radu, S., et al. 1998. "An Impact of Layer Stack-up on EMI."
2.16: LOGIC FAMILIES Proceedings of the IEEE International Symposium on Electromagnetic
REFERENCES
Compatibility, pp. 828833.
nd
[6] Ott, H. 1988. Noise Reduction Techniques in Electronic Systems. 2
ed. New York: John Wiley & Sons.
[7] Johnson, H. W., and M. Graham. 1993. High Speed Digital Design.
Englewood Cliffs, NJ: Prentice Hall.
[9] Hsu, T. 1991. "The Validity of Using Image Plane Theory to Predict
Printed Circuit Board Radiation." Proceedings of the IEEE International
Symposium on Electromagnetic Compatibility, pp. 5860.
[12] Woody, J.A., and C.A. Pauldi. 1980. "Modeling Techniques for
Discrete Passive Components to Include Parasitic Effects in EMC and
Design." Proceedings of the IEEE International Symposium on
Electromagnetic Compatibility, pp. 3945.
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Table of Contents
Chapter 3 - Bypassing and Decoupling
Chapter 3
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
3.1: REVIEW OF RESONANCE
by Mark I. Montrose
3.2: PHYSICAL
CHARACTERISTICS IEEE Press 2000
3.3: CAPACITORS IN
PARALLEL
3.4: POWER AND GROUND Recommend this title?
PLANES
3.5: PLACEMENT
3.6: HOW TO PROPERLY
SELECT A CAPACITOR
REFERENCES
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Table of Contents
Chapter 3 - Bypassing and Decoupling
Chapter 3
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
3.1: REVIEW OF by Mark I. Montrose
RESONANCE
3.1.1: Series Resonance IEEE Press 2000
3.1.2: Parallel Resonance
3.1.3: Parallel C-Series RL
Resonance (Antiresonant Recommend this title?
Circuit)
3.2: PHYSICAL
CHARACTERISTICS
3.3: CAPACITORS IN
PARALLEL
3.4: POWER AND GROUND
PLANES
3.5: PLACEMENT
3.6: HOW TO PROPERLY
SELECT A CAPACITOR 3.1 REVIEW OF RESONANCE
REFERENCES
Series resonance
Parallel resonance
Impedance is at a minimum.
Current is at a maximum.
Impedance is at a maximum.
Current is at a minimum.
If the resistance value is too high, the equivalent series resistance of the
component will exceed the inductance values at the resonant frequency
point. If the resistance is just right, inductive impedance is equal to the
resistance, again at the resonant frequency. Resonance is the condition
under which the inductive impedance is equal to the capacitive impedance.
At resonance, the capacitor and inductor trade the same stored energy on
alternate half cycles. When the capacitor discharges, the inductor charges,
and vice versa. At the antiresonant frequency, the tank circuit presents
high impedance to the primary circuit current, even though the current
within the tank is high. Power is dissipated only in the resistive portion of
the network.
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Personal account | University of Southern Queensland
Table of Contents
Chapter 3 - Bypassing and Decoupling
Chapter 3
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
3.1: REVIEW OF RESONANCE
by Mark I. Montrose
3.2: PHYSICAL
CHARACTERISTICS IEEE Press 2000
3.2.1: Impedance
3.2.2: Capacitor Types
Recommend this title?
3.2.3: Energy Storage
3.2.4: Resonance
3.3: CAPACITORS IN
PARALLEL
3.4: POWER AND GROUND
PLANES
3.5: PLACEMENT
3.6: HOW TO PROPERLY
SELECT A CAPACITOR
3.2 PHYSICAL CHARACTERISTICS
REFERENCES
3.2.1 Impedance
The equivalent circuit of a capacitor was shown in Fig. 3.1. The actual
impedance value of this capacitor is
(3.1)
Get MathML
where Z = impedance ()
R = equivalent series resistanceESR ()
s
f = frequency (Hz)
L = equivalent series inductanceESL (H)
C = capacitance (F)
(3.2)
Get MathML
In reality, the impedance equation (Eq. 3.1) reflects hidden parasitics that
are present when we take into account ESL and ESR.
Examining Eq. (3.1), we have a variation of the same equation with ESR
and ESL substituted in, shown in Eq. (3.3).
(3.3)
Get MathML
where X = 2f(ESL)
ESL
Get MathML
In order for an ideal capacitor to exist, the device needs to have a high
capacitance, C, and a low inductance, L, such that the overall impedance
will not increase at higher frequencies. For this reason, power and ground
plane structures are optimal in providing low-impedance decoupling within
a PCB over discrete components.
(3.4)
Get MathML
t = switching time
Note that for V, EMI requirements are usually more demanding than
component supply needs. The I requirement is usually unknown or not
provided by the device manufacturer. The value of t is usually given as
"typical" or "maximum," but rarely as "minimum," which is the primary
variable of interest.
Output capacitive load: Capacitive load charging current that the driver
must send to a load.
3.2.4 Resonance
When selecting bypass and decoupling capacitors, storage capacity and
discharge frequency must be calculated based on the logic family and
clock speed of the circuit (self-resonant frequency). One must select a
capacitance value based on the impedance that the capacitor presents to
the circuit. A capacitor remains capacitive up to its self-resonant frequency.
Above self-resonance, the capacitor starts to appear as an inductor due to
lead length and trace inductance. Inductance minimizes the ability of the
capacitor to decouple or remove RF energy that exists between power and
ground. Table 3.2 illustrates the self-resonant frequency for two types of
ceramic capacitors, one with standard 0.25 in. leads (radial or axial) and
the other surface mount. The self-resonant frequency of surface mount
(SMT) capacitors is always higher, although interconnect inductance may
obviate this benefit. Interconnect inductance includes routed traces and the
bond wires internal to a component package. Depending on the type of
product being designed, as well as on the frequency of operation, a change
of inductance in the picohenry range may be too much to tolerate.
Table 3.2: Approximate Self-Resonant Frequency of Various
Capacitors (lead-length dependent)
Open table as spreadsheet
[b]
For surface mount, L = 1 nH.
When selecting a capacitor, one should consider not only the self-resonant
frequency but the dielectric material as well. The most commonly used
material is Z5U (barium titanate ceramic). This material has a high
dielectric constant that allows small capacitors to have large capacitance
values with self-resonant frequencies from 1 MHz to 20 MHz, depending
on design and construction. Above self-resonance, performance of Z5U
decreases as the loss factor of the dielectric becomes dominant, which
limits its usefulness to approximately 50 MHz.
A problem observed when Z5U and NPO are provided in parallel is that the
higher dielectric material, Z5U, can damp the resonance of the more
frequency-stable, low-dielectric constant material, NPO. For EMI problems
below 50 MHz, it is better to use only a good, low-inductance Z5U (or
equivalent) capacitor. This is because Z5U combines excellent low-
frequency decoupling with reduction in radiated emissions.
Through-hole capacitors are nothing more than surface mount devices with
leads attached. A typical leaded capacitor has on the average
approximately 2.5 nH of inductance for every 0.10 in. of lead length.
Surface mount capacitors average 1 nH total lead-length inductance. This
inductance is based on typical trace dimensions and will vary with width,
thickness, and length.
An inductor does not change its resonant response like a capacitor;
instead, the magnitude of the device's impedance will change as frequency
changes. Parasitic capacitance between the windings of the inductor,
however, can cause a parallel resonance to occur, which may alter the
desired response. The higher the frequency of the circuit, the greater the
magnitude of the impedance changes. RF current traveling through this
impedance causes a RF voltage potential difference between input and
output. Consequently, RF current is developed within the device, described
by Ohm's law, V = I * Z (see Chapter 2). An important design concern
rf rf
when selecting and implementing capacitors for decoupling deals with lead
inductance. SMT capacitors perform better at higher frequencies than
radial or axial capacitors because of lower internal lead inductance. Table
3.3 shows the magnitude of impedance of a 15 nH inductor versus
frequency (Z = 2fL).
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Table of Contents
Chapter 3 - Bypassing and Decoupling
Chapter 3
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
3.1: REVIEW OF RESONANCE
by Mark I. Montrose
3.2: PHYSICAL
CHARACTERISTICS IEEE Press 2000
3.3: CAPACITORS IN
PARALLEL
Recommend this title?
3.4: POWER AND GROUND
PLANES
3.5: PLACEMENT
3.6: HOW TO PROPERLY
SELECT A CAPACITOR
REFERENCES
Figure 3.8 shows a plot of two bypass capacitors, 0.01 F and 100 pF,
both individually and in parallel. The 0.01 F capacitor is self-resonant at
14.85 MHz. The 100 pF capacitor has its self-resonant frequency at 148.5
MHz. At 110 MHz, there is a large increase in the magnitude of impedance
owing to this parallel combination. The 0.01 F capacitor has already gone
inductive, while the 100 pF capacitor is still capacitive. We now have both L
and C in resonance at 110 MHz, causing an antiresonant effect. An
antiresonant frequency is exactly what we do not want in a PCB, if
compliance to EMI requirements is required. At this particular frequency,
any harmonic of a clock transition will be observed as a powerful,
transmitting signal. For this example, the third harmonics of a 36 MHz
oscillator is 108 MHz.
Figure 3.8: Resonant effect from two capacitors in parallel. (Source: Ref
[2]. Reprinted by permissionIEEE Press.)
Figure 3.8 shows that at 500 MHz, the impedances of the individual
capacitors are virtually identical. The parallel impedance is only 6 dB lower.
This 6 dB improvement is only valid over a limited frequency range from
about 120 to 160 MHz.
To optimize the effects of parallel bypassing and to allow use of only one
capacitor, reduction in lead inductance is required. A finite amount of
inductance will always exist when installing the capacitor on the board.
Note that lead inductance must also include the inductance value and
physical length of the via that connects the capacitor to the planes. The
shorter the lead length, the greater the performance. In addition, some
manufacturers provide capacitors with significantly reduced ESL internal to
the capacitor package.
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Table of Contents
Chapter 3 - Bypassing and Decoupling
Chapter 3
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
3.1: REVIEW OF RESONANCE
by Mark I. Montrose
3.2: PHYSICAL
CHARACTERISTICS IEEE Press 2000
3.3: CAPACITORS IN
PARALLEL
3.4: POWER AND Recommend this title?
GROUND PLANES
3.4.1: Calculating Power
and Ground Plane
Capacitance
3.4.2: Combined Effects of
Planar and Discrete
Capacitors
3.4.3: Buried Capacitance
3.5: PLACEMENT
3.6: HOW TO PROPERLY
3.4 POWER AND GROUND PLANES
SELECT A CAPACITOR
REFERENCES
A benefit of using multilayer assemblies is the ability to have a power and
ground plane distribution network to enhance the overall performance of
system operation. This performance exists by virtue of having a low-
impedance path between the power source and component. A low-
impedance path allows for a minimal amount of voltage drop to be present
for the overall assembly, power supply to components, and component to
component. If an imbalance exists within the power distribution network,
common-mode RF energy will be developed.
The physical relationship of these two planes creates one large capacitor
two parallel plates separated by a dielectric. This capacitor generally
provides adequate decoupling for most low-speed (slower edge rate)
designs; however, additional signal or plane layers add cost to the overall
assembly. If components have signal edge transitions (t or t ) slower than
r f
10 ns (e.g., standard TTL logic), use of high-performance, high self-
resonant frequency discrete decoupling capacitors may not be required.
Bulk capacitors are still needed, however, to maintain proper voltage levels
to ensure proper operation of the design.
(3.5)
Get MathML
(3.6)
Get MathML
In the past, slower speed logic devices fell well below the spectrum of the
self-resonant frequency of the PCB's power and ground plane structure.
The logic devices used in newer, high-technology designs easily approach
or exceed this critical resonant frequency. When both the impedance of the
power/ground planes and individual decoupling capacitors approach the
same resonant frequency, severe performance deterioration can occur.
This degraded high-frequency impedance will result in EMI. Thus, the
assembled PCB becomes an unintentional transmitter. The PCB is not
really the transmitter; rather, the highly repetitive circuits or clocks are the
cause of RF energy present that radiates or couples to unintentional
circuits. Because decoupling will not solve this type of problem (owing to
the resonance of the decoupling effect), system-level containment
measures will be required.
[1]
Buried capacitance is a registered trademark of HADCO Corporation
(which purchased Zycon Corporation, developers of this technology).
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Table of Contents
Chapter 3 - Bypassing and Decoupling
Chapter 3
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
3.1: REVIEW OF RESONANCE
by Mark I. Montrose
3.2: PHYSICAL
CHARACTERISTICS IEEE Press 2000
3.3: CAPACITORS IN
PARALLEL
3.4: POWER AND GROUND Recommend this title?
PLANES
3.5: PLACEMENT
3.5.1: Power Planes
3.5.2: Equivalent Circuit
Model of a PCB
3.5.3: Decoupling
Capacitors
3.5.4: Single- and Double-
Sided Assemblies
3.5.5: Mounting Pads
3.5.6: Microvias
3.6: HOW TO PROPERLY
SELECT A CAPACITOR
REFERENCES
3.5 PLACEMENT
Power planes that are located next to ground planes provide for enhanced
flux cancellation in addition to decoupling RF currents created from power
fluctuations owing to components injecting noise into the network.
Components switching logic states cause a current surge during the
transition. This current surge places a strain on the power distribution
network. An image plane is a solid copper plane at voltage or ground
potential located adjacent to a signal routing plane. RF currents present will
mirror image themselves in this adjacent solid reference plane. This solid
reference plane must not be isolated from the power distribution network
[5]. To remove common-mode RF currents created within a PCB, all
routing (signal) layers must be physically adjacent to an image plane. (For
a detailed discussion of image planes, see Chapter 2.)
Figure 3.11 [1] makes it clear that EMI is a function of loop geometry and
frequency. Hence, the smallest closed-loop area is desired. We acquire
this small area by placing a local decoupling capacitor, C , for current
d
storage adjacent to the power pins of the component. It is mandatory that
the decoupling loop impedance be much lower than the rest of the power
distribution system. This low impedance will cause high-frequency RF
energy developed by both traces and components to remain almost
entirely within this small loop area. Consequently, lower EMI emissions are
developed.
If the impedance of the decoupling loop is smaller than the rest of the
system, some fraction of the high-frequency RF energy will transfer, or
couple, to the larger loop formed by the power distribution system. With
this situation, RF currents are injected in the larger loop structure, and
hence, higher EMI emissions are the result. This situation is illustrated in
Fig. 3.12 [8].
To summarize,
Poor planning during PCB layout and component selection may require
use of Micro-Q. As yet, no equivalent retrofit for SMT components is
available.
Placement of 1-nF (1000 pF) capacitors (capacitors with a very high self-
resonant frequency) on a 1-in. (2.54 cm) grid may provide additional
protection from RF currents for both signal traces and power planes,
especially if a high-density PCB stackup is provided [6]. A lumped model
analysis of the PCB shows that the capacitors will still function as desired,
regardless of where the device is actually placed for overall decoupling
performance. Depending on the resonant structure of the board, values of
the capacitors placed in the grid may be as small as 3040 pF [7, 8].
VLSI and high-speed components (F, ACT, BCT, CMOS, ECL, etc.) may
require additional use of parallel decoupling. As slew rates of components
become faster, a greater spectral distribution of RF energy is developed.
Parallel capacitors generally provide optimal bypassing of power plane
noise. Multiple paired sets of capacitors are placed between the power and
ground pins of VLSI components located around all four sides. These high-
frequency decoupling capacitors are typically rated 0.1 F in parallel with
0.001 F for 50 MHz systems. Higher clock frequencies generally require
use of a parallel combination of 0.01 F and 100 pF components. (The
uses of parallel capacitors were discussed in Section 3.3.)
For the first technique, running a trace from capacitor to a component, and
then connecting the composite configuration to the power and ground
planes by a vias, is a poor implementation technique, even if the trace is
physically wide, regardless of location. The reason this is a poor
implementation technique deals with loop area and trace inductance. The
loop area of the current path between the circuit to one of the planes,
through a via, plus the trace distance through the capacitor back through
another trace and via to the other plane, is physically much larger than the
loop area dimension that is commonly assumed. Total inductance of the
loop area is also very large.
Why do we care about the loop area? Because the bigger the loop, the
more flux that is observed as EMI owing to the higher the inductance. With
inductance, there exists a lower self-resonant frequency among other
items. These other items make the antiresonant frequency of the capacitor
higher, thus lowering the bandwidth of performance. With a low-bandwidth
performance, use of more discrete capacitors to achieve the same bypass
effectiveness is required. The goal is to create a low-impedance network
over a large spectral area for the power distribution system. Therefore,
component power pins must be routed directly to the power and ground
planes. In addition, the decoupling capacitor must be connected directly to
the planes to minimize the current loop area and trace/via inductance [8].
Using analysis tools, we see that calculated inductance for the following
are on the order of
For a +5V/+3.3V system, planes can be located close to the outer side of
the PCB and decoupled from the side closest to the pair. Remember that a
decoupling capacitor also provides a path for return current to travel
through the board within the plane. Driving a rising-edge transition means
that return current has to get back to the power pin of the driver. Another
reason for locating traces between a pair of ground planes is that ground
vias or bypass capacitors are not required to provide a path for RF return
currents. To review, bypassing allows energy to be transferred from one
location to another at the same potential, while decoupling is between
planes of different potential. Optimal placement of capacitors minimizes the
RF return path. The important item to remember is not the specific numeric
value of capacitance, or total inductance, but the magnitude of impedance,
which must be extremely low for optimal performance.
3.5.6 Microvias
A technology known as microvias permits use of vias embedded within
component mounting pads. These microvias minimize the amount of solder
absorbed by the via during a wave or IR soldering process. Additional
costs may be incurred from use of this technology, which is becoming
common in extremely high-density, high-performance designs. One
advantage of using microvias is to minimize trace inductance between the
mounting pad and a remote via. In addition, less real estate is required for
incorporation of the microvia, thus allowing greater routing densities to
exist. If more traces can be routed within internal layers, fewer routing
planes may be required. The use of fewer planes may be more cost
effective then implementing the cost of microvia technology.
[2]
Micro-Q is a trademark of Circuit Components Inc. (formerly Rogers
Corporation).
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Table of Contents
Chapter 3 - Bypassing and Decoupling
Chapter 3
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
3.1: REVIEW OF RESONANCE
by Mark I. Montrose
3.2: PHYSICAL
CHARACTERISTICS IEEE Press 2000
3.3: CAPACITORS IN
PARALLEL
3.4: POWER AND GROUND Recommend this title?
PLANES
3.5: PLACEMENT
3.6: HOW TO PROPERLY
SELECT A CAPACITOR
3.6.1: Bypass and
Decoupling
3.6.2: Capacitive Effects on
Signal Traces
3.6.3: Bulk
REFERENCES
3.6 HOW TO PROPERLY SELECT A CAPACITOR
For historical purposes, in 1965, the United States Air Force discovered
that if it decoupled airborne electronic equipment, the plane would be able
to communicate by radio. Use of 0.1 F electrolytic capacitors was
incorporated with long wire leads (large ESL and ESR values). The
operating frequency of the equipment was 200 kHz. Consequently, if 0.1
F is acceptable for 200 kHz systems, then it must be acceptable for 200
MHz products, which is totally wrong! The key to optimal performance is to
calculate the capacitor for functionality reasons. A capacitor should not be
used based on historical usage without understanding how and why a
particular value was chosen.
It is alleged that designers choose decade values of capacitor (0.1, 0.01,
0.001 F, 100 pF) units that exclusively have zeros (0's) and ones (1's),
because "digital" engineers think binary.
(3.7)
Get MathML
The minimum capacitive value of the bypass capacitor required for optimal
performance is determined by the maximum amount of voltage drop
allowable across the capacitor as a result of a transient current surge. This
voltage drop is exacerbated when a component operates under maximum
capacitive load. An appropriate value for bypassing can be easily
calculated by
(3.8)
Get MathML
Get MathML
A problem with using these equations as written lies with lead inductance
in the decoupling loop. Additional voltage spiking occurs across the
inductance. For any magnitude of noise spike, the maximum amount of
series inductance is described by
(3.9)
Get MathML
Get MathML
This means that total lead and series inductance cannot exceed 10 nH.
Referring back to Fig. 3.14, we see that total ESL of the circuit must be
kept below 10 nH; this is a challenging task when traces are required to be
routed between component and capacitor. One should not forget to include
the inductance associated with the bond wires internal to a component
package.
Figure 3.19 shows the change in the slew rate (clock edge) of the desired
signal. Although the transition points remain unchanged, the time period, t ,
r
is different. This elongation, or slowing of the signal edge, is a result of the
capacitor charging and discharging. The change in transition time is
described by the equations and illustration of Fig. 3.20. Note that a
Thevenin equivalent circuit is shown, without the load. The source voltage,
V , and series impedance, R , are internal to the driver or clock generation
b s
circuit. The capacitive effect on the trace is a result of this capacitor being
located in the circuit. To determine the time rate of change of the capacitor
of Fig. 3.19, the equations in Fig. 3.20 are used.
The value used to alter the shape of a signal can be calculated in two
ways. Although capacitance is calculated for optimal performance at a
particular resonant frequency, use and implementation depend on
installation, lead-length inductance, trace length inductance, and other
parasitic parameters that may change the resonant frequency of the
capacitor. The installed value of capacitive reactance is the item of interest.
Calculating the value of capacitance will be in the ballpark and is generally
accurate enough for actual implementation.
(3.10)
Get MathML
Method 1
Equation (3.11) is used to determine the maximum capacitance value for
wave shaping, based on knowing the edge rate of the clock signal.
(3.11)
Get MathML
C in picofarads if t is in picoseconds
r
The capacitor must be chosen so that the edge transition time (t = 3.3R *
r
C) equals an acceptable rise or fall time for proper functionality of the
signal; otherwise baseline shift may occur. Baseline shift refers to the
steady-state voltage level that is identified as logic LOW or logic HIGH for a
particular logic family. The number 3.3 is the value of the time constant for
a capacitor to charge, based on the time constant equation = RC.
Approximately three (3) time constants equal one (1) rise time. Since we
are interested in only one time constant for calculating this capacitance
value, the value of the time constant period, k = 1/3t , which becomes 3.3t
r r
when incorporated within the equation (inverse of 1/3t ).
r
For example, if the edge rate is 5 ns and the impedance of the circuit is
140 , calculate the maximum value of C as
(3.12)
Get MathML
A 60-MHz clock with a period of 8.33 ns on and 8.33 ns off, R = 33
(typical for an unterminated TTL part) has an acceptable t = t = 2 ns (25%
r f
of the on or off value). Therefore,
(3.13)
Get MathML
Method 2
For wave shaping, determine the highest frequency to be filtered, f .
max
For differential pair traces, determine the maximum tolerable value for
each capacitor. To minimize signal distortion, using Eq. (3.14)
(3.14)
Get MathML
To filter a 20 MHz signal with R = 140 , the capacitance value with low
L
source impedance, Z , would be
c
(3.15)
Get MathML
Select a capacitor with proper voltage rating and dielectric material for
intended use.
Verify the functionality of the circuit with the capacitor installed. Too
large a value capacitor can cause excessive signal degradation.
3.6.3 Bulk
Bulk capacitors ensure that a sufficient amount of DC voltage and current
is available, especially when digital components transition all data,
address, and control signals simultaneously under maximum capacitive
load. Maximum capacitive load refers to the total amount of current that
must enter the power pins of a component. The component then sends this
transient current to all output loads. Each load connected to a routed net
consumes current. The greater the number of loads, the greater the
amount of current that must pass through the source driver.
When using bulk capacitors, the voltage rating can be calculated such that
the nominal voltage level equals 50% of the capacitor's actual rating to
prevent self-destruction, should a voltage surge occur. For example, with
power at 5 volts, one should use a capacitor with a minimum of a 10-volt
rating.
Memory arrays require additional bulk capacitors owing to the extra current
required for proper operation during a refresh cycle. The same is true for
VLSI components with large pin counts. High-density pin grid array (PGA)
modules also must have additional bulk capacitors provided, especially
when all signal, address, and control pins switch simultaneously under
maximum capacitive load.
Example 1
1. Determine maximum current (I) consumption anticipated on the
board. Assume all gates switch simultaneously. Include the effect of
power surges by logic crossover (cross-conduction currents).
(3.16)
Get MathML
(3.17)
Get MathML
(3.18)
Get MathML
Example 2
A PCB has 200 CMOS gates (G), each switching 5 pF (C) loads within a 2-
ns time period. Power supply inductance is 80 nH.
(3.19)
Get MathML
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Table of Contents
Chapter 3 - Bypassing and Decoupling
Chapter 3
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
3.1: REVIEW OF RESONANCE
by Mark I. Montrose
3.2: PHYSICAL
CHARACTERISTICS IEEE Press 2000
3.3: CAPACITORS IN
PARALLEL
3.4: POWER AND GROUND Recommend this title?
PLANES
3.5: PLACEMENT
3.6: HOW TO PROPERLY
SELECT A CAPACITOR
REFERENCES
REFERENCES
[1] Montrose, M. 1999. EMC and the Printed Circuit BoardDesign,
Theory and Layout Made Simple. Piscataway, NJ: IEEE Press.
[9] Johnson, H. W., and M. Graham. 1993. High Speed Digital Design.
Englewood Cliffs, NJ: Prentice Hall.
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Table of Contents
Chapter 4 - Clock Circuits, Trace Routing, and Terminations
Chapter 4
4.1: CREATING Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
TRANSMISSION LINES
WITHIN A PCB by Mark I. Montrose
4.2: TOPOLOGY
IEEE Press 2000
CONFIGURATIONS
4.3: PROPAGATION DELAY
AND DIELECTRIC CONSTANT Recommend this title?
4.4: CAPACITIVE LOADING OF
SIGNAL TRACES
4.5: COMPONENT
PLACEMENT
4.6: IMPEDANCE
MATCHINGREFLECTIONS
AND RINGING
4.7: CALCULATING TRACE
LENGTHS (ELECTRICALLY
LONG TRACES)
4.8: TRACE ROUTING
4.9: ROUTING LAYERS
4.10: CROSSTALK
4.11: TRACE SEPARATION
AND THE 3-W RULE
4.12: GUARD/SHUNT TRACES
4.13: TRACE TERMINATION
REFERENCES
Chapter 4: Clock Circuits, Trace
Routing, and Terminations
4.1 CREATING TRANSMISSION LINES WITHIN A PCB
With today's high-technology products and faster logic devices,
transmission line effects have become a limiting factor for proper circuit
operation. Traces routed adjacent to a reference plane, or RF return path,
form a simple transmission line. Consider the case of a multi-layer PCB.
When a trace is routed on an outer layer, we have the microstrip topology,
though it may be asymmetrical in construction. When a trace is routed on
an internal layer, this is called the stripline. This chapter provides details,
definitions, and differences regarding microstrip and stripline topology.
Trace thickness.
First-order effects are detailed in the equations for microstrip and stripline
topologies. Use of field solvers (which are beyond the scope of this book)
reveals that second-order effects result in
1. Extent of the return path. The longer the trace route, the greater the
inductance value. This distance also includes the RF return path.
Approximations should be used only for tradeoff analysis when using first-
order effects. Rules-of-thumb are powerful tools allowing one to perform
quick sanity checks. The accuracy of analytical approximations varies,
depending on specific applications, and is hard to generate. Accuracy of
simulation tools is based on models. The models for the circuit may not be
available. Before relying on simulation tools to calculate trace impedance,
the vendor of the PCB should be consulted to verify the accuracy of
parameters used within the equations. Without accurate numbers for
material proprieties, a lot of time will be wasted trying to simulate an
answer, when a simple calculator will provide a result that is accurate for
most applications.
Note None of the equations provided in the next section for microstrip
and stripline is applicable to PCBs constructed of two or more
dielectric materials, excluding air, or fabricated with more than one
type of laminate. All equations are extracted from IPC-D-317A,
Design Guidelines for Electronic Packaging Utilizing High-Speed
[1]
Technique [4].
[1]
Within the IPC standardsm typographical and mathematical errors exist
in the section related to impedance calculation. Before applying equations
detailed within IPC-D-317, study and identify all errors before literal use.
Equations presented herein have been independently verified for accuracy.
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Table of Contents
Chapter 4 - Clock Circuits, Trace Routing, and Terminations
Chapter 4
4.1: CREATING Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
TRANSMISSION LINES
WITHIN A PCB by Mark I. Montrose
4.2: TOPOLOGY
IEEE Press 2000
CONFIGURATIONS
4.2.1: Microstrip Topology
4.2.2: Embedded Microstrip Recommend this title?
Topology
4.2.3: Single-Stripline
Topology
4.2.4: Dual or Asymmetric
Stripline Topology
4.2.5: Differential Microstrip
and Stripline Topology
4.3: PROPAGATION DELAY
AND DIELECTRIC CONSTANT
4.4: CAPACITIVE LOADING OF
4.2 TOPOLOGY CONFIGURATIONS
SIGNAL TRACES
4.5: COMPONENT
PLACEMENT
4.6: IMPEDANCE
MATCHINGREFLECTIONS
4.2.1 Microstrip Topology
AND RINGING
4.7: CALCULATING TRACE
LENGTHS (ELECTRICALLY Microstrip is one topology used to provide trace-controlled impedance on a
LONG TRACES)
4.8: TRACE ROUTING
PCB for digital circuits. Microstrip lines are exposed to both air and a
4.9: ROUTING LAYERS dielectric referenced to a planar structure. The approximate formula for
4.10: CROSSTALK
4.11: TRACE SEPARATION
calculating the impedance of a surface microstrip trace is provided in Eq.
AND THE 3-W RULE (4.1) for the configuration of Fig 4.2. The intrinsic capacitance of the trace
4.12: GUARD/SHUNT TRACES
4.13: TRACE TERMINATION is described by Eq. (4.2).
REFERENCES
(4.1)
Get MathML
(4.2)
Get MathML
Note Use consistent dimensions for width, thickness, and height above
a reference plane (inches or centimeters). The value for C is
o
provided in inches, which is easily converted to metric.
(4.3)
Get MathML
(4.4)
Get MathML
(4.5)
Get MathML
(4.6)
Get MathML
(4.7)
Get MathML
(4.8)
Get MathML
(4.9)
Get MathML
(4.10)
Get MathML
(4.11)
Get MathML
The propagation delay for the dual stripline configuration is the same as
that for the single stripline, since both configurations are embedded in a
single, homogeneous dielectric material.
(4.12)
Get MathML
Note When using dual stripline topology, both layers must be routed
orthogonal to each other. This means that one layer is provided for
the x-axis traces, while the other layer is used for y-axis traces.
Routing these layers at 90-degree angles to each other prevents
crosstalk from developing between the two planes, especially with
wide busses. High-frequency traces can cause data corruption to
the alternate routing layer.
When two traces are routed parallel to each other, magnetic field coupling
occurs between the two transmission lines. The magnitude of coupling
induces a current from one trace to the other. Therefore, the mutual
inductance between traces will cause the differential-mode impedance to
be approximately twice that of single-ended.
For Fig. 4.6, differential traces are shown. If the configuration is microstrip,
an upper reference plane is not provided. For stripline, both reference
planes are provided, with equal center spacing between the parallel traces
and the two reference planes.
(4.13)
Get MathML
where
(4.14)
Get MathML
There are five reasons why differential pair traces are used:
1. To match an external, balanced differential transmission line. For
purposes of illustration, intertrace coupling is irrelevant. Two
independent 50-ohm traces will couple a signal into a 100-ohm
differential pair. The application is to guarantee that the signal
transmitted is purely differential. No common-mode components are
to be present within the transmission line. These two traces must
have equal impedance to ground; that is, they need to be symmetrical
but not necessarily physically close together.
3. To reduce EMI. Magnetic flux from one trace of the differential pair is
canceled by the magnetic flux traveling in the opposite direction from
the adjacent trace, resulting in a significant reduction in emissions.
This cancellation is proportional to the ratio S/D where S is trace
separation and D is the distance to the receiving antenna. For FCC
Class B, at a distance of 3 meters (117 in. or 297 cm), a 1 in. (2.54
cm) separation would yield a 40-dB reduction in EMI. A 0.10 in. (0.25
cm) separation should yield 60 dB. These attenuation values are
better than having a common-mode balance between the two outputs
that create the differential signal. With a separation of 0.10 in., we
have balanced the signal as best as possible, given imperfections in
the source driver. At the 0.10 in. separation level, the reduction in
emissions is at a level far below FCC limits. For EMI purposes,
differential trace spacing of 0.10 in. is close enough to be adequate.
We need not struggle to place the traces any closer than this
distance, as far as EMI requirements are concerned.
Unless absolutely pressed for space, the preferred routing method is the
side-by-side format (edge-coupled). These traces should be kept near
each other and they may be separated from time to time, as needed, to go
around obstacles such as vias while keeping both routing lengths nearly
equal. Figure 4.7 illustrates two configurations of differential routing.
The dielectric value between the two signal pairs can become critical
when routing on different layers as a trace pair. Different dielectrics may
cause a variation in the differential impedance along the entire trace
route.
Use wide line widths to cut down on the impedance variation caused by
registration problems and etch-back.
Ensure that the trace pair is located on the same core material. This
helps reduce impedance variation caused by fabrication tolerances.
Both signal amplitude loss and crosstalk have a number of variables that
need to be considered. This situation exists with both single-ended and
differential-mode transmissions. Crosstalk is developed by either capacitive
or inductive coupling. Reducing coupling would yield identical results
regardless of routing topology. The same is true for signal-amplitude
losses. Theoretically, DC resistance, skin effect, and dielectric losses can
all be manipulated. Again, identical results would be observed.
Wider trace widths are needed to keep the line impedance stable with
regard to layer registration in broadside-coupled construction.
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Table of Contents
Chapter 4 - Clock Circuits, Trace Routing, and Terminations
Chapter 4
4.1: CREATING Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
TRANSMISSION LINES
WITHIN A PCB by Mark I. Montrose
4.2: TOPOLOGY
CONFIGURATIONS IEEE Press 2000
4.3: PROPAGATION
DELAY AND DIELECTRIC Recommend this title?
CONSTANT
4.4: CAPACITIVE LOADING OF
SIGNAL TRACES
4.5: COMPONENT
PLACEMENT
4.6: IMPEDANCE
MATCHINGREFLECTIONS
AND RINGING
4.7: CALCULATING TRACE
4.3 PROPAGATION DELAY AND DIELECTRIC
LENGTHS (ELECTRICALLY
LONG TRACES) CONSTANT
4.8: TRACE ROUTING
4.9: ROUTING LAYERS
4.10: CROSSTALK
Electromagnetic waves propagate at a speed that is dependent on the
4.11: TRACE SEPARATION electrical properties of the surrounding medium. Propagation delay is
AND THE 3-W RULE
4.12: GUARD/SHUNT TRACES typically measured in units of picoseconds/inch. Propagation delay is the
4.13: TRACE TERMINATION inverse of velocity of propagation (the speed at which data is transmitted
REFERENCES
through conductors in a PCB). The dielectric constant, , varies with
r
several material parameters. Factors that influence the relative permittivity
include the electrical frequency, temperature, extent of water absorption
(also forming a dissipative loss), and the electrical characterization
technique. In addition, if the PCB material is a composite of two or more
laminates, the value of may vary significantly, as the relative amount of
r
resin and glass of the composite is varied [4].
(4.15)
Get MathML
For FR-4, the propagation delay of a signal between a source and load for
various topologies, with a dielectric constant of 4.3, based on Eqs. (4.3,
4.6, 4.9, 4.12) is presented in Table 4.1.
Table 4.1: Velocity of Propagation for Various Topologies (Dielectric
Constant = 4.3)
Open table as spreadsheet
Embedded microstrip, single stripline, and dual stripline have the same
value for propagation delay because the transmission line is completely
surrounded by a dielectric. Microstrip has one-half of the transmission line
in a dielectric, whereas the other one-half is in air. Therefore, the velocity of
propagation of the electromagnetic wave within the microstrip transmission
line is faster.
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Table of Contents
Chapter 4 - Clock Circuits, Trace Routing, and Terminations
Chapter 4
4.1: CREATING Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
TRANSMISSION LINES
WITHIN A PCB by Mark I. Montrose
4.2: TOPOLOGY
CONFIGURATIONS IEEE Press 2000
4.3: PROPAGATION DELAY
AND DIELECTRIC CONSTANT Recommend this title?
4.4: CAPACITIVE
LOADING OF SIGNAL
TRACES
4.5: COMPONENT
PLACEMENT
4.6: IMPEDANCE
MATCHINGREFLECTIONS
AND RINGING
4.7: CALCULATING TRACE
4.4 CAPACITIVE LOADING OF SIGNAL TRACES
LENGTHS (ELECTRICALLY
LONG TRACES)
4.8: TRACE ROUTING When digital devices are used within a circuit, each input pin of a
4.9: ROUTING LAYERS component contains a specific value of input capacitance. With many
4.10: CROSSTALK
4.11: TRACE SEPARATION components, the summation of this capacitance can become substantial.
AND THE 3-W RULE
4.12: GUARD/SHUNT TRACES
This condition is identified as capacitive loading, and it affects both signal
4.13: TRACE TERMINATION integrity and EMI. Capacitive input loading also lowers the value of the
REFERENCES
trace impedance when additional devices are added to the routed net. The
unloaded propagation delay for a transmission line is defined by .
This equation is valid when no devices are connected to the end of the net
(open circuit). If a load, C , is placed in the transmission line (including all
d
loads with their capacitance added together), the propagation delay, or
slowing down of the signal, will increase by a factor of Eq. (4.16). This
means that the signal will arrive at the load at a later time than if no loads
were provided.
(4.16)
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For C , units must be per unit length, not the total line capacitance.
o
(4.17)
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This equation gives us the total propagation delay within the transmission
line due to added capacitance, not the added delay contributed by the
capacitance. The signal arrives at its destination 0.92 ns/ft (0.19 ns/cm)
later than expected (2.57 - 1.65 = 0.92 ns/ft).
(4.18)
Get MathML
Get MathML
Typical values of C are 5 pF for ECL inputs, 10 pF for each CMOS device,
d
and 1015 pF for TTL. Typical C values of a PCB traces are 22.5
o
pF/inch. These C values are subject to wide variations due to the physical
o
geometry and the length of the trace. Sockets and vias also add to the
overall distributed capacitance of the transmission line. Sockets add
approximately 2-pF capacitance for each one, and vias approximately 0.3
0.8 pF each. Given that and , total trace
distributed capacitance, C , is calculated as
o
(4.19)
Get MathML
This loaded propagation delay value is one method that may be used to
decide whether a trace needs be treated as a transmission line (2 * t' *
pd
trace length > t or t ) where t is the rising edge of the signal transition and
r f r
t the falling edge.
f
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Table of Contents
Chapter 4 - Clock Circuits, Trace Routing, and Terminations
Chapter 4
4.1: CREATING Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
TRANSMISSION LINES
WITHIN A PCB by Mark I. Montrose
4.2: TOPOLOGY
CONFIGURATIONS IEEE Press 2000
4.3: PROPAGATION DELAY
AND DIELECTRIC CONSTANT Recommend this title?
4.4: CAPACITIVE LOADING OF
SIGNAL TRACES
4.5: COMPONENT
PLACEMENT
4.6: IMPEDANCE
MATCHINGREFLECTIONS
AND RINGING
4.7: CALCULATING TRACE
LENGTHS (ELECTRICALLY
LONG TRACES)
4.8: TRACE ROUTING
4.5 COMPONENT PLACEMENT
4.9: ROUTING LAYERS
4.10: CROSSTALK Clock circuits should be located near a ground stitch location (to chassis
4.11: TRACE SEPARATION
AND THE 3-W RULE
ground) on the PCB rather than along the perimeter or near the I/O section.
4.12: GUARD/SHUNT TRACES If the transmission line goes to a daughter card, ribbon cable, or peripheral
4.13: TRACE TERMINATION
REFERENCES
located remote from the main PCB, the transmission line must be
terminated directly at the connector or boundary location. It is imperative
that this be a point-to-point radial, discussed later in this chapter.
Termination of traces enhances signal quality instead of the unterminated
clock line being left open ended. An open-ended transmission line will
energize a dipole antenna. (Trace is the driven element, and 0V-reference
is the ground element.) In addition to termination, suppression of radiated
RF currents coupling into other areas susceptible to RF corruption is
prevented, discussed later in this chapter.
Oscillators and crystals must be installed directly on the PCB. Do not use
sockets! Sockets add additional lead inductance (LdI/dt) to the
transmission line. Inductance allows a voltage potential difference to be
established between the silicon die and bonding pad. This voltage potential
difference develops common-mode RF energy. Sockets, like lead-length
inductance, provides an additional path for radiated RF currents and
harmonics to couple into areas both internal to the product and outside
environment.
When placing PCB components during layout that use clocks or periodic
signals, these devices must be located so that periodic signal or clock
traces are routed for a best straightline path possible with minimal length
and number of vias. Vias add inductance to the trace, approximately 1 to 3
nH each. Inductance in a trace may cause signal integrity concerns and
potential RF emissions. The faster the edge-rate transition of a signal, the
more this design rule approaches mandatory status. If a periodic signal or
clock trace must traverse from one routing plane to another, this transition
should occur at a component lead (pin escape) and not anywhere else, if
possible, to reduce additional inductance within the transmission line from
use of additional vias.
Any periodic signal or clock circuitry located within 2 in. (5 cm) of I/O
components (or I/O connectors) should have edge rate transitions (t or t )
r f
slower than 10 ns, since most I/O circuits (serial, parallel, audio, and the
like) are generally slow compared to other functional areas. It is
recommended that traces located within 3 in. (7.6 cm) of an I/O section
should have an edge rate transition between 5 and 10 ns. This general rule
of locating clocks near I/O areas is not required when functional partitioning
occurs (Chapter 5). This is because functional partitioning of the power and
ground planes in an I/O area prevents RF currents that exist in other
sections of the board from entering the I/O section. RF currents can be
coupled onto I/O cables and radiated to the external environment as
common-mode or differential-mode energy. Keeping RF currents created
from periodic or clock signals entering I/O circuitry is the ultimate design
objective.
The old directive to "keep all clock lines short" is valid. The longer the trace
length, the greater the probability that RF currents will be produced and
more spectral distribution of RF energy will be developed. Clock traces
must be terminated to reduce ringing and creation of avoidable RF
currents. This is because unterminated transmission lines generate signal
reflections that can cause EMI to be generated (detailed in the next
section). Clock traces might also be degraded to the point of being
nonfunctional owing to transmission line effects.
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Table of Contents
Chapter 4 - Clock Circuits, Trace Routing, and Terminations
Chapter 4
4.1: CREATING Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
TRANSMISSION LINES
WITHIN A PCB by Mark I. Montrose
4.2: TOPOLOGY
CONFIGURATIONS IEEE Press 2000
4.3: PROPAGATION DELAY
AND DIELECTRIC CONSTANT Recommend this title?
4.4: CAPACITIVE LOADING OF
SIGNAL TRACES
4.5: COMPONENT
PLACEMENT
4.6: IMPEDANCE
MATCHING
REFLECTIONS AND
RINGING
4.7: CALCULATING TRACE
4.6 IMPEDANCE MATCHINGREFLECTIONS AND
LENGTHS (ELECTRICALLY
LONG TRACES) RINGING
4.8: TRACE ROUTING
4.9: ROUTING LAYERS
4.10: CROSSTALK
Reflections are unwanted byproducts in digital logic designs. This section
4.11: TRACE SEPARATION discusses why reflections are unwanted. Ringing within a transmission line
AND THE 3-W RULE
4.12: GUARD/SHUNT TRACES contains both overshoot and ringing before stabilizing to a quiescent level
4.13: TRACE TERMINATION
and is a manifestation of the same effect. Overshoot is the effect of an
REFERENCES
excessive voltage level above the power rail or below the ground
reference. Excessive voltage levels below ground reference are still
identified as overshoot. Undershoot is a condition that occurs when the
voltage level does not reach the desired amplitude for both maximum and
minimum transition levels. Components must have a sufficient tolerance
rating to voltage margin requirements. Overshoot can be controlled by
terminations and proper PCB and IC package design. Overshoot, if severe
enough, can overstress devices and cause damage or failure. Overshoot
and undershoot are illustrated in Fig. 4.8.
Reflections are frequently both a signal integrity and an EMI issue, when
the edge time of the signal constitutes a significant percentage of the
propagation time between the device load intervals. Solutions to reflection
problems may require extending the edge time (slowing the edge rate) or
decreasing the distance between load device intervals.
Lack of terminations.
Connector transitions.
[2]
A bifurcated trace is a single trace that is broken up into two traces
routed to different locations.
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Table of Contents
Chapter 4 - Clock Circuits, Trace Routing, and Terminations
Chapter 4
4.1: CREATING Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
TRANSMISSION LINES
WITHIN A PCB by Mark I. Montrose
4.2: TOPOLOGY
CONFIGURATIONS IEEE Press 2000
4.3: PROPAGATION DELAY
AND DIELECTRIC CONSTANT Recommend this title?
4.4: CAPACITIVE LOADING OF
SIGNAL TRACES
4.5: COMPONENT
PLACEMENT
4.6: IMPEDANCE
MATCHINGREFLECTIONS
AND RINGING
4.7: CALCULATING
TRACE LENGTHS
(ELECTRICALLY LONG
TRACES)
4.8: TRACE ROUTING
4.9: ROUTING LAYERS
4.10: CROSSTALK
4.11: TRACE SEPARATION
AND THE 3-W RULE
4.12: GUARD/SHUNT TRACES
4.13: TRACE TERMINATION
REFERENCES
(4.20)
Get MathML
Figure 4.9 illustrates Eq. (4.20) for quick reference with a dielectric
constant of 4.6 used within the equation.
Figure 4.9: Maximum unterminated line length vs. signal edge rate (FR-
4 material).
To simplify Eq. (4.20), the real value of the propagation delay within the
transmission must be determined using the actual dielectric constant value
based at the frequency of interest. Both propagation delay and edge
transition rate must be taken into account. Equations (4.21) and (4.22) are
presented for determining the maximum routed electrical line length before
termination becomes mandatory. This length is for round-trip distance. The
one-way length from source to load is one-half the value of l calculated.
max
The factor (k) used in the calculation is for a dielectric constant value of
4.6.
(4.21)
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(4.22)
Get MathML
For example, if the minimum edge rate signal transition is 2 ns, the
maximum round-trip, unterminated trace length possible before termination
is required, when routed microstrip is
Get MathML
When routed stripline, the maximum unterminated trace length of this same
2 ns signal edge becomes
Get MathML
To calculate the constant "k," (9 or 7) found within Eqs. (4.21) and (4.22),
use the following example:
Get MathML
Example: with = 4.6, k = 8.87 for microstrip (in cm) or 3.49 (in inches)
r
(4.23)
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Microstrip Example
Get MathML
Get MathML
Get MathML
Get MathML
Get MathML
Get MathML
From above:
Get MathML
Again, this trace would not require termination since 3.4 ns 5 ns. The
propagation delay for stripline is 1.60 ns longer because t (unloaded) is
pd
substantially greater than microstrip (0.65 ns margin). This factor helps
prevent transmission line effects from being masked during edge rate
changes.
Stripline Example
A 2-ns edge rate device on a 10 in. stripline trace is used. Five logic
devices are distributed throughout the route. Each device has an input
capacitance of 12 pF. Is termination required for this route?
Geometry
Trace width, W = 0.006 in.
Get MathML
Get MathML
Get MathML
Get MathML
Get MathML
Since the edge rate of the component t = t = 2 ns, and propagation delay
r f
(6.4 2), termination is required to absorb transmission line effects.
From above:
Get MathML
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Table of Contents
Chapter 4 - Clock Circuits, Trace Routing, and Terminations
Chapter 4
4.1: CREATING Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
TRANSMISSION LINES
WITHIN A PCB by Mark I. Montrose
4.2: TOPOLOGY
CONFIGURATIONS IEEE Press 2000
4.3: PROPAGATION DELAY
AND DIELECTRIC CONSTANT Recommend this title?
4.4: CAPACITIVE LOADING OF
SIGNAL TRACES
4.5: COMPONENT
PLACEMENT
4.6: IMPEDANCE
MATCHINGREFLECTIONS
AND RINGING
4.7: CALCULATING TRACE
LENGTHS (ELECTRICALLY
LONG TRACES)
4.8: TRACE ROUTING 4.8 TRACE ROUTING
4.8.1: Single-Ended
Transmission Lines
4.8.2: Differential Pair
Signaling
4.9: ROUTING LAYERS 4.8.1 Single-Ended Transmission Lines
4.10: CROSSTALK
4.11: TRACE SEPARATION
AND THE 3-W RULE Engineers and designers sometimes daisy-chain traces for ease of routing.
4.12: GUARD/SHUNT TRACES Unless the distance is small between loads, with respect to propagation
4.13: TRACE TERMINATION
REFERENCES length and signal edge transitions, signal integrity concerns may develop.
These concerns include ringing and reflection. Daisy-chaining may also
impact signal quality and EMI spectral energy distribution to the point of
nonfunctionality or noncompliance. Therefore, radial connections for fast
edge transition signals are preferred over daisy-chaining for nets with a
single, common drive source. Radial connection refers to a single point-to-
point connection from a driver capable of sourcing multiple loads
simultaneously. Each component must have its respective trace terminated
in its characteristic impedance as shown in Fig. 4.10, using a termination
method appropriate for circuit operation.
2. Return currents and layer jumping. Flux cancellation for the return
current may not be optimal, especially for certain configurations.
Assume a double-sided PCB with no power and ground plane.
Separating the differential pair will result in significant development
and propagation of RF energy. For multilayer assemblies, the return
current may not have an optimal, low-impedance return path, thus
allowing a RF loop to exist. For long routed traces, this loop could be
significant. Common-mode RF energy is now developed.
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Table of Contents
Chapter 4 - Clock Circuits, Trace Routing, and Terminations
Chapter 4
4.1: CREATING Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
TRANSMISSION LINES
WITHIN A PCB by Mark I. Montrose
4.2: TOPOLOGY
CONFIGURATIONS IEEE Press 2000
4.3: PROPAGATION DELAY
AND DIELECTRIC CONSTANT Recommend this title?
4.4: CAPACITIVE LOADING OF
SIGNAL TRACES
4.5: COMPONENT
PLACEMENT
4.6: IMPEDANCE
MATCHINGREFLECTIONS
AND RINGING
4.7: CALCULATING TRACE
LENGTHS (ELECTRICALLY
LONG TRACES) 4.9 ROUTING LAYERS
4.8: TRACE ROUTING
4.9: ROUTING LAYERS
4.9.1: Which Layers to
PCB designers need to determine which signal layers to use for routing
Route Traces On
4.9.2: Layer JumpingUse
clocks and periodic signals. Clocks and periodic signals must be routed on
of Vias either one layer or on an adjacent layer separated by a same potential
4.10: CROSSTALK
4.11: TRACE SEPARATION reference plane. An example of routing a trace between layers is shown in
AND THE 3-W RULE
4.12: GUARD/SHUNT TRACES
Fig. 4.12. Three issues must be remembered when selecting routing
4.13: TRACE TERMINATION layers: deciding which layers to use for trace routing, jumping between
REFERENCES
designated layers, and maintaining constant transmission line impedance.
Three phenomena by which planes and hence, PCBs, create EMI are
enumerated next. Proper understanding of these concepts will allow the
designer to incorporate suppression techniques on any PCB in an optimal
manner.
1. Discontinuities in the image plane due to the use of vias and jumping
clock traces between layers. The RF return current will be diverted
from having a direct-line RF return path, creating a loop antenna.
2. Peak surge currents injected into the power and ground network
(image planes) due to components switching output signals. These
surge current spikes propagate throughout the PCB, which is what we
do not want.
3. Flux loss into the annular keep-out region of vias if 3-W routing is not
provided for the trace route. Physical separation of a trace from a via
must also conform to 3-W spacing. The 3-W rule is discussed in the
next section. This requirement prevents RF energy (magnetic flux)
that is present within a transmission line (trace) from coupling into the
via. This via may contain a static signal, such as reset, and may re-
propagate RF energy throughout the PCB into areas susceptible to
RF disruption.
As a signal trace jumps from one layer to another, RF return current tries to
mirror image the trace route. When a trace is routed internal to a PCB
between two planar structures, commonly identified as the power and
ground planes, or two planes with the same potential, return current is
shared between these two planes. Return current can jump between
different potential planes only at a location where there are decoupling
capacitors. If both planes are at the same potential (0V-reference), the RF
return current jump will occur at a location where a via connects both 0V-
references planes together, using the component's ground pin assigned to
that via.
What happens when only one 0V-reference (ground) plane is provided and
the alternate plane is at voltage potential, commonly found with four-layer
stackups? To maintain a constant return path for RF currents, the 0V
(ground) plane should be allowed to act as the primary return path. The
majority of the signal trace must be routed against this 0V-plane. When the
trace routes against the power plane, after jumping layers, use of a ground
trace is required only on the layer adjacent to the power plane layer. This
ground trace must connect to the ground plane, by vias, at both ends. This
trace must also be parallel to the signal trace at a distance spacing that is
as close as manufacturable. Using this configuration, we now maintain a
constant RF return path throughout the entire route (Fig. 4.15).
How can we minimize the use of ground vias when layer jumping is
mandatory? In a properly designed PCB, the first traces to be routed are
clock or high-threat signals, which must be "manually routed!" The PCB
designer is permitted much freedom in routing the first few traces. The
designer is then able to route the rest of the board using direct-line routing
(shortest Manhattan length). These first few routed traces must make a
layer jump adjacent to the ground pin via of a component. This layer jump
will co-share this component's ground pin. This joint ground pin will provide
both 0V-references to the component, while allowing RF return current to
make the layer jump, as detailed in Fig. 4.16.
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Personal account | University of Southern Queensland
Table of Contents
Chapter 4 - Clock Circuits, Trace Routing, and Terminations
Chapter 4
4.1: CREATING Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
TRANSMISSION LINES
WITHIN A PCB by Mark I. Montrose
4.2: TOPOLOGY
CONFIGURATIONS IEEE Press 2000
4.3: PROPAGATION DELAY
AND DIELECTRIC CONSTANT Recommend this title?
4.4: CAPACITIVE LOADING OF
SIGNAL TRACES
4.5: COMPONENT
PLACEMENT
4.6: IMPEDANCE
MATCHINGREFLECTIONS
AND RINGING
4.7: CALCULATING TRACE
LENGTHS (ELECTRICALLY
LONG TRACES)
4.8: TRACE ROUTING
4.10 CROSSTALK
4.9: ROUTING LAYERS
4.10: CROSSTALK
4.10.1: Description of
Crosstalk
4.10.1 Description of Crosstalk
4.10.2: Design Techniques
to Prevent Crosstalk
4.11: TRACE SEPARATION Crosstalk is one important aspect of a layout that must be considered
AND THE 3-W RULE
4.12: GUARD/SHUNT TRACES during the design cycle. It refers specifically to unintended electromagnetic
4.13: TRACE TERMINATION coupling between traces, wires, trace-to-wire, cable assemblies,
REFERENCES
components, and other electrical components subject to electromagnetic
field disturbance. These paths include PCB traces. This undesirable effect
is associated not only with clock or periodic signals, but also with other
system critical nets. Data, address, control lines, and I/O may be affected
by crosstalk and coupling effects. Clock and periodic signals create the
majority of problems and can cause serious functionality concerns (signal
integrity) to other sections of the assembly.
For crosstalk to occur, three or more conductors are required. These three
conductors are identified in Fig. 4.17. Two lines carry the signal of interest,
and the third line is a reference conductor that gives the circuit the ability to
talk (communicate) by capacitive or inductive coupling. If a two-wire system
is provided, one of the wire pair is usually at reference potential while the
other is differential. This prevents crosstalk from naturally occurring [6].
Figure 4.17 illustrates coupling between two circuits due to the result of a
nonzero impedance in the mutual reference conductor. This nonzero
impedance is a prime reason to maintain a low-impedance path between
connecting points.
With parallel routed traces, two forms of crosstalk are observed: forward
and backward. The signal that appears on the victim line at the source of
the inducing line is referred to as backward crosstalk, whereas the signal
observed at the received end of the victim trace is identified as forward
crosstalk. Backward crosstalk is considered a greater concern than forward
crosstalk. The high impedance in the circuit between source and victim
trace will produce a high level of crosstalk. Figure 4.18 illustrates both
forward and backward inductive crosstalk effects.
Capacitive and inductive coupling can now be detailed (see Fig. 4.19). If a
signal is sent from source-to-load, trace A-B, the signal will capacitively
couple to the adjacent trace C-D only, providing the two lines are parallel to
each other and are in close proximity. The larger the capacitance between
the two traces (mutual capacitance), the tighter the coupling that occurs
with electromagnetic energy transferred between the two. The coupled
voltage on the victim trace, C-D, causes a current to flow from the
"coupling point" toward both ends of the trace. The current going back
toward the source, C, is backward crosstalk, whereas the signal traveling
to the load, D, is forward crosstalk. The two traces also have mutual
inductance between them, causing inductive coupling, L . If the output
m
impedance of the driver, C, is normally low compared to the transmission
line impedance, most of the backward crosstalk is reflected back toward
the driver, C. Since a capacitor conducts RF energy (current) efficiently at
high frequencies, the faster the edge rate, the greater the crosstalk.
Figure 4.19: Fundamental representation of crosstalk.
10. Isolate routing layers that must be routed in the same axis by a solid
planar structure (typical of backplane stackup assignments).
When using mixed logic families, design rules must take into consideration
coupling levels between parallel traces. Five percent coupling between TTL
traces may be acceptable. However, if the victim trace is TTL to LVDS
(low-voltage differential signaling), ECL, or PCI bus, 5 percent variation of
signal transition for a MOS (metal-oxide-silicon) component may be too
much. To make sure that intertechnology coupling is properly managed,
distance spacing must be calculated between similar logic families and
between different technologies of component designs. When performing
calculations for different technologies on the same routing layer, one must
identify those traces that require one set of calculations and another set of
dimensions for the other circuits. This information needs to be provided to
the autorouter as a routing constraint. This is best achieved when a special
list of net-classes is identified to the router. Various crosstalk configurations
are shown in Fig. 4.20.
(4.24)
Get MathML
For embedded microstrip, if the parallel traces are at different heights, the
2
H term becomes the product of the two heights, shown in Fig. 4.20 and
Eq. (4.25). The dimension D becomes the direct distance between the
centerline of the traces [10].
(4.25)
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(4.26)
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Personal account | University of Southern Queensland
Table of Contents
Chapter 4 - Clock Circuits, Trace Routing, and Terminations
Chapter 4
4.1: CREATING Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
TRANSMISSION LINES
WITHIN A PCB by Mark I. Montrose
4.2: TOPOLOGY
CONFIGURATIONS IEEE Press 2000
4.3: PROPAGATION DELAY
AND DIELECTRIC CONSTANT Recommend this title?
4.4: CAPACITIVE LOADING OF
SIGNAL TRACES
4.5: COMPONENT
PLACEMENT
4.6: IMPEDANCE
MATCHINGREFLECTIONS
AND RINGING
4.7: CALCULATING TRACE
LENGTHS (ELECTRICALLY
LONG TRACES) 4.11 TRACE SEPARATION AND THE 3-W RULE
4.8: TRACE ROUTING
4.9: ROUTING LAYERS
4.10: CROSSTALK The 3-W rule is used basically to minimize coupling between transmission
4.11: TRACE lines or PCB traces. The rule states that the distance separation between
SEPARATION AND THE 3-
W RULE traces must be three times the width of a single trace measured from
4.12: GUARD/SHUNT TRACES
4.13: TRACE TERMINATION
centerline to centerline. Otherwise stated, the distance separation between
REFERENCES two traces, edge-to-edge, must be greater than two times the width of a
single trace. For example, a clock line is 6-mils wide. No other trace can be
routed within a minimum of 12 mils (2 * 6 mils) of this trace, edge-to-edge.
As observed, much real estate is lost in areas where trace isolation occurs.
An example of the 3-W rule is shown in Fig. 4.21.
The 3-W rule is affected by the presence of a reference plane and the
distance of the signal trace above that plane. The main item to note is that
prevention of magnetic flux coupling to adjacent traces occurs in the
horizontal axis. If a reference (return) plane is physically closer to the
signal trace than the trace-to-trace spacing, the plane will minimize
magnetic flux within the transmission line, thus enhancing performance
over that of the 3-W rule.
Note that the 3-W rule represents the approximate 70% flux boundary at
logic current levels. For the approximate 98% boundary, 10-W should be
used. These values are derived from complex mathematical analysis,
which is beyond the scope of this book.
Use of the 3-W rule is mandatory for only high-threat signals, such as
clock, differential pairs, video, audio, the reset line, or other system critical
nets. Not all traces within a PCB have to conform to 3-W routing. It is
important to determine which traces are to be classified as critical. Before
using this design technique, it is important to determine exactly which
traces must be routed 3-W.
As shown in Fig. 4.21, a via is located between two traces. This via is
usually associated with a third routed net, and it may contain a signal trace
that is susceptible to electromagnetic field disruption. For example, the
reset line, a video or audio trace, an analog level control trace, or an I/O
interface may pick up electromagnetic energy by either inductive or
capacitive means. To minimize crosstalk corruption to the via, the distance
spacing between adjacent traces must include the angular diameter and
clearance of the via. The same requirement exists for the distance spacing
between a routed trace rich in RF spectral energy that may couple to a
component's breakout pin (pin escape) to this routed trace.
Use of the 3-W rule should not be limited to clock or periodic signal traces.
Differential pairs (balanced, ECL, and similar sensitive nets) are also prime
candidates for 3-W. The distance between paired traces must be 1-W for
differential traces and 3-W from each of the differential pairs to adjacent
traces. For differential pair traces, power plane noise and single-ended
signals can capacitively, or inductively, couple into the paired traces. This
can cause data corruption if traces not associated with the differential pair
are physically closer than 3-W. An example of routing differential pair
traces within a PCB structure is shown in Fig. 4.22.
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Table of Contents
Chapter 4 - Clock Circuits, Trace Routing, and Terminations
Chapter 4
4.1: CREATING Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
TRANSMISSION LINES
WITHIN A PCB by Mark I. Montrose
4.2: TOPOLOGY
CONFIGURATIONS IEEE Press 2000
4.3: PROPAGATION DELAY
AND DIELECTRIC CONSTANT Recommend this title?
4.4: CAPACITIVE LOADING OF
SIGNAL TRACES
4.5: COMPONENT
PLACEMENT
4.6: IMPEDANCE
MATCHINGREFLECTIONS
AND RINGING
4.7: CALCULATING TRACE
LENGTHS (ELECTRICALLY
LONG TRACES)
4.12 GUARD/SHUNT TRACES
4.8: TRACE ROUTING
4.9: ROUTING LAYERS Guard traces are traces at 0V-potential that surround clocks, periodic
4.10: CROSSTALK
4.11: TRACE SEPARATION signals, differential pairs, or system critical (high-threat) nets from source to
AND THE 3-W RULE
4.12: GUARD/SHUNT
destination. Shunt traces are traces located directly above or below a high-
TRACES
4.13: TRACE TERMINATION
threat transmission line that parallels the trace along its entire route. Both
REFERENCES guard and shunt traces have unique applications, implementations, and
drawbacks. Depending on functional requirements, one or both techniques
may be used. It is up to the design engineer to select which technique is
required for suppression of RF energy (flux cancellation/minimization).
Guard and shunt traces have no effect in enhancing the signal integrity of
the desired signal. If the purpose of using guard traces is to prevent
crosstalk, or magnetic field coupling between adjacent traces, use of the 3-
W rule generally provides an adequate flux boundary, circumventing the
usefulness of a guard trace.
Shunt traces are used when the sensitivity of a trace is critical, related to
crosstalk corruption, or when a known amount of excessive RF energy will
be present within a particular transmission line or trace. Routing a trace at
0V-potential parallel, or adjacent, to the signal trace allows for enhanced
flux cancellation in differential mode. The shunt trace acts as an image
plane and must be three times the width of the signal trace to fully capture
flux that surround the trace. If the trace has an image plane on one side, at
0V-potential, and a shunt trace on the other side, also at 0V-potential, a
partial coaxial transmission line structure is developed. If guard traces are
provided with a shunt trace, a true coaxial transmission line exists. For
many applications, implementing the use of guard traces in a stripline
topology is a waste of time. A reason for this statement follows and
becomes obvious when Fig. 4.23 is examined.
Figure 4.23 is for illustrative purposes. Two examples will describe how
and why guard and shunt traces either work or do not work within a
stripline configuration.
1. The width of a trace (W) is 0.010 in. (0.25 mm). The distance spacing
between traces is also 0.010 in. (0.25 mm), per manufacturing
requirements. If the distance spacing between signal trace and image
(reference) plane (H) is 0.008 in. (0.20 mm), magnetic flux will see the
image plane long before the guard trace observes this field. With
close dimensional spacing, guard traces become useless. This is the
primary explanation for why guard traces do not work well for some
stripline configurations. If a guard trace is implemented as stripline to
remove radiated RF energy developed within the transmission line,
and the image planes located both above and below the signal trace
already prevent RF energy from radiating to the environment, why use
guard traces?
Guard and shunt traces are used for specific applications only. Applications
are product specific and may not be required in most designs. The
advantages and disadvantages of using both guard and shunt traces
include the following:
1. To enforce the 3-W rule. When we increase the distance separation
between traces, we minimize the amount of crosstalk that might
develop between high-threat traces and other nearby components or
traces. A guard trace forces the distance spacing between the source
and victim trace to be much greater than if the guard trace was not
present between the two. In addition, magnetic flux present within the
transmission line containing RF energy will be captured by the guard
trace, thus preventing crosstalk from occurring.
When using guard traces, the trace must be grounded at both source and
destination. This ground connection must be as close as possible to the
component. If the routing lengths of both the signal and guard trace are
significant, multiple connections to the ground planes by vias, along the
edges of the guard trace, are also required. These additional vias break up
the resonant effects that occur from this potential "dipole" antenna.
When guard traces are used, the spacing between the guard and signal
trace must be minimized to the smallest manufacturable distance. This
distance must be maintained throughout the length of the route. Although
the capacitive contribution of this spacing is minimal, suppression of RF
energy could be significant.
When a guard trace is forced away from a signal trace due to vias or
through-hole component leads in the routing path, this trace must be
returned to normal as soon as the detour is cleared. Never locate anything
between a signal trace and its guard trace. When two or more periodic
signal or clock traces are routed side by side, they may "share" a common
guard trace between them for only a short distance (see Fig. 4.24). All
effort must be made to prevent routing two traces within the same guard
trace if possible. Exceptions do exist, such as differential or paired signals.
Differential pair traces usually do not require use of either guard or shunt
traces.
Figure 4.24: Guard trace implementation.
It must be restated here that "guard" traces are primarily effective on one-
or two-layer circuit boards. On multilayer stackup assemblies, the flux
boundary provided by the 3-W rule will accomplish much of the benefit
provided by guard traces, taking up significantly less real estate!
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Table of Contents
Chapter 4 - Clock Circuits, Trace Routing, and Terminations
Chapter 4
4.1: CREATING Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
TRANSMISSION LINES
WITHIN A PCB by Mark I. Montrose
4.2: TOPOLOGY
CONFIGURATIONS IEEE Press 2000
4.3: PROPAGATION DELAY
AND DIELECTRIC CONSTANT Recommend this title?
4.4: CAPACITIVE LOADING OF
SIGNAL TRACES
4.5: COMPONENT
PLACEMENT
4.6: IMPEDANCE
MATCHINGREFLECTIONS
AND RINGING
4.7: CALCULATING TRACE
LENGTHS (ELECTRICALLY
LONG TRACES)
4.8: TRACE ROUTING
4.13 TRACE TERMINATION
4.9: ROUTING LAYERS
4.10: CROSSTALK Trace termination plays an important role in ensuring optimal signal integrity as
4.11: TRACE SEPARATION
AND THE 3-W RULE well as minimizing development of RF energy. To prevent impedance matching
4.12: GUARD/SHUNT TRACES
problems and provide higher quality signal transfer between circuits,
4.13: TRACE
TERMINATION termination may be required. Transmission line effects in high-speed circuits
4.13.1: Series Termination
4.13.2: End Termination and traces must always be considered. If the clock speed is fast, for example,
4.13.3: Parallel Termination
4.13.4: Thevenin 100 MHz, and components are, for example, FCT series (2 ns edge rate being
Termination
4.13.5: AC Termination
typical), reflections from a long trace route could cause the receiver to double
4.13.6: Diode Network
4.13.7: Differential or Paired
clock on a single-edge transition. This is possible because it takes a finite time
Signaling
REFERENCES
for the signal to propagate from source to load and return. If the return signal
does not occur before the next edge transition event, functionality issues arise.
Any signal that clocks a flip-flop is a possible candidate for causing
transmission line effects, regardless of actual frequency of operation.
Each source driver must have its respective output properly terminated. The
most common forms of terminations are detailed in Fig. 4.25. An excellent
discussion on using transmission line theory is found in Ref. [9, Chapters 3 and
7], and Ref. [1, 5].
The need to terminate is based on several design criteria, the most important of
which is the existence of an electrically long trace. When a trace is electrically
long, or when the length exceeds one-sixth of the electrical length of the edge
transition time, the trace requires termination. Even if a trace is short,
termination may still be required if the load is capacitive or highly inductive to
prevent ringing.
Termination not only matches trace impedance and removes (reduces) ringing
and reflections, but it may also slow down the edge rate transition of the clock
signal if incorrect values are applied. Inappropriate termination may degrade
the signal amplitude integrity to the point of nonfunctionality. Reducing either
dI/dt or dV/dt within the trace will reduce the creation of RF currents generated
by high-amplitude voltage and current levels.
3. Thevenin termination
5. Diode termination
6. Differential signals
Get MathML
To summarize:
1. The signal of interest travels down the transmission line at full voltage and
current level without degradation.
There is an optimal way to locate and route end terminators. This difference is
shown in Fig. 4.27. Regardless of the method chosen, termination must occur
at the "very end of the trace route." For purposes of discussion, the AC method
is shown in this figure.
Simple parallel termination creates a DC current path to ground when the driver
is at logic HI. Excessive power dissipation and V degradation (noise margin)
OH
occur. Because a driver's output is always switching, DC current consumed by
the termination resistor must exist. At higher frequencies, the AC switching
current becomes the major component of the circuit. When using parallel
termination, one should consider how much V degradation is acceptable by
OH
the receivers.
Designers commonly, but arbitrarily, use a 220/330 ohm ratio (132 ohms
parallel) for driving bus logic. It may be difficult to determine the resistor ratio
value, especially if the switch point for various logic families is different. This is
especially true when both TTL and CMOS are used. A 1:1 resistor ratio (e.g.,
110/110 ohms will create a 55-ohm value, the desired characteristic Z of the
o
trace) limiting the line voltage to 2.5V, thus causing an invalid transition level to
exist.
(4.28)
Get MathML
R = The drive requirements for logic HI and LOW are identical. This
1
setting may be unacceptable for most logic families.
R :
2
R > The LOW current requirements are greater than the HI current
2
requirement. This setting works well for TTL and CMOS devices.
R :
1
R > The HI current requirements are greater than the LOW current
1
requirement. This is a more appropriate selection for the majority
R :
2 of designs and logic families.
With a properly chosen termination ratio for the resistors, an optimal DC voltage
level now will exist for both logic HI and LOW states. The advantage of using
parallel termination over Thevenin is the parallel termination's use of one less
component. If we compare the effects of parallel termination to Thevenin, both
termination methods provide identical results. The signal within a transmission
line will always be identical, regardless of which termination method is chosen.
4.13.5 AC Termination
The AC (also known as RC) termination method works well in both TTL and
CMOS systems; it should be used only for clocks and never on data or address
lines. The resistor matches the characteristic impedance of the trace (identical
to parallel). The capacitor holds the DC voltage level of the signal. The source
driver does not have to provide current to drive an end terminator.
Consequently, AC current (RF energy) flows to ground during a switching state.
A capacitor allows RF energy (which is an AC sine wave, not the DC logic level
of the signal) to pass through. Although an additional propagation delay is
presented to the signal due to the RC time constant, less power dissipation
exists than parallel or Thevenin termination. From the viewpoint of the circuit,
all end termination methods are identical. The main difference lies in power
dissipation, with AC consuming far less power than the other two.
To determine the proper value of the resistor and capacitor, Eq. (4.29) provides
a simple calculation, which includes round-trip propagation delay 2 * t' .
pd
(4.29)
Get MathML
For certain applications, Schottky diodes are preferred. When using fast
switching diodes, the diode switching time must be at least four times as fast as
the signal rise time. When the line impedance is not well defined, as in
backplane assemblies, diode termination is convenient and easy to use. The
Schottky diode's low forward voltage value, V , is typically 0.3 to 0.45V. This
f
low-voltage level clamps the input signal voltage, V , to ground. For this high-
f
voltage value, the clamp level is dependent on the maximum voltage rating of
the device. When both diodes are provided, overshoot is significantly reduced
for both positive and negative transitions. Some applications may not require
that both diodes be used simultaneously.
The diodes may be able to replace termination resistors if the edge rate is
slow.
Differential signaling requires that signal traces be routed on the same layer,
either microstrip or stripline, and not a combination of both. This requirement is
due to the velocity of propagation of the transmitted signal through the dielectric
of the PCB. Signals routed microstrip will arrive at their destination faster than
traces routed stripline. The longer the trace, the more significant this
requirement becomes, especially if clock skew and timing at the differential
receiver are critical.
Two propagation modes are present with differential signaling: differential mode
and common mode. Both modes must be considered at the same time,
according to the logic family selected. Differential-mode impedance is the value
of the line-to-line resistor that will optimally terminate pure differential signals.
Common-mode termination is the value of the signal trace to chassis ground.
These types of configurations are illustrated in Fig. 4.32. Because a termination
works for one propagation mode does not mean it will work for the other.
Signals propagated differentially will also have a common-mode component.
Sometimes both termination methods are required, depending on application
and logic family.
If the need to terminate two traces is required for any signal driven into them, a
combination of both termination methods is permitted (Fig. 4.32). This
combination prevents reflections from propagating on the trace pair. To
properly select a correct terminator, the following are recommended:
1. For common-mode signals, a line-to-line terminator (differential type) is
invisible to the circuit. This means that no current flows through it.
Termination to the transmission lines must be provided as a single-ended
circuit, discussed earlier in this section.
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Table of Contents
Chapter 4 - Clock Circuits, Trace Routing, and Terminations
Chapter 4
4.1: CREATING Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
TRANSMISSION LINES
WITHIN A PCB by Mark I. Montrose
4.2: TOPOLOGY
CONFIGURATIONS IEEE Press 2000
4.3: PROPAGATION DELAY
AND DIELECTRIC CONSTANT Recommend this title?
4.4: CAPACITIVE LOADING OF
SIGNAL TRACES
4.5: COMPONENT
PLACEMENT
4.6: IMPEDANCE
MATCHINGREFLECTIONS
AND RINGING
4.7: CALCULATING TRACE
LENGTHS (ELECTRICALLY REFERENCES
LONG TRACES)
4.8: TRACE ROUTING
4.9: ROUTING LAYERS [1] Montrose, M. 1999. EMC and the Printed Circuit Board Design
4.10: CROSSTALK
4.11: TRACE SEPARATION
Design, Theory and Layout Made Simple. Piscataway, NJ: IEEE Press.
AND THE 3-W RULE
4.12: GUARD/SHUNT TRACES
4.13: TRACE TERMINATION
[2] Kaupp, H. R. 1967, April. "Characteristics of Microstrip Transmission
REFERENCES Lines: IEEE Transactions." Vol. EC-16, No. 2.
[10] Johnson, H. W., and M. Graham. 1993. High Speed Digital Design.
Englewood Cliffs, NJ: Prentice Hall.
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Table of Contents
Chapter 5 - Interconnects and I/O
Chapter 5
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
5.1: PARTITIONING
by Mark I. Montrose
5.2: ISOLATION AND
PARTITIONING (MOATING) IEEE Press 2000
5.3: FILTERING AND
GROUNDING
5.4: LOCAL AREA NETWORK Recommend this title?
I/O LAYOUT
5.5: VIDEO
5.6: AUDIO
REFERENCES
Power plane switching noise coupling into I/O circuits and cables.
Lack of data line filtering on signal traces (both common mode and
differential mode).
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Table of Contents
Chapter 5 - Interconnects and I/O
Chapter 5
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
5.1: PARTITIONING by Mark I. Montrose
5.1.1: Functional
Subsystems IEEE Press 2000
5.1.2: Quiet Areas
5.1.3: Internal Radiated
Noise Coupling Recommend this title?
5.2: ISOLATION AND
PARTITIONING (MOATING)
5.3: FILTERING AND
GROUNDING
5.4: LOCAL AREA NETWORK
I/O LAYOUT
5.5: VIDEO
5.6: AUDIO
5.1 PARTITIONING
REFERENCES
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Table of Contents
Chapter 5 - Interconnects and I/O
Chapter 5
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
5.1: PARTITIONING
by Mark I. Montrose
5.2: ISOLATION AND
PARTITIONING IEEE Press 2000
(MOATING)
5.2.1: Method 1: Moating Recommend this title?
5.2.2: Method 2: Bridging in
a MoatPartitioning
5.3: FILTERING AND
GROUNDING
5.4: LOCAL AREA NETWORK
I/O LAYOUT
5.5: VIDEO
5.6: AUDIO
REFERENCES 5.2 ISOLATION AND PARTITIONING (MOATING)
Isolation and partitioning refer to the physical separation of components,
circuits, and planes from other functional devices, areas, and subsystems.
Allowing RF currents to propagate to different parts of the board by
radiated or conductive means can cause problems not only in terms of
EMI, but also functionality.
CMOS and bipolar digital components create large transient current flow
under three conditions:
1. Current flows directly from power to ground (internal power
absorption).
2. Current flows from the power pin, through the chip, to the output pin
(driving high, sourcing current to the loads).
3. Current flows into the output pin, through the chip, to its internal
ground pin (driving low, sinking current from the loads).
The current flow pattern for item (1), for most small-scale (SSI) and
medium-scale (MSI) integrated components, is by far the smallest of the
three transient current conditions.
For situations (2) and (3), the chip creates large transient current loops that
involve output pins, external loads, and the power and ground planes
surrounding the chip. For example, suppose the chip is connected to a
long, 50-ohm trace, and further suppose that the trace is routed on a layer
adjacent to a reference plane. When the driver forces current into and out
of that trace, an equal and opposite current flows on the reference plane,
directly underneath the trace. This reaction current (or returning signal
current) reenters the driver through either the power or the ground pin,
depending on whether the driver is switching high or low, respectively.
2. Isolate all plane layers along this partition line with absence of copper
between regions. This absence of copper area is identified as a moat.
3. For power and ground planes, use a 0.010 in. (0.25 mm) minimum
wide moat.
4. Tie analog ground and digital ground at one and only one point. This
section of the ground plane will be the "bridge" that goes across the
moat.
7. Ensure that any signals that must pass between the analog and
digital sections travel only through the bridge, and do so on a layer
adjacent to the bridge (maintain RF return current path).
8. Provide filters for analog power and phase lock loop circuits. This filter
provides a digital noise-free analog power source.
There are two areas of concern for selecting components used in I/O
circuits for isolation purposes:
1. Proper bandwidth filtering.
There is an absence of copper area between the data line filter (DLF) and
the I/O connector. This is a design technique not easily recognized. The
concern for RF return current to have a return path physically adjacent to
the signal line can be waived for this application. Common-mode RF
energy is removed from the interface by the filter, preventing radiated RF
energy from getting onto the cable. The cable interconnect provides a
discontinuity in the return path, in addition to the fact that many cables
provided by users are unshielded.
The DLF prevents RF energy from leaving the unit. What is not observed is
what happens when an externally induced event occurs, such as ESD,
conducted susceptibility, or an electrically fast transient burst. Externally
induced energy is injected onto the signal cable. The cable brings the
energy into the PCB. If an image plane is provided between the DLF and
I/O interconnect, radiated coupling of high-energy levels of crosstalk may
develop between signal lines and the plane. The plane will then recouple
this energy to the input of the DLF, thus defeating its purpose and use. The
item to remember is to keep undesired energy from coupling between
filtered and unfiltered circuits. Mixing two circuits, at different potential
levels, will result in serious functionality problems or permanent damage
owing to component failure. This is useful only for a differential/balanced
interface/line.
Sometimes only the power plane must be isolated and the ground plane
connected through the bridge. This technique is common for circuits where
a common ground plane is needed, or separately filtered and regulated
power is required. In this case, a ferrite bead is needed to bridge the moat
for filtered power only. If analog or digital power is not required in an
isolated area, this unused power plane can be redefined as a second
ground plane, referenced to the main ground plane by vias within the
isolated area.
When using bridging Method 2, both ends of the bridge should be bonded
to chassis, or frame ground. This is highly recommended if multipoint
grounding is provided in the chassis and system-level design. Grounding
the entrances to the bridge performs two functions:
1. Grounding removes high-frequency common-mode RF components in
the ground planes (ground-noise voltage) from coupling into the
partitioned area.
Figure 5.5 illustrates how traces are to be routed when using digital and
analog partitions. Because power plane switching noise may be injected
into the analog section from digital components, isolation and/or filtering is
required, especially on the power plane. All traces that travel from the
digital to analog section must be routed through a bridge. For analog
power, a ferrite bead must be used to cross the moat. A voltage regulator
may also be required. The analog power moat is usually 100% complete
around the entire partition. Certain analog components will want analog
ground to be referenced to digital ground, but only through a bridge,
detailed in Fig. 5.5. Many analog-to-digital and digital-to-analog devices
connect the "AGNDS" and "DGNDS" (indicated on the pin designation)
together in the device lead frame. When such is the application of a
partition, with one ground reference, digital signal currents will not return
efficiently to their source, causing noise and EMI. AGNDS and DGNDS
should be moated away from each other only when the circuit devices
themselves provide AGND to DGND isolation.
Figure 5.5: Digital and analog partitioning.
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Table of Contents
Chapter 5 - Interconnects and I/O
Chapter 5
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
5.1: PARTITIONING
by Mark I. Montrose
5.2: ISOLATION AND
PARTITIONING (MOATING) IEEE Press 2000
5.3: FILTERING AND
GROUNDING
Recommend this title?
5.3.1: Filtering
5.3.2: Why I/O Cables and
Interconnects Radiate
5.3.3: Grounding (I/O
Connector)
5.4: LOCAL AREA NETWORK
I/O LAYOUT
5.5: VIDEO
5.6: AUDIO
REFERENCES
5.3.1 Filtering
Two types of filter configurations exist, capacitive and inductive (or their
combinations). Different applications require one, the other, or both. Every
I/O trace requires filtering, with exceptions permitted such as fiber optic
and certain types of local area networks and telecommunication interfaces.
Filter components will not be effective unless their placement is exactly
adjacent to their entry point. One inch (2.54 cm) may be too far away.
Capacitive bypass filtering is required to remove high-frequency RF
currents on external I/O cable shields, in addition to inductive filtering for
differential-mode RF current from logic devices and I/O interconnects.
In the case of an ESD event, voltage and current levels received may be
extremely large in amplitude. International test specifications mandate a
minimum voltage level for performance reasons. Surface mount capacitors
used for RF emissions are usually rated 25 volts or less. Most capacitors
will not only survive the ESD event, but will also protect the circuit from it.
Transient surge protection devices are not always needed. Should an ESD
event enter an I/O line, these capacitors may self-destruct. When this
condition occurs, capacitive filtering for I/O lines no longer exist. This now
leaves the unit noncompliant for both RF emissions and immunity
purposes.
To calculate the value of this bypass capacitor for use with an inductor, Eq.
(5.1) is provided. A data line filter provides high-frequency attenuation of
RF energy on signal lines but does not provide inductance that is part of a
tuned filter equation.
(5.1)
Get MathML
When data line filters are used to bridge two areas, common-mode current
is removed from the trace. Selection of the correct material type of data line
filter is important because the ferrite material and construction operate at
optimal performance within a specific range of frequencies (explained in
Chapter 8). One manufacturer's filter or ferrite material may provide 30
ohms of impedance at 30 MHz and 300 ohms at 100 MHz. Another
vendor's product (100% form, fit, function but with a different permeability
value) may provide 15-ohm impedance at 30 MHz and 1000 ohms at 100
MHz. It should be verified before use that the permeability and composition
of the ferrite material chosen is compatible with the intended range of
frequencies to be suppressed. Vendor data sheets discuss this matter in
detail.
Trace lengths between control logic and the I/O connector must be as
physically short as possible. Filter components must always be located
directly at the I/O connector and nowhere else. The same layout design
techniques must be used for I/O signal traces as one would use for clock
signals (discussed in Chapter 4).
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Table of Contents
Chapter 5 - Interconnects and I/O
Chapter 5
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
5.1: PARTITIONING
by Mark I. Montrose
5.2: ISOLATION AND
PARTITIONING (MOATING) IEEE Press 2000
5.3: FILTERING AND
GROUNDING
5.4: LOCAL AREA Recommend this title?
NETWORK I/O LAYOUT
5.5: VIDEO
5.6: AUDIO
REFERENCES
The recommended layout topology shown in Figs. 5.9 through 5.12 has
been proven to allow compliance with International Class B emission
requirements. Proper design of the interface is not the total solution for
electromagnetic interference compliance. All other areas discussed in this
book are still required, especially trace routing, proper selection of
components and their placement, correct I/O isolation and filtering, optimal
decoupling, and other design and layout techniques.
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Table of Contents
Chapter 5 - Interconnects and I/O
Chapter 5
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
5.1: PARTITIONING
by Mark I. Montrose
5.2: ISOLATION AND
PARTITIONING (MOATING) IEEE Press 2000
5.3: FILTERING AND
GROUNDING
5.4: LOCAL AREA NETWORK Recommend this title?
I/O LAYOUT
5.5: VIDEO
5.6: AUDIO
REFERENCES
5.5 VIDEO
Printed circuit boards with video require careful attention to impedance
control, filtering, and grounding. For analog monitors, the slowest slew rate
signal possible from the video generator is required. A passive filter must
be installed between the video generator and I/O connector. Locate the
filter immediately adjacent to the connector with minimal lead inductance.
Manufacturers of video controllers generally prescribe a recommended
way to layout the design, including selection of discrete components. For
analog monitors, maintain constant trace impedance of the three RGB
signals (red, green, and blue), along with both horizontal and vertical sync
traces. These layout requirements prevent reflections from being
developed owing to a potential transmission line impedance mismatch in
the system and interconnect cable.
If the vendor ties analog ground to digital ground internal to the device
package and instructs the user to tie analog ground to the digital partition
externally, then why has the vendor allocated the pin name as AGND? In
reality, only one ground structure exists. The moat for the analog section
needs to be routed to those components using filtered "analog" power. "All"
video traces must be routed within the analog section, and their respective
RF return currents must remain in analog, not digital. If the analog traces
are routed over a digital plane, digital switching noise may couple to the
analog traces (crosstalk), causing signal integrity concerns.
One must not violate or cross the moat with the placement of "any"
component or trace that physically resides exclusively in either the digital
or analog section. Use of the 20-H rule assists in implementing this
technique. It is recommended that the surrounding planes be at ground
reference rather than voltage to minimize crosstalk between traces. This is
shown in Fig. 5.14 for a multilayer stackup. For two-sided boards, the same
guidelines apply but with extra attention given to component placement
and trace routing to prevent coupling noise between analog and digital
sections. The discrete video filter components must always be located
adjacent to the I/O connector, with minimal trace length routing possible.
Certain analog monitors use a coax from the I/O connector to the monitor.
The braid, or shield, of the coax is not an RF shield but a video signal
return path. This braid (shield) therefore cannot be RF bonded to chassis
ground; rather it must be connected directly to the video return logic.
Provision must always be made for an AC shunt using a bypass capacitor
between the braid (shield) of the coax and system chassis ground. The
shunt capacitor removes RF currents that may exist on the coax shield
without affecting the signal integrity of the transmitted signal.
RF energy on a braid travels on the basis of skin effect. The inside portion
of the braid carries the video return signal, whereas the outside portion of
the braid carries RF energy. Because of the propagation mode of the
electromagnetic wave within a transmission line, both RF and low-
frequency energy will be present simultaneously. For this reason, the
bypass capacitor is effective in removing unwanted high-frequency RF
energy, while letting the desired low-frequency DC signal to pass
undisturbed.
For PCBs with digital mode video interface, data line filters, or their
equivalent, must be used only on high-threat signals. Constant trace
impedance is mandatory at all times, taking into consideration layer
jumping. The output portion of the video generator to the I/O connector
must be located in an isolated (quiet) area (discussed earlier). RF ground
(bond) the metal I/O connector and cable shield directly to chassis ground
immediately at the exit point, if the cable braid (shield) is not used as signal
return. If the I/O connector contains video return, then design requirements
mandate isolation. Under this condition, a bypass capacitor is required to
divert RF energy on the braid to chassis ground. Externally induced RF
energy is not to be allowed to corrupt the video circuitry once it enters the
system.
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Table of Contents
Chapter 5 - Interconnects and I/O
Chapter 5
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
5.1: PARTITIONING
by Mark I. Montrose
5.2: ISOLATION AND
PARTITIONING (MOATING) IEEE Press 2000
5.3: FILTERING AND
GROUNDING
5.4: LOCAL AREA NETWORK Recommend this title?
I/O LAYOUT
5.5: VIDEO
5.6: AUDIO
REFERENCES
5.6 AUDIO
Printed circuit boards with audio generally require three separate
partitioned areas: digital, analog, and audio. This multilevel partitioning is
applicable only for a four- or more layer stackup, and it is impossible for
two-layer assemblies. Most two-layer PCBs do not implement moats, for it
is impossible to use split plane technology when solid reference planes do
not, and cannot, exist.
The analog section must be isolated from the digital area using a bridge or
moat. An example of this multilevel partitioning is shown in Fig. 5.15. The
concept used for partitioning analog and digital is similar to a video layout,
discussed in the previous section.
When designing a moat structure for analog power and ground, route
traces between the digital and analog section in the area immediately
adjacent, or under the audio controller, using a ferrite bead between
analog/digital power and ground. If a common ground plane is used for
both analog and digital components, only the power plane needs to be
moated (isolated). The 20-H rule should be used only on the analog power
plane (Fig. 5.15).
All interconnect traces not associated with the audio controller must
traverse through a bridge located directly under the audio controller and
physically adjacent to a solid reference (image) plane. Violation of any
trace over the moat, not traveling through the bridge, separating the analog
to digital partition, will allow digital switching noise, white noise, and other
electrical disturbance to be injected from the digital section into the analog
section. White noise is random noise that has a constant energy per unit
bandwidth throughout the frequency spectrum. Power supply and system
noise is usually heard as a 50/60 cycle hum and is not classified as white
noise.
The audio interface must be treated differently from both the digital logic
and analog control section. To prevent chassis switching noise from
coupling to the audio I/O cables, complete isolation of the digital power
and ground planes is mandatory. An audio cable usually consists of a
two-wire pair: signal and return for each channel. If this type of two-wire
cabling is used, the audio I/O interface connector must be isolated from the
rest of the PCB using a moat.
Analog traces and components must be located within the isolated analog
section. This placement prevents coupling between the digital section to
analog. This partitioning is illustrated by a "dead zone" on Layer 3 in Fig.
5.15. Use of the 20-H rule may also be required in the analog section of the
PCB. It is preferred that the surrounding reference planes be at ground
potential rather than power in order to minimize crosstalk or digital
switching noise that may exist within the planes.
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Table of Contents
Chapter 5 - Interconnects and I/O
Chapter 5
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
5.1: PARTITIONING
by Mark I. Montrose
5.2: ISOLATION AND
PARTITIONING (MOATING) IEEE Press 2000
5.3: FILTERING AND
GROUNDING
5.4: LOCAL AREA NETWORK Recommend this title?
I/O LAYOUT
5.5: VIDEO
5.6: AUDIO
REFERENCES
REFERENCES
[1] Montrose, Mark I. 1999. EMC and the Printed Circuit BoardDesign,
Theory and Layout Made Simple, Piscataway, NJ: IEEE Press.
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Table of Contents
Chapter 6 - Electrostatic Discharge Protection
Chapter 6
6.1: INTRODUCTION Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
6.2: TRIBOELECTRIC SERIES
by Mark I. Montrose
6.3: FAILURE MODES FROM
AN ESD EVENT IEEE Press 2000
6.4: DESIGN TECHNIQUES
FOR ESD PROTECTION
6.5: GUARD BAND Recommend this title?
IMPLEMENTATION
REFERENCES
In addition to current levels, ESD rise time is also important. ESD is a very
fast transient. Two parameters are of great concern: peak level of current
and rate of change (dI/dt). In the EMI world, rise times are equated to a
frequency spectral distribution based on the Fourier transform, which
relates time domain signals (edge rates) to frequency domain components,
as explained by Eq. (6.1):
(6.1)
Get MathML
where f is frequency in hertz, and t = edge rate transition time. Given this
r
discussion, a typical 1 ns rise time exhibits a spectrum of over 300 MHz.
As a result, immunity design and layout techniques are required, similar to
those used to minimize EMI energy.
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Table of Contents
Chapter 6 - Electrostatic Discharge Protection
Chapter 6
6.1: INTRODUCTION Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
6.2: TRIBOELECTRIC by Mark I. Montrose
SERIES
6.3: FAILURE MODES FROM IEEE Press 2000
AN ESD EVENT
6.4: DESIGN TECHNIQUES
FOR ESD PROTECTION Recommend this title?
6.5: GUARD BAND
IMPLEMENTATION
REFERENCES
POSITIVE CHARGE
1. Air 19. Sealing wax
2. Human skin 20. Hard rubber
3. Asbestos 21. Mylar
4. Rabbit fur 22. Epoxy glass
5. Glass 23. Nickel, copper
6. Human hair 24. Brass, silver
7. Mica 25. Gold, platinum
8. Nylon 26. Polystyrene foam
9. Wool 27. Acrylic rayon
10. Fur 28. Orlon
11. Lead 29. Polyester
12. Silk 30. Celluloid
13. Aluminum 31. Polyurethane foam
14. Paper 32. Polyethylene
15. Cotton 33. Polypropylene
16. Wood 34. PVC (vinyl)
17. Steel 35. Silicon
18. Amber 36. Teflon
NEGATIVE CHARGE
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Table of Contents
Chapter 6 - Electrostatic Discharge Protection
Chapter 6
6.1: INTRODUCTION Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
6.2: TRIBOELECTRIC SERIES
by Mark I. Montrose
6.3: FAILURE MODES
FROM AN ESD EVENT IEEE Press 2000
6.4: DESIGN TECHNIQUES
FOR ESD PROTECTION
Recommend this title?
6.5: GUARD BAND
IMPLEMENTATION
REFERENCES
There are four basic failure modes from ESD-related events to PCBs [1, 3].
The first three are shown in Fig. 6.1.
With a 1-ns rise time for an ESD event, ground impedance may not
be low. Hence, the ground will "bounce." The usual result is an upset.
Ground bounce, or level shifting of the 0V-reference, can drive CMOS
circuits into latchup. Latchup is a situation where the ESD doesn't
actually do the damageit just sets things up so that the power
supply can destroy the part or, at best, the circuit becomes
nonfunctional without a power cycle reset.
Because ESD is transient in nature, fast digital circuits are more prone to
ESD upsets than slow analog or, for that matter, low-bandwidth digital
device circuits. In fact, ESD rarely upsets the functionality of analog
circuits. However, both analog and digital circuits are vulnerable to ESD
damage from a direct discharge. Digital circuits with edge rates faster than
3 ns are particularly vulnerable because phantom ESD pulses can fool
them. As a result, digital circuits are more vulnerable than older circuits
with slower edge rates.
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Table of Contents
Chapter 6 - Electrostatic Discharge Protection
Chapter 6
6.1: INTRODUCTION Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
6.2: TRIBOELECTRIC SERIES
by Mark I. Montrose
6.3: FAILURE MODES FROM
AN ESD EVENT IEEE Press 2000
6.4: DESIGN
TECHNIQUES FOR ESD
Recommend this title?
PROTECTION
6.4.1: Single- and Double-
Sided PCBs
6.4.2: Multilayer PCBs
6.5: GUARD BAND
IMPLEMENTATION
REFERENCES
Although the majority of direct ESD problems are cable related, any place
where humans can come into contact with the circuit or system may cause
disruption. The solution is straightforwardprotect all lines, including
signal, power, and ground path. The objective is to prevent ESD current
from entering the PCB with a high series impedance such as a resistor,
ferrite bead, or capacitive filters. Another technique is to provide a low-
impedance path to ground. The problem with a low-impedance path to
ground is that we have now set up a ground bounce situation. On a
multilayer board, with a ground plane, the ground impedance is usually low
enough that ground bounce is not a major concern.
When field coupling of a discharge occurs, with respect to an I/O cable, the
noise transient coupled into the system is common-mode. This means that
the coupled energy is applied to all cables or interconnects at the same
time and with the same polarity. A ferrite core rejects common-mode
energy when placed over the cable assembly. This ferrite core rejects
common-mode noise while passing the differential-mode signal of interest.
A disadvantage of using ferrite cores is the physical size of the device,
along with cost.
1. Route power and ground traces adjacent to each other with minimal
distance spacing between the two.
The pointed tips are separated by a maximum of 0.010 in. (0.25 mm)
and a minimum of 0.006 in. (0.15 mm). One triangle is connected to
the ground plane, while the other triangle is part of the signal trace.
These triangle spark gaps must be placed only on the outer layer of
the PCB, with no soldermask. A soldermask provides a dielectric
insulator (barrier) that prevents ESD energy from jumping between
the two triangles. The only signals, or I/O connections exempt from
use of spark gaps, are those mandated by regulatory safety agencies
to pass dielectric withstand tests (hipotting). Implementation of a
spark gap is shown in Fig. 6.5. Hermetically sealed spark gaps,
available as a component, are generally too slow in responding to an
ESD event. Thus, they provide only minimal effectiveness for the
intended application and are more suited to transient surge protection
in power supplies connected to an AC mains source.
Circuit Layout
1. Use a multilayer stackup. Multilayer PCBs are superior to single- and
double-sided assemblies because a stable ground layer is available.
ESD must never be allowed onto the surface of a double-sided
assembly. Once ESD enters a double-sided board, it becomes
practically impossible to cope with the ESD event. If a double-sided
PCB must be used, provide a separate ground layer, shield, or fill on
the top and bottom of the board. This allows for termination of filter
elements, if provided, and permits the ESD event to find a lower
impedance path to ground, away from components.
4. Minimize loop areas. Identify areas where loop currents can exist.
This includes the distance spacing between components, I/O
connectors, and component/power planes. Keep in mind that loop
areas include both signal (RF return path) and power distribution.
6. Fill in both the top and bottom layers of the PCB with as much copper
at ground potential (ground fill) as possible. This localized fill
minimizes ESD effects by providing a low-impedance path to chassis
or system ground. A large metal plane, or copper fill, has a lower
impedance value compared to a ground trace. This low-impedance
ground fill conducts a high-energy pulse to ground, rather than
allowing the energy to corrupt or enter signal lines or components.
One disadvantage of using fill areas at ground potential is that an
ESD pulse could be discharged into the ground system, causing
potential damage to components through ground bounce. Ground
bounce can cause devices to become nonfunctional, along with
injecting system glitches into the operation of the device. If ground fill
is provided on the outer layers of the PCB, connect the fill to the
ground plane or chassis ground at frequent interval spacing not signal
return ground.
11. Keep signal lines as close as possible to ground lines, ground planes,
and circuits. This is illustrated in Fig. 6.6 when single- and double-
sided boards are used. Do not route critical signals near the edge of
the PCB.
System-Level Protection
1. Provide a complete shield around components and circuits
susceptible to radiated ESD corruption. Bond the shield to chassis
ground at multiple points, providing a low-impedance path for the ESD
currents absorbed by the shield. If shielding is impractical, consider
effective insulation. This insulation would work just as effectively for
"direct discharge," not for radiated coupling of ESD.
2. Route internal cables away from slots and openings. These openings
can couple radiated energy into cables or interconnects, which then
transfer this energy to circuits through conduction.
5. When membrane keypads for user control are provided, recess the
conductive layer of the membrane to eliminate direct discharge to
digital circuits. This is applicable primarily if the surface of the
enclosure is nonconductive. Benefits will result even if the rest of the
plastic cover is conductive.
8. Avoid pigtails. Pigtails present problems for both EMI and ESD. In
addition to being a radiator of RF energy, ESD sees a loop antenna,
which by virtue of typical dimensions is tuned to a particular
frequency, generally the same one as the ESD event. The frequency
of an ESD pulse is approximately 300 MHz (1-ns edge transition).
Pigtail termination is not adequate, unless the pigtail is very short and
as fat (wide) as possible. Keep the pigtail, if used, far away from
signal or I/O cables. Do not terminate the shield of the enclosure
directly to the PCB's ground structureuse chassis ground.
[1]
Tranzorb is a trademark of General Semiconductor.
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Table of Contents
Chapter 6 - Electrostatic Discharge Protection
Chapter 6
6.1: INTRODUCTION Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
6.2: TRIBOELECTRIC SERIES
by Mark I. Montrose
6.3: FAILURE MODES FROM
AN ESD EVENT IEEE Press 2000
6.4: DESIGN TECHNIQUES
FOR ESD PROTECTION
6.5: GUARD BAND Recommend this title?
IMPLEMENTATION
REFERENCES
The topside band is connected to the bottom-side band by vias every 1/2
in. (1.3 cm) around the entire periphery. Vias ensure that the bands are
securely bonded to each other. A solid bond connection allows for a
maximum amount of ESD energy to travel between the two bands, using
the lowest impedance path available. When a guard band is provided,
soldermask or conformal coating must not be provided to the band. Use of
soldermask or conformal coating provides a dielectric barrier between the
energy source and guard band. Depending on the dielectric constant and
thickness of the coating, ESD energy may find an alternate, lower
impedance path to ground, which is what we do not want. This alternate,
lower impedance path to ground could develop as a radiated or conducted
field, causing harmful results to components and devices or to the entire
system.
Now comes the questiondo we, or do we not, connect the guard band to
the ground planes, if a ground plane is provided?
1. Connection of the guard band to the ground plane. The band is
connected to the ground planes if the PCB is installed in a metal
enclosure using a multipoint ground connection to the metal chassis.
The metal chassis must also be connected to the third-wire ground,
commonly identified as Protector Earth (PE). The ground between the
PCB and chassis must be of a low-impedance type, securely bonded.
The purpose of connecting the guard band to the ground plane for
this application is to allow the ESD energy to have a very low-
impedance path to a large metal enclosure at ground potential. If a
low-impedance bond is provided, the ground plane should not
bounce, synchronous with the ESD event. Bouncing of the ground
plane can cause destruction or malfunction of digital components. The
ESD energy is essentially drained out of the system.
If a moat is used on the PCB traversing to the edge of the board, the guard
band must be broken at the partition break. This break in the guard band
will not degrade EMI or ESD performance (Fig. 6.7).
If the distance spacing between the break in the guard band is less than
0.020 in. (0.5 mm), parasitic capacitance can exist between the two band
segments. This parasitic capacitance is capable of allowing RF energy to
bridge across the gap, causing potential susceptibility problems related to
both EMI and ESD, with the existence of a loop antenna.
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Table of Contents
Chapter 6 - Electrostatic Discharge Protection
Chapter 6
6.1: INTRODUCTION Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
6.2: TRIBOELECTRIC SERIES
by Mark I. Montrose
6.3: FAILURE MODES FROM
AN ESD EVENT IEEE Press 2000
6.4: DESIGN TECHNIQUES
FOR ESD PROTECTION
6.5: GUARD BAND Recommend this title?
IMPLEMENTATION
REFERENCES
REFERENCES
[1] Montrose, M. 1999. EMC and the Printed Circuit BoardDesign,
Theory and Layout Made Simple. Piscataway, NJ: IEEE Press.
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Table of Contents
Chapter 7 - Backplanes, Ribbon Cables, and Daughter Cards
Chapter 7
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
7.1: BASICS
by Mark I. Montrose
7.2: CONNECTOR PINOUT
ASSIGNMENT IEEE Press 2000
7.3: AC CHASSIS PLANES
7.4: BACKPLANE Recommend this title?
CONSTRUCTION
7.5: INTERCONNECTS
7.6: MECHANICAL
7.7: SIGNAL ROUTING
7.8: TRACE LENGTH/SIGNAL
TERMINATION
7.9: CROSSTALK
7.10: GROUND LOOP
CONTROL
Chapter 7: Backplanes, Ribbon Cables,
7.11: GROUND SLOTS IN
BACKPLANES
REFERENCES
and Daughter Cards
OVERVIEW
This chapter provides an overview of PCB layout techniques for
backplanes, ribbon cable assemblies, and daughter cards. Among the
concerns that arise when designing interconnects are impedance of the
trace routes, purity of the power distribution system, construction of the
assembly, trace termination, signal routing topology, crosstalk, and trace
length. All design rules and techniques applicable to PCB layout presented
in earlier chapters also apply to backplanes, ribbon cables, daughter cards,
and motherboards with adapter slots.
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Table of Contents
Chapter 7 - Backplanes, Ribbon Cables, and Daughter Cards
Chapter 7
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
7.1: BASICS by Mark I. Montrose
7.2: CONNECTOR PINOUT
ASSIGNMENT IEEE Press 2000
7.3: AC CHASSIS PLANES
7.4: BACKPLANE Recommend this title?
CONSTRUCTION
7.5: INTERCONNECTS
7.6: MECHANICAL
7.7: SIGNAL ROUTING
7.8: TRACE LENGTH/SIGNAL
TERMINATION
7.9: CROSSTALK
7.10: GROUND LOOP
7.1 BASICS
CONTROL
7.11: GROUND SLOTS IN
BACKPLANES Before designing an interconnect, one must first determine the connector
REFERENCES
pin assignment. Assigning connector pinout at this stage helps prevent
crosstalk, maintains impedance, reduces radiated emissions, and provides
for enhanced signal quality performance while maintaining proper ground
loop control for EMI compliance. An interconnect is essentially the freeway
of signal flow between interface circuits and adapter cards or backplanes.
As such, care must be taken to ensure optimal performance at all times.
Because backplanes have large via holes, where the trace enters at the
connector location, a decrease in impedance is observed every time a PCB
is inserted. Typically, trace impedance (Z ) is 45 to 70 . Large-size vias
o
in the backplane can drop overall trace impedance significantly. With lower
trace impedance, more current is required, according to Ohm's law. An
increase in drive current allows additional RF energy to exist. This RF
current can then couple to other circuits, subsystems, or free space. The
greater the number of board plugs into a backplane, the lower the
impedance. The impedance change can easily approach 30 to 40 ohms.
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Table of Contents
Chapter 7 - Backplanes, Ribbon Cables, and Daughter Cards
Chapter 7
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
7.1: BASICS
by Mark I. Montrose
7.2: CONNECTOR PINOUT
ASSIGNMENT IEEE Press 2000
7.3: AC CHASSIS PLANES
7.4: BACKPLANE Recommend this title?
CONSTRUCTION
7.5: INTERCONNECTS
7.6: MECHANICAL
7.7: SIGNAL ROUTING
7.8: TRACE LENGTH/SIGNAL
TERMINATION
7.9: CROSSTALK
7.10: GROUND LOOP
7.2 CONNECTOR PINOUT ASSIGNMENT
CONTROL
7.11: GROUND SLOTS IN
BACKPLANES The major source of RF energy developed in a system is generated from
REFERENCES
the physical connection between a backplane and motherboard or between
a motherboard and daughter card. An imbalance in differential-mode wave
propagation is one method of developing common-mode energy, which
then causes EMI concerns. This interconnect is performed by either cables
or connectors. Differential-mode RF current is developed by many sources.
EMC compliance is generally neglected when backplanes, ribbon cables,
daughter cards, and interconnect pinout assignment are designed or
specified.
When ground pins are assigned throughout the entire length of the
connector, ground loop areas must be minimized to prevent high-amplitude
levels of RF currents from being coupled to other components or
subsystems. Loop control on the PCB can be maintained using a multilayer
stackup, with both 0V-reference and alternating ground pins between clock
and signal lines on the interface connector. An example is shown in Fig.
7.1.
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Table of Contents
Chapter 7 - Backplanes, Ribbon Cables, and Daughter Cards
Chapter 7
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
7.1: BASICS
by Mark I. Montrose
7.2: CONNECTOR PINOUT
ASSIGNMENT IEEE Press 2000
7.3: AC CHASSIS PLANES
7.4: BACKPLANE Recommend this title?
CONSTRUCTION
7.5: INTERCONNECTS
7.6: MECHANICAL
7.7: SIGNAL ROUTING
7.8: TRACE LENGTH/SIGNAL
TERMINATION
7.9: CROSSTALK
7.10: GROUND LOOP
7.3 AC CHASSIS PLANES
CONTROL
7.11: GROUND SLOTS IN
BACKPLANES Some applications require use of an AC chassis plane in addition to 0V-
REFERENCES
reference planes. This AC chassis plane has no direct connection to other
reference planes, except through bypass capacitors (usually 0.1 F). The
AC chassis plane must, however, be physically located directly next to a
0V-reference plane, providing very tight capacitive coupling between the
two, thus minimizing use of discrete capacitors. At high frequencies, these
planes are effectively tied together because of interplanar capacitance
between the two. The AC plane always connects to a metal chassis along
a continuous axis. At high frequencies, we have shorted the digital 0V-
reference plane to chassis. This coupling reduces the amount of digital
ground noise at that point, sending it into the chassis, also reducing signal
noise transmitted by the source driver to the outside world.
When using an AC chassis plane, the digital logic return plane must be
electrically isolated at low frequencies from chassis potential. This isolation
may also be desirable for safety or other reasons. If isolation is not
important, the AC chassis and 0V-reference planes may be shorted
together.
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Table of Contents
Chapter 7 - Backplanes, Ribbon Cables, and Daughter Cards
Chapter 7
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
7.1: BASICS
by Mark I. Montrose
7.2: CONNECTOR PINOUT
ASSIGNMENT IEEE Press 2000
7.3: AC CHASSIS PLANES
7.4: BACKPLANE Recommend this title?
CONSTRUCTION
7.4.1: Number of Layers
7.4.2: Number of Connector
Slots
7.5: INTERCONNECTS
7.6: MECHANICAL
7.7: SIGNAL ROUTING
7.8: TRACE LENGTH/SIGNAL
TERMINATION
7.4 BACKPLANE CONSTRUCTION
7.9: CROSSTALK
7.10: GROUND LOOP
CONTROL
There are basic concerns related to daughter cards, ribbon cables,
7.11: GROUND SLOTS IN
BACKPLANES
interconnects, and plug-in modules when defining overall construction and
REFERENCES configuration. These concerns are in addition to the information presented
throughout this book. Consideration must be made to determine if routing
on the outer layers of the assembly (microstrip) or inner layers (stripline) is
to be performed. Generally, a plug-in module is positioned at a 90, or
orthogonal angle to the main board (e.g., adapter boards for personal
computers) or card cage assemblies where the modules are plugged into a
backplane.
POWER PLANE PURITY. Switching noise from the power supply, radiated
or conductive coupling of RF currents, voltage drop (IR), and ground
bounce affects the purity of the voltage distribution system provided for all
components and adapter cards.
Contamination of the power and ground plane is possible, which affects the
performance of sensitive components, especially analog or PLL circuits.
This contamination may be caused by switching noise from a power
supply, externally induced RF fields, ESD, electrical overstress (EOS)
events, I/O cables and interconnects, peripherals with motors, and
magnetic components injecting inductive switching noise into the power
distribution system (disk drives). Contamination of low-voltage sensitive
circuits may also cause functional degradation to occur.
Voltage drop may occur when multiple boards are inserted into a
backplane slot, with one board consuming more power than another lower-
power-consuming board inserted at the opposite end of the assembly. This
IR drop between boards may affect functionality and signal integrity.
For those applications where a solid ground plane is not possible on the
bottom layer of a board and coupling of RF energy occurs from an adjacent
board, use of a metal shield partition may be required. This partition
prevents interboard coupling. It is imperative that this shield partition be
securely fastened to the PCB in as many locations as possible, which
minimizes the physical dimension of a loop antenna that may exist
between circuits and functional subsections on that particular board.
Proper referencing of the backplane to the card cage takes the form of
establishing a very low-impedance RF reference between the backplane
and card cage. This reference method is mandatory to short out eddy
currents developed at and by the daughter cards. These currents are
coupled to the card cage assembly through a distributive transfer
impedance, often in the low tens of ohms. This transfer impedance will
allow RF energy to attempt to close the loop by coupling to the backplane.
If the common-mode reference impedance between the backplane and
card cage is not significantly lower than the distributive "driving source" (of
the eddy currents), an RF voltage potential will be developed between the
backplane and the card cage. This voltage will have the spectral energy
signature not only of the backplane, but of all daughter cards as well. This
voltage will cause any conductors that are connected to the backplane to
radiate the spectral profile of the entire assemblyeven DC wire. The
spectral voltage developed by this mechanism will even contribute to
interboard coupling using the backplane to card cage relationship as an
intermediary.
Simply put, the common-mode spectral potential between the backplane
and card cage must be shorted out. This may take the form of frequently
connecting the backplane's 0V-reference plane to the card cage (chassis)
at regular intervals around the perimeter of the assembly. Alternatively, a
chassis plane can be used, positioned immediately adjacent to a ground
plane. This chassis plane also serves as a "Faraday partition" within the
backplane assembly. The location of a chassis plane on the outer layers
must be designed such that it is never used as a return reference for signal
traces or as an RF return path. Generally, to be reasonably effective, the
RF transfer impedance between the logic ground plane and the chassis
plane must be equal to, or less than, 1-, thereby shorting out common-
mode potential between the daughter card and backplane. This transfer
impedance occurs through capacitive coupling between the two planes.
For this application to work, the outer two layers must be at chassis
potential, with the next two layers inward at ground potential.
The reader is cautioned that the best EMI and system performance will be
gained when signal impedances on the routing layers are well controlled
and preferably referenced to the ground planes rather than voltage planes.
The intrinsic parallel-plane power impedance distribution established must
be as low a value as is reasonably possible. To conform to these goals for
a backplane having two or more signal routing layers, multiple slot
positions and signal edge rates faster than approximately 5 ns cannot be
efficiently implemented on a simple four-layer assembly. More layers are
required.
If the top and bottom layers of the backplane, or daughter card, are a solid
plane at ground potential, a lower impedance connection to chassis ground
becomes available to both the backplane connector and faceplate screw
securement. This low-impedance connector will now source RF currents to
chassis ground, thus preventing ground loops L1 and L3 from existing
between the faceplate to board and backplane to board, respectively. With
solid bonding of the mounting plate to various locations on the PCB,
ground loops L2 also become minimized, detailed in Fig. 7.3.
All signal routing layers must be routed internally (stripline), with both top
and bottom layers being solid planes, preferably at AC chassis potential. If
the outer layers are at 0V-potential, direct chassis connection from logic
ground to chassis ground is easily achieved.
The greater the number of connector slots, the larger the value of lumped
distributed capacitance presented to the circuit. With additional
capacitance, degradation of signal quality can occur, sometimes to the
point of nonfunctionality. Compensating for clock skew must be performed
for all source drivers, taking into account the total capacitance of the routed
trace as well as all loads present within the transmission line (discussed in
Chapter 4).
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Table of Contents
Chapter 7 - Backplanes, Ribbon Cables, and Daughter Cards
Chapter 7
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
7.1: BASICS
by Mark I. Montrose
7.2: CONNECTOR PINOUT
ASSIGNMENT IEEE Press 2000
7.3: AC CHASSIS PLANES
7.4: BACKPLANE Recommend this title?
CONSTRUCTION
7.5: INTERCONNECTS
7.6: MECHANICAL
7.7: SIGNAL ROUTING
7.8: TRACE LENGTH/SIGNAL
TERMINATION
7.9: CROSSTALK
7.10: GROUND LOOP
7.5 INTERCONNECTS
CONTROL
7.11: GROUND SLOTS IN
BACKPLANES Concerns exist for interconnects used for backplanes, ribbon cable
REFERENCES
assemblies, and daughter cards, especially when a large number of
connectors are provided. When many connector slots exist in an assembly,
a summation of intrinsic device delay will occur between loads connected
to the bus. This device delay is in addition to the intrinsic line delay when
boards are inserted into the assembly. Our concern with signal delay is the
capabilities of the total assembly related to I/O data transfer. I/O data
transfer includes the source driver injecting a signal onto a bus, which must
be received at a load located somewhere else.
4. Using low dielectric constant board materials. The lower the dielectric
value, the faster the velocity of propagation of the transmitted signal.
Capacitance within a trace route will slow the transmitted signal,
sometimes significantly. If we allow for a faster propagation medium,
the "net result" is enhanced high-speed signal integrity using a faster
dielectric, along with a slowing down of the transmitted signal due to
line capacitance.
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Table of Contents
Chapter 7 - Backplanes, Ribbon Cables, and Daughter Cards
Chapter 7
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
7.1: BASICS
by Mark I. Montrose
7.2: CONNECTOR PINOUT
ASSIGNMENT IEEE Press 2000
7.3: AC CHASSIS PLANES
7.4: BACKPLANE Recommend this title?
CONSTRUCTION
7.5: INTERCONNECTS
7.6: MECHANICAL
7.7: SIGNAL ROUTING
7.8: TRACE LENGTH/SIGNAL
TERMINATION
7.9: CROSSTALK
7.10: GROUND LOOP
7.6 MECHANICAL
CONTROL
7.11: GROUND SLOTS IN
BACKPLANES If possible, one should try to provide additional real estate on a backplane
REFERENCES
for support circuitry. This additional area allows for filtering and termination
of I/O connectors and hookup to the power supply. Decoupling, bulk and
bypass capacitors, if required, are installed in this area. Cable shield
(braid) attachment, if used, must also occur to all ground planes in this
area through a low-impedance path to chassis ground, not logic ground or
the power return plane. Low-impedance connection means a solid 360
degree bond to the metal I/O connectors, or a flat braid with a width to
thickness ratio of 5:1, respectively.
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Table of Contents
Chapter 7 - Backplanes, Ribbon Cables, and Daughter Cards
Chapter 7
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
7.1: BASICS
by Mark I. Montrose
7.2: CONNECTOR PINOUT
ASSIGNMENT IEEE Press 2000
7.3: AC CHASSIS PLANES
7.4: BACKPLANE Recommend this title?
CONSTRUCTION
7.5: INTERCONNECTS
7.6: MECHANICAL
7.7: SIGNAL ROUTING
7.8: TRACE LENGTH/SIGNAL
TERMINATION
7.9: CROSSTALK
7.10: GROUND LOOP
7.7 SIGNAL ROUTING
CONTROL
7.11: GROUND SLOTS IN
BACKPLANES Vias should be avoided when routing signal traces between planes for
REFERENCES
high-threat signals, which are defined as reset, clocks, audio, video,
analog, high-speed transmission of data, and related signals. Each via
adds approximately 13 nH inductance to the trace route. This inductance
range is due to the physical characteristics of the viadiameter and length.
Use of vias may make traces susceptible to signal integrity problems and
EMI emissions. All traces must be routed on the same signal plane without
use of vias, from source to load, if possible. Daisy-chaining traces is
permitted only if load components are located adjacent to each other at the
end of a long trace route. In all other cases, terminated radial trace routing
(see Chapter 4) must be used. Series termination must be provided
immediately adjacent to the output of each driver, with a minimal number of
fanouts if this termination method is chosen. A radial termination maintains
functional signal quality, as well as minimizing EMI noise by removing
reflections within the transmission line, as well as minimizing overshoot
and ringing.
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Table of Contents
Chapter 7 - Backplanes, Ribbon Cables, and Daughter Cards
Chapter 7
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
7.1: BASICS
by Mark I. Montrose
7.2: CONNECTOR PINOUT
ASSIGNMENT IEEE Press 2000
7.3: AC CHASSIS PLANES
7.4: BACKPLANE Recommend this title?
CONSTRUCTION
7.5: INTERCONNECTS
7.6: MECHANICAL
7.7: SIGNAL ROUTING
7.8: TRACE
LENGTH/SIGNAL
TERMINATION
7.9: CROSSTALK
7.8 TRACE LENGTH/SIGNAL TERMINATION
7.10: GROUND LOOP
CONTROL
7.11: GROUND SLOTS IN
For standard speed TTL logic, trace termination is generally not required.
BACKPLANES
REFERENCES
For higher speed components, terminators become mandatory. The bus
driver (e.g., 74xxx244) on one plug-in board must be designed for driving
terminated loads to other boards through all connectors located throughout
a backplane assembly. The terminator, if used, must be the last load on a
signal trace route, with the driver circuit the first item on the bus. If using
multiple drivers from different slots, high-current drivers must be
substituted for high-speed drivers. Furthermore, owing to the possibility of
obtaining a distorted waveform, the slowest possible receivers, properly
balanced and terminated, must be used.
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Table of Contents
Chapter 7 - Backplanes, Ribbon Cables, and Daughter Cards
Chapter 7
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
7.1: BASICS
by Mark I. Montrose
7.2: CONNECTOR PINOUT
ASSIGNMENT IEEE Press 2000
7.3: AC CHASSIS PLANES
7.4: BACKPLANE Recommend this title?
CONSTRUCTION
7.5: INTERCONNECTS
7.6: MECHANICAL
7.7: SIGNAL ROUTING
7.8: TRACE LENGTH/SIGNAL
TERMINATION
7.9: CROSSTALK
7.10: GROUND LOOP
CONTROL
7.9 CROSSTALK
7.11: GROUND SLOTS IN
BACKPLANES
REFERENCES Crosstalk in backplanes, ribbon cable assemblies, adapter slots, and the
like is a major concern for signal integrity and EMC compliance. This
concern exists because many traces are routed in parallel and are
generally spaced close together. Signal routes may be very short to
extremely long (electrical wise with respect to propagation delay and signal
edge rate transitions). With long trace routes, termination is required to
remove harmful effects, thus enhancing signal quality. Although reference
is made to ribbon cables within this section, the concepts are identical to
backplane and daughter card implementation, as ribbon cable assemblies
are easier to describe and illustrate.
One ground plane or RF return path adjacent to all signal traces in the
assembly.
Note Although a ribbon cable assembly is detailed in Fig. 7.4, the same
concept applies directly to backplane and daughter card
interconnects to minimize or prevent crosstalk from occurring. The
concept provided is to ensure that there are adequate RF return
paths, separation of transmission lines, or placement of an image
plane adjacent to each signal trace.
If a very large parallel route is required and the traces are electrically long,
use of transmission line theory and application must be understood. For
paired signals, crosstalk may be minimized by twisting the traces (similar to
twisted-pair wire) internal to the PCB, if required. This technique is rarely
used, as cost-effective data line filters are available that provide enhanced
performance over this layout technique. Twisting traces is accomplished by
routing a paired set of signals to a via pair, crossing the traces (on an
adjacent routing layer), and with a second set of vias continue the signal
route. An even number of twists is required for optimal performance. This
outdated technique is shown in Fig. 7.5 and is provided for completeness.
Twisting traces in a PCB is not feasible, consumes valuable real estate,
and is an additional design concern during fabrication of the board. If
twisting is used, many twists must be implemented as possible. The twist
distance must be determined as /20 of the highest frequency (edge rate
transition) that is expected to traverse the entire route from source to load,
regardless of how propagation occurs.
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Table of Contents
Chapter 7 - Backplanes, Ribbon Cables, and Daughter Cards
Chapter 7
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
7.1: BASICS
by Mark I. Montrose
7.2: CONNECTOR PINOUT
ASSIGNMENT IEEE Press 2000
7.3: AC CHASSIS PLANES
7.4: BACKPLANE Recommend this title?
CONSTRUCTION
7.5: INTERCONNECTS
7.6: MECHANICAL
7.7: SIGNAL ROUTING
7.8: TRACE LENGTH/SIGNAL
TERMINATION
7.9: CROSSTALK
7.10: GROUND LOOP
7.10 GROUND LOOP CONTROL
CONTROL
7.11: GROUND SLOTS IN
BACKPLANES If a one-, two-, or four-layer backplane is implemented, proper attention
REFERENCES
must be paid to minimize ground loops between all power and ground
traces. Signal lines must be routed with as many ground paths as possible,
interconnected to the main ground reference through the connector or
interface. Power and ground must always be routed adjacent to each other
(Fig. 7.6). This configuration is recommended for ribbon cable assemblies
and may not be feasible for a typical PCB layout.
As seen in Fig. 7.6, traces are routed in stripline fashion: signal trace
adjacent to a ground trace. The main power and ground trace are routed in
the middle of the board for better uniformity in power distribution. Also,
routing power and ground adjacent to each other minimizes ground loops
in the power section of the backplane. Use of many ground traces in a
backplane or ribbon cable minimizes development of crosstalk between
traces. This separation for high-speed, high-threat signal traces (source)
prevents corrupting other sensitive traces (victim), such as reset, alarm,
video, audio, and analog control.
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Table of Contents
Chapter 7 - Backplanes, Ribbon Cables, and Daughter Cards
Chapter 7
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
7.1: BASICS
by Mark I. Montrose
7.2: CONNECTOR PINOUT
ASSIGNMENT IEEE Press 2000
7.3: AC CHASSIS PLANES
7.4: BACKPLANE Recommend this title?
CONSTRUCTION
7.5: INTERCONNECTS
7.6: MECHANICAL
7.7: SIGNAL ROUTING
7.8: TRACE LENGTH/SIGNAL
TERMINATION
7.9: CROSSTALK
7.10: GROUND LOOP 7.11 GROUND SLOTS IN BACKPLANES
CONTROL
7.11: GROUND SLOTS IN
BACKPLANES A common practice when designing backplanes is to select a connector
REFERENCES
with pressfit (stake) or through-hole pins. Newer technology connectors
with a large number of pins are available in surface mount form. Surface
mount connectors route signal traces to inner layers through vias.
Depending on the connector style and method chosen, ground slots may
be accidentally designed into the backplane assembly.
As seen in Fig. 7.7, return currents between adapter modules cannot mirror
image themselves directly under their respective trace route. Instead, RF
return current is diverted to the ends of the connector assembly due to a
continuous slot created by oversized holes. To remedy this problem, a
solid reference plane with sufficient copper must exist around all through-
hole locations.
Figure 7.7 also shows that RF return current from traces parallel to each
other actually overlaps at the edge of the through-hole slots. The
commingling of RF return current creates a situation of common-mode
impedance coupling. This means that RF current from one return path will
mix with other return current sharing the same physical space. Depending
on the phase of the RF current for each trace, a significant amount of RF
energy may be present, exacerbating EMI harmful effects.
(7.1)
Get MathML
where L = inductance, nH
w = trace width (in. or cm)
d = slot length of connector (in. or cm)
The value of d is the extent of current diversion away from the signal trace.
Consistent units of measurements must be used.
Inductance is not related to the width of the ground slot; it is related only to
the perpendicular length of the slot. Any slot length will cause RF diversion.
Since RF current division is based only on slot length, traces closest to the
edge of the connector will have less current diversion than traces routed in
the middle of the connector (longer return current travel length).
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Table of Contents
Chapter 7 - Backplanes, Ribbon Cables, and Daughter Cards
Chapter 7
OVERVIEW Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
7.1: BASICS
by Mark I. Montrose
7.2: CONNECTOR PINOUT
ASSIGNMENT IEEE Press 2000
7.3: AC CHASSIS PLANES
7.4: BACKPLANE Recommend this title?
CONSTRUCTION
7.5: INTERCONNECTS
7.6: MECHANICAL
7.7: SIGNAL ROUTING
7.8: TRACE LENGTH/SIGNAL
TERMINATION
7.9: CROSSTALK
7.10: GROUND LOOP
REFERENCES
CONTROL
7.11: GROUND SLOTS IN
BACKPLANES [1] Montrose, M. 1999. EMC and the Printed Circuit Board Design
REFERENCES
Design, Theory and Layout Made Simple. Piscataway, NJ: IEEE Press.
[2] Johnson, H. W., and M. Graham. 1993. High Speed Digital Design.
Englewood Cliffs, NJ: Prentice Hall.
[6] Williams, T. 1996. EMC for Product Designers. 2nd ed. Oxford, UK:
Butterworth-Heinemann.
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Table of Contents
Chapter 8 - Additional Design Techniques
Chapter 8
8.1: LOCALIZED PLANES Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
8.1.1: Localized Decoupling
by Mark I. Montrose
Capacitor Implementation
8.2: 20-H RULE IEEE Press 2000
8.3: TRACE ROUTING FOR
CORNERS
8.4: SELECTING FERRITE Recommend this title?
COMPONENTS
8.5: GROUNDED HEATSINKS
8.6: LITHIUM BATTERY
CIRCUITS
8.7: BNC CONNECTORS
8.8: CREEPAGE AND
CLEARANCE DISTANCES
8.9: CURRENT-CARRYING
CAPACITY OF COPPER
Chapter 8: Additional Design
TRACES
8.10: FILM
REFERENCES
Techniques
8.1 LOCALIZED PLANES
During component placement, oscillators, crystals, and support circuitry
(buffers, drivers, etc.) must be located over a single localized plane. This
plane is usually at ground potential but can be at voltage potential. Some
components, having unique power requirements, mandate a voltage plane
directly under the device. Regardless of potential, the concept described
herein is the issue of importance: localized planes. This localized plane is
located on the outer microstrip layer and ties directly into the main power or
ground planes of the PCB through both the oscillator and component's
power and ground pins. In addition to these pins, a minimum of two
additional vias is required. If the plane is at ground potential, it should be
positioned next to a ground stitch location, where it must be fully connected
in a 360 fashion to remove RF energy present within the plane. Use of
soldermask is not recommended. Soldermask provides a dielectric material
on the board that could possibly change the impedance of a transmission
line that carries the clock signal, thus causing potential concerns about
signal integrity. This situation rarely occurs, however, and should not be a
significant design concern. An example of a localized plane at ground
potential is shown in Fig. 8.1.
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Table of Contents
Chapter 8 - Additional Design Techniques
Chapter 8
8.1: LOCALIZED PLANES Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
8.2: 20-H RULE by Mark I. Montrose
Technical Presentation on
How and Why the 20-H Rule IEEE Press 2000
Works
Analysis of a Microstrip
Transmission Line Recommend this title?
Analysis of Planar
Application: Plane
Terminations
8.3: TRACE ROUTING FOR
CORNERS
8.4: SELECTING FERRITE
Figure 8.3 shows the effects of RF fringing from the edge of a PCB and
illustrates how magnetic flux exist. The two planes are first located far apart
and then are brought in close to each other. To visualize what happens,
consider a source of current modulation, along with any other impedance
that may be present. This current source can be developed by an item
such as a storage capacitor, positioned in various places throughout the
PCB. For example, a component is on one side of a plane, and the DC
current source (storage capacitor) is on the exact opposite side. There will
be a clearly defined current and flux pattern within the planes. Under this
condition, and without flux linkage between the planes, the current and flux
"loop" will take a defined form. Flux will surround each plane, appearing, in
general, more or less elliptical.
Now slowly bring the two planes closer together. As the flux begins to link,
the flux density is significantly increased between the planes. In order for
the flux density to increase, the "shape" of the "elliptical" flux changesit is
directed inward toward the opposing plane. Two things happen in this
process, other than the increase of flux density between planes: (1) the
"shape" of the flux that surrounds the planes gets directed inward; and (2)
the fringing of the flux at the edges of the planes gets directed outward.
Use of the 20-H rule increases the intrinsic self-resonant frequency of the
PCB, because the physical dimensions of the power distribution network
are altered. Since less capacitance will be present, there will be a higher
self-resonant frequency of operation. This impedance change in the power
distribution threshold is first noticed at approximately 10-H, with 20-H
representing the approximately 70% flux boundary. The dimension "H" is
the physical distance spacing between the power and ground plane within
the stackup. Flux boundary refers to the distance that magnetic lines of flux
are observed from the planar structure in the near field. To achieve a 98%
flux boundary, 100-H is used. Increasing the physical dimension between
planes greater than 20-H does not provide any significant reduction in the
propagation of RF energy and in fact makes the PCB more difficult to
route.
To implement the 20-H rule, determine the distance spacing between the
power plane and its nearest ground plane. This distance spacing includes
the thickness of the core or prepreg, including isolation separation
specified in the PCB fabrication drawing. Assuming a distance separation
of 0.006 in. (0.2 mm) between the power and ground planes, calculate H
as [20 * 0.006 in. (0.2 mm) = 0.120 in. (3.0 mm)]. Physically make the
power plane 0.120 in. (3.0 mm) smaller than the ground plane. Should a
power pin to a component be located inside this isolated (absence of
copper) area, the power plane may be altered to provide power to this pin
by using a trace or by altering the shape. This alteration of the power plane
is shown in Fig. 8.4. Altering the shape of the reduced power plane does
not affect performance.
When using the 20-H rule, any traces on the adjacent signal routing plane,
located over the absence of copper area, must be rerouted inward to be
physically adjacent to the solid power plane, with no exceptions. It
becomes important now to check two or more planes for proper
implementation: 20-H on the power plane, and routing of traces over a
solid power plane. Traces cannot be routed on the outer edge of the
routing layer adjacent to a physically smaller power plane because traces
must be adjacent to a reference plane for impedance control and for RF
return current. Routing traces in this area gives identical results to routing a
trace over a moat (violation), as discussed in Chapter 5.
Note The intended audience for this book is practicing engineers with
hands-on requirements to get the job done. The following
discussion is extremely technical.
Assume that the termination value is about ten times higher than the
characteristic impedance of the transmission line. In this situation, the
"termination" is a value that will not fully terminate the line. The position of
the termination is such that a rather long "stub," as a percentage of total
transmission line length, is created at the end of the line. The flux field
fringing depends on the exact relationship and distribution path near the
plane edges. The distribution of the flux depends on the geometry of the
component and its geometry from the edge of the PCB.
The result of this example is that the transmission line will not be properly
terminated. The stub will create reflections back toward the source that can
set up resonances in the line. The reflections themselves will only be
partially terminated, because the impedance of the termination is incorrect
(too high).
Next, translate transmission line theory to the power and ground planes,
along with their respective currents contained between the two planes.
What is the "shape" of the current flow? Obviously, it depends on the
positions of the loads. The shape or geometry of the flux lines, as well as
the manner in which the current propagates between planes is difficult, if
not impossible, to simulate for a fully active PCB with many components
and routed traces switching current levels simultaneously.
A PCB with a source injected into the center of the board will have current
travel to the edge of the board in all directions (360 degrees). This current
flow is an excellent example of a complex problem that is not well
understood by engineers. This analysis is simply an application of the
microstripline analogy given earlier, viewed now with the planes forming
the transmission line in a vertical, or z-axis.
The planes, however, continue out far beyond the shape of this boundary.
This simply means that they are "not" terminated, and if they are "not"
terminated, the planes become one large planar "stub" that causes
reflections and resonances throughout the board. These resonances
usually do not cancel because of the phase angle skew between the
planes. This skew is caused by the inductive characteristics of the planes.
In any transmission line, there are two possible solutions to this problem.
Either plane (usually the power plane) could be "undercut" to mechanically
"remove" the stub; or the edges of the plane could be terminated in a
distributed manner. Since the planes themselves are distributed,
terminations would have to be located around the perimeter in small
increments, being bandwidth and harmonic spectra dependent. In addition,
when attempting to "edge-terminate" transmission lines, which are in fact
"the planes," there exist a spectra of RF energy at different wavelengths.
This spectral energy is observed because the planes are of significant size
with respect to wavelength harmonics. Multiple and frequent terminations
around the edges will be required. These terminators must be located at
intervals that are small with respect to the spectra of interest.
The advantage of undercutting one of the planes, usually the power plane,
is that power energy is not wasted in the dissipation of the terminations.
RC terminations can be poor at specific frequencies of concern, because of
the resonance of the capacitor and the connection traces.
The intended goal of the 20-H rule is to terminate the planes locally toward
the circulating current boundaries of the flux and RF fields formed by
device-power-currents located at the edges of the boards, not to set an
arbitrary dimension. Even if one were to resistively terminate the
"flying" (unterminated) planes, the mechanical geometry of the resistors (at
least 1206 in size) would probably require undercutting the planes about
20-H at a 0.055 in. (1.4 mm) planar height.
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Table of Contents
Chapter 8 - Additional Design Techniques
Chapter 8
8.1: LOCALIZED PLANES Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
8.2: 20-H RULE
by Mark I. Montrose
8.3: TRACE ROUTING
FOR CORNERS IEEE Press 2000
8.3.1: Time Domain
Analysis
Recommend this title?
8.3.2: Frequency Domain
Analysis
8.3.3: Summary of Effects
from Right-Angle Corners
8.4: SELECTING FERRITE
COMPONENTS
8.5: GROUNDED HEATSINKS
8.6: LITHIUM BATTERY
CIRCUITS 8.3 TRACE ROUTING FOR CORNERS
8.7: BNC CONNECTORS
8.8: CREEPAGE AND
CLEARANCE DISTANCES Attention to detail must be observed when designing with sub-nanosecond
8.9: CURRENT-CARRYING
CAPACITY OF COPPER transitions to avoid an effect similar to capacitive loading that occurs during
TRACES
8.10: FILM normal routing of traces. When a trace makes a bend on the PCB, its
REFERENCES capacitance per unit length will increase while its inductance per unit length
will decrease. This is shown in Fig. 8.7 and is true for sharp angles of 90
or more. The magnitude of the capacitive and inductive change within a
sharp-angled corner is extremely small.
(8.1)
Get MathML
The primary electrical effect, in the time domain for a right-angle corner
referenced to a plane, is a small amount of parasitic capacitance to ground,
described by Eq. (8.2) [3]. For example, assume Z = 65 ohms (typical
o
impedance of a PCB trace), = 4.3, and W = 0.007 in. The right-angle
r
corner has a capacitive increase of C = 0.014 pF or 14 femtoFarads, a
value that is so small as to not cause concerns for signals propagating
through the transmission line below 100 GHz.
(8.2)
Get MathML
(8.3)
Get MathML
Equation 8.3 tells us that the only signals affected by a trace width
discontinuity (right-angle corner) are for signals with an edge rate transition
faster than 100 ps. In reality, the actual edge transition speed, before
signal integrity concerns develop, is 50 ps. The 50 ps value is conservative
for design purposes. Once we start to have signals with this fast transition
time, the product is probably operating in the GHz range, using microwave
design and layout techniques, which mandate use of round corners
anyway, for all traces.
(8.4)
Get MathML
The main reason for not designing a PCB with right-angle corners lies with
manufacturing. When traces are etched, the chemical etchant starts at the
corner of trace. During etching, the corner will be etched back first by a
certain amount, thus causing the physical dimensions to decrease. For a
20-mil trace, the amount of etch back is minimal. For a 5-mil trace, the
finished etched trace may end up at 3 mils, which is a more serious
problem than a wider trace. Functional problems may occur if a significant
amount of current is transferred through the corner (fusing of the trace). In
addition, delamination may occur. Delamination refers to the peeling of the
trace from the board, thus destroying the trace during manufacturing and
assembly.
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Table of Contents
Chapter 8 - Additional Design Techniques
Chapter 8
8.1: LOCALIZED PLANES Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
8.2: 20-H RULE
by Mark I. Montrose
8.3: TRACE ROUTING FOR
CORNERS IEEE Press 2000
8.4: SELECTING FERRITE
COMPONENTS
Recommend this title?
8.5: GROUNDED HEATSINKS
8.6: LITHIUM BATTERY
CIRCUITS
8.7: BNC CONNECTORS
8.8: CREEPAGE AND
CLEARANCE DISTANCES
8.9: CURRENT-CARRYING
CAPACITY OF COPPER
TRACES
8.4 SELECTING FERRITE COMPONENTS
8.10: FILM
REFERENCES
It is a well-known fact that ferrite devices (bead-on-lead, toroids, cores,
split cores, wound beads, etc.) attenuate RF energy. The biggest difficulty
in using a ferrite component is selecting the proper device for a specific
application. Usually, the trial and error method is performed by the EMI or
design engineer during attempts to solve a radiated or conducted emission
problem. In reality, selection of a ferrite device is quite simple [5].
For the last two applications, ferrite cores suppress EMI by eliminating or
reducing high-frequency RF currents emanating from an EMI source.
When a ferrite material is introduced, high-frequency impedance results,
suppressing high-frequency RF currents. Theoretically, an ideal ferrite
would provide high impedance at RF frequencies and zero impedance at
all other frequencies. The impedance value is generally low, below 1 MHz.
Depending on the ferrite material used, maximum impedance is usually
observed between 10 MHz and 300 MHz.
3. Suppression of RF energy.
Soft ferrite changes its magnetic state based on the environment in which
the device is being used. Hard ferrite is a permanent polarization or
magnetizing of a material, similar to a permamagnet with a north and south
pole. Each application requires optimal intrinsic material characteristic
selection and a required core geometry.
(8.5)
Get MathML
Bias (current flow through the material) will decrease the impedance to
the point of nonfunctionality.
(8.6)
Get MathML
Impedance (ohms)
Bead Type and
Dimensions (L 1 5 10 20 30 50
OD ID in mm) MHz MHz MHz MHz MHz MHz
= 850, 3.25 2 8 13 20 28 32
3.5 1.6
= 2500, 3.25 11 26 32 37 37 35
3.5 1.6
= 850, 7.5 5 18 29 40 58 61
7.65 2.25
= 2500, 7.5 25 47 58 61 61 60
7.65 2.25
= 850, 11.1 14 41 66 95 110 115
5.1 1.5
= 2500, 11.1 46 100 125 160 160 155
5.1 1.5
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Table of Contents
Chapter 8 - Additional Design Techniques
Chapter 8
8.1: LOCALIZED PLANES Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
8.2: 20-H RULE
by Mark I. Montrose
8.3: TRACE ROUTING FOR
CORNERS IEEE Press 2000
8.4: SELECTING FERRITE
COMPONENTS
8.5: GROUNDED Recommend this title?
HEATSINKS
8.6: LITHIUM BATTERY
CIRCUITS
8.7: BNC CONNECTORS
8.8: CREEPAGE AND
CLEARANCE DISTANCES
8.9: CURRENT-CARRYING
CAPACITY OF COPPER
TRACES
8.10: FILM 8.5 GROUNDED HEATSINKS
REFERENCES
Heatsinks are usually made of metal and contain fin structures. Depending
on processor harmonics, heatsink dimensions can become electrically able
to start radiating RF energy. Because of the close proximity of the
processor, related to other circuits and subassemblies, RF noise may be
coupled through various paths, for example, internal cables or apertures,
both of which can leak to the outside environment.
Having examined the thermal need for heatsinks, we observe the following
characteristics (Figs. 8.9 and 8.10):
Figure 8.9: Grounded heatsink theory of operation.
The wafer dies operating at high clock speeds, generally 100 MHz and
above, generate large amounts of common-mode RF current internal to
the device package.
The wafer (or die) internal to the package (Fig. 8.10) is located closer to
the top of the case (dimension X) than the bottom of the package
(dimension Y). Therefore, height separation from the silicon die to an
image plane internal to the PCB is greater than the distance of the die
to the top of the package case and heatsink. Common-mode RF
currents generated internally within the wafer have no place to couple to
0V-reference. Hence, RF energy is radiated from the device into free
space. Differential-mode decoupling capacitors will not remove
common-mode noise created within the component.
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Table of Contents
Chapter 8 - Additional Design Techniques
Chapter 8
8.1: LOCALIZED PLANES Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
8.2: 20-H RULE
by Mark I. Montrose
8.3: TRACE ROUTING FOR
CORNERS IEEE Press 2000
8.4: SELECTING FERRITE
COMPONENTS
8.5: GROUNDED HEATSINKS Recommend this title?
8.6: LITHIUM BATTERY
CIRCUITS
8.7: BNC CONNECTORS
8.8: CREEPAGE AND
CLEARANCE DISTANCES
8.9: CURRENT-CARRYING
CAPACITY OF COPPER
TRACES
8.6 LITHIUM BATTERY CIRCUITS
8.10: FILM
REFERENCES International safety agencies require protection against explosion from
lithium batteries should an abnormal fault occur, such as a short circuit or
reverse bias during a charging cycle. Lithium battery circuits may consist of
a discrete battery with passive components, or may be included as part of
a NVRAM (Non-Volatile RAM) or Non-Volatile Clock Calendar module. The
battery must be provided with reverse current protection. This protection
must be redundant in nature and typically consists of two diodes back to
back or a diode and a resistor in series. A typical lithium battery circuit with
common protection components is shown in Figure 8.12.
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Table of Contents
Chapter 8 - Additional Design Techniques
Chapter 8
8.1: LOCALIZED PLANES Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
8.2: 20-H RULE
by Mark I. Montrose
8.3: TRACE ROUTING FOR
CORNERS IEEE Press 2000
8.4: SELECTING FERRITE
COMPONENTS
8.5: GROUNDED HEATSINKS Recommend this title?
8.6: LITHIUM BATTERY
CIRCUITS
8.7: BNC CONNECTORS
8.8: CREEPAGE AND
CLEARANCE DISTANCES
8.9: CURRENT-CARRYING
CAPACITY OF COPPER
TRACES
8.10: FILM 8.7 BNC CONNECTORS
REFERENCES
For applications where the shell of the BNC connector is signal return and
is not used as a RF return shield, the shell of the BNC connector, must be
connected through a low-impedance path to the 0V-reference of the signal
return circuit. Do not connect the ground (outer barrel) pin of the BNC
connector to the I/O isolated (quiet ground) area. In addition, do not
connect the shell of the BNC connector to the chassis ground (I/O bracket).
To implement this unique scheme, an isolated BNC connector available
from many vendors must be used. These connectors guarantee that the
shell and internal signal pin of the connector are isolated from chassis
ground. This scheme will cause problems if not properly implemented (Fig.
8.13).
Pigtails must never be used, under any condition, to connect the shell of
the BNC connector to chassis ground or to any other ground system.
Measurements are well documented showing a 40- to 50-dB difference
between a pigtail and a 360 connection of the cable shield to the BNC
connector shell in the 15- to 200-MHz frequency range related to RF
emission. In addition to improvement in reducing RF emissions, a greater
level of ESD immunity is provided due to less lead inductance presented to
the ESD event. For most applications, the recommendation for cable
shields is to connect the cable shield to the BNC connector shell in a 360
fashion. This backshell then mates with a bulkhead panel containing a solid
metallic contact with chassis ground.
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Table of Contents
Chapter 8 - Additional Design Techniques
Chapter 8
8.1: LOCALIZED PLANES Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
8.2: 20-H RULE
by Mark I. Montrose
8.3: TRACE ROUTING FOR
CORNERS IEEE Press 2000
8.4: SELECTING FERRITE
COMPONENTS
8.5: GROUNDED HEATSINKS Recommend this title?
8.6: LITHIUM BATTERY
CIRCUITS
8.7: BNC CONNECTORS
8.8: CREEPAGE AND
CLEARANCE DISTANCES
Insulation Definition
Definition of Pollution
Degrees
8.8 CREEPAGE AND CLEARANCE DISTANCES
8.9: CURRENT-CARRYING
CAPACITY OF COPPER
TRACES Another concern with safety agencies lies with the potential risk of electric shock that may occur between traces and conductive parts of a system. Although creepage
8.10: FILM
REFERENCES
and clearance are not directly associated with EMI, a discussion of this topic must be presented in a book for PCB designers, since all products must comply with both
safety and EMC requirements. One cannot design a product to be compliant for only EMC. Both safety and EMC must be considered simultaneously during the design
and layout cycle.
Creepage and clearance, defined by harmonized safety standards, are described in the following list and illustrated in Fig. 8.14 [7]:
Creepage is the shortest path between two conductive parts, or between a conductive part and the bounding surface of the equipment, measured along the surface
of the insulation.
Clearance is the shortest distance between two conductive parts, or between a conductive part and the bounding surface of the equipment, measured through air.
Bounding surface is the outer surface of the electrical enclosure considered as though metal foil was pressed into contact with the accessible surface of insulation
material.
The creepage and clearance distance must be maintained primarily because high-voltage circuits on a PCB may be subjected to a failure condition. Failures include
electrical shorts between primary-to-secondary, primary-to-ground, or primary-to-primary circuits. To prevent a shock hazard resulting from an unexpected fault, the
designer must route specific traces with a certain amount of spacing (distance) between high-energy (voltage) sources and secondary or ground circuits. This
requirement is especially critical in power supplies and telecommunication products.
Under high-voltage or fault conditions, arcing may occur across the conformal coating, the soldermask, or between traces and a bounding surface. Consequently, a
high level of voltage and current may be present that creates a situation for risk of fire or electric shock. International safety standards specify minimum creepage and
clearance distances for various types of equipment under specific operating conditions identified as pollution degrees. Tables 8.3 to 8.6 present details on distance
requirements for both creepage and clearance, extracted from internationally harmonized safety standards for information technology equipment. These distances are
recognized worldwide and are strictly enforced. The values in the tables are the minimum values that shall be applied, after taking into account manufacturing
tolerances and deformation. These variations occur as a result of handling, shock, and vibration encountered during manufacture, transport, and normal use. For all
power systems, the main supply voltage in Tables 8.3, 8.4, 8.5 and 8.6 is the phase-to-neutral voltage.
Table 8.3: Clearance Distances for Primary Current Carrying Traces
Open table as spreadsheet
Minimum clearances for insulation in primary circuits, and between primary and secondary circuits mm
Circuits subject to Installation category II
Insulation working voltage
(see 2.2.7) up to and Nominal mains supply
Nominal mains supply voltage 150 V Nominal mains supply voltage >150 V 300
Including voltage > 300 V 600 V
(Translent rating 1500 V) V (Translent rating 2500 V)
(Translent rating 4000 V)
Pollution degrees 1 Pollution degrees 1 Pollution degrees 1, 2 and
V peak V r.m.s. Pollution degree 3 Pollution degree 3
and 2 and 2 3
or d.c. V (sinusoidal) V
Op B/S R Op B/S R Op B/S R Op B/S R Op B/S R
71 50 0.4 1.0 2.0 1.0 1.3 2.6 1.0 2.0 4.0 1.3 2.0 4.0 2.0 3.2 6.4
(0.7) (1.4) (1.0) (2.0) (1.7) (3.4) (1.7) (3.4) (3.0) (6.0)
210 150 0.7 1.0 2.0 1.0 1.3 2.6 1.4 2.0 4.0 1.7 2.0 4.0 2.0 3.2 6.4
(0.7) (1.4) (1.0) (2.0) (1.7) (3.4) (1.7) (3.4) (3.0) (6.0)
420 300 Op 1.7 B/S 2.0 (1.7) R 4.0 (3.4) 2.5 3.2 6.4
(3.0) (6.0)
840 600 Op 3.0 B/S 3.2 (3.0) R 6.4 (6.0)
1,400 1,000 Op/B/S 4.2 R 6.4
2,800 2,000 Op/B/S/R 8.4
7,000 5,000 Op/B/S/R 17.5
9,800 7,000 Op/B/S/R 25
14,000 10,000 Op/B/S/R 37
28,000 20,000 Op/B/S/R 80
42,000 30,000 Op/B/S/R 130
Table 8.4: Additional Clearance Distances for Use with High- Voltage Applications
Open table as spreadsheet
Additional clearances for insulation in primary circuits with repetitive peak voltages exceeding the peak value of the mains supply voltage
Nominal mains supply voltage >
Nominal mains supply voltage 150 V Additional clearance mm
150 V 300 V
Pollution degrees 1 and 2 Pollution degree 3 Pollution degrees 1, 2 and 3 Operational, basic or
supplementary Insulation
Maximum repetitive peak Maximum repetitive Maximum repetitive peak Reinforced
voltage V peak voltage V voltage V Insulation
210 (210) 210 (210) 420 (420) 0 0
298 (290) 294 (300) 493 (497) 0.1 0.2
386 (370) 379 (390) 567 (574) 0.2 0.4
474 (450) 463 (480) 640 (651) 0.3 0.6
562 (530) 547 (570) 713 (728) 0.4 0.8
650 (610) 632 (660) 787 (805) 0.5 1.0
738 (690) 716 (750) 860 (881) 0.6 1.2
826 (770) 800 (840) 933 (958) 0.7 1.4
914 (850) - - 1,006 (1,035) 0.8 1.6
1,002 (930) - - 1,080 (1,112) 0.9 1.8
1,090 (1,010) - - 1,153 (1,189) 1.0 2.0
- - - - 1,226 (1,266) 1.1 2.2
- - - - 1,300 (1,343) 1.2 2.4
- - - - - (1,420) 1.3 2.6
71 50 0.4 0.7 1.4 1.0 1.3 2.6 0.7 1.0 2.0 1.0 1.3 2.6 1.7 2.0 4.0 0.4 0.4 0.8
(0.4) (0.8) (1.0) (2.0) (0.7) (1.4) (1.0) (2.0) (1.7) (3.4)
140 100 0.6 0.7 1.4 1.0 1.3 2.6 0.7 1.0 2.0 1.0 1.3 2.6 1.7 2.0 4.0 0.6 0.7 1.4
(0.6) (1.2) (1.0) (2.0) (0.7) (1.4) (1.0) (2.0) (1.7) (3.4) (0.6) (1.2)
210 150 0.6 0.9 1.8 1.0 1.3 2.6 0.7 1.0 2.0 1.0 1.3 2.6 1.7 2.0 4.0 0.6 0.7 1.4
(0.6) (1.2) (1.0) (2.0) (0.7) (1.4) (1.0) (2.0) (1.7) (3.4) (0.6) (1.2)
280 200 Op 1.1 B/S 1.4 (1.1) R 2.8 (2.2) 1.7 (2.0) 4.0 1.1 1.1 2.2
(1.7) (3.4)
420 300 Op 1.6 B/S 1.9 (1.6) R 3.8 (3.2) 1.7 2.0 4.0 1.4 1.4 2.8
(1.7) (3.4)
700 500 Op/B/S 2.5 R 5.0
840 600 Op/B/S 3.2 R 5.0
1,400 1,000 Op/B/S 4.2 R 5.0
2,800 2,000 Op/B/S/R 8.4
7,000 5,000 Op/B/S/R 17.5
9,800 7,000 Op/B/S/R 25
14,000 10,000 Op/B/S/R 37
28,000 20,000 Op/B/S/R 80
42,000 30,000 Op/B/S/R 130
Within the tables, the following terms and references are used:
Insulation Definition
Operational Insulation: Insulation needed for the correct operation of the equipment.
Note By definition operational insulation does not protect against electric shock. It may, however serve to minimize exposure to ignition and fire. The use of air
as a barrier between a conductive part and dead metal is considered operational insulation.
Basic Insulation: Insulation to provide basic protection against electric shock. This insulation may be a PVC jacket over wire or shrink tubing over quick disconnect
terminals.
Supplementary Insulation: Independent insulation applied in addition to Basic Insulation in order to ensure protection against electric shock in the event of a failure
of the Basic Insulation.
Double Insulation: Insulation comprising both Basic Insulation and Supplementary Insulation.
Reinforced Insulation: A single insulation system that provides a degree of protection against electric shock equivalent to Double Insulation under the conditions
specified in the standard.
Note The term "insulation system" does not imply that the insulation has to be in one homogeneous piece. It may comprise several layers that cannot be tested
as Supplementary or Basic Insulation.
Working Voltage: The highest voltage to which the insulation under consideration is, or can be, subjected when the equipment is operating at its Rated Voltage
under conditions of normal use.
Pollution Degree 2: Generally applicable to equipment covered by the scope of the standard (applies to most equipment).
Pollution Degree 3: Applicable where a local internal environment within the equipment is subject to conductive pollution or to dry nonconductive pollution which
could become conductive due to expected condensation.
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Table of Contents
Chapter 8 - Additional Design Techniques
Chapter 8
8.1: LOCALIZED PLANES Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
8.2: 20-H RULE
by Mark I. Montrose
8.3: TRACE ROUTING FOR
CORNERS IEEE Press 2000
8.4: SELECTING FERRITE
COMPONENTS
8.5: GROUNDED HEATSINKS Recommend this title?
8.6: LITHIUM BATTERY
CIRCUITS
8.7: BNC CONNECTORS
8.8: CREEPAGE AND
CLEARANCE DISTANCES
8.9: CURRENT-CARRYING
CAPACITY OF COPPER
TRACES
8.9 CURRENT-CARRYING CAPACITY OF COPPER TRACES
8.10: FILM
REFERENCES The power-handling capability of copper traces is based on cross-sectional area and is related to temperature rise. For a specific cross-sectional area, the temperature rise within a trace, above
ambient levels, is approximately proportional to the power dissipated in the trace. An excessively large temperature rise makes circuits unreliable, heats up the dielectric material, and may
cause destruction of the trace. To be conservative during the design cycle, an upper limit on the heating of traces should not exceed 10C above ambient.
Figure 8.15 illustrates the current-carrying capability of traces, based on the amperage applied and cross-sectional area for a specific weight of copper [8, 9].
To illustrate how to read these charts, assume a 0.010-in. trace is constructed of 1-oz copper. The current-carrying capacity at 20C is 1.2A. Locate the conductor width (bottom chart, vertical
axis) and travel across to the appropriate weight of the copper, in this case, 1 oz. Draw a straight line up to the upper chart and stop at the desired temperature of operation. Read maximum
current value on the vertical axis of the upper chart.
The curves include a nominal 10% derating (on a current basis) to allow for normal variation in etching techniques, copper thickness, conductor width estimates, and cross-sectional area. An
additional derating of 15% (current-wise) is suggested under the following conditions:
1. For panel thickness of 0.031 in. (0.8 mm) or less.
High-power, high-current-carrying traces pose a serious constraint except for large power distribution buses, networks, or planes. As thin-film technology is being used on a frequent basis,
heating limitations become a serious design concern.
The temperature of a trace, or wire, depends on the environment within which the transmission line operates, and on whether the wire is insulated, coiled, or straight. Since resistance is
distributed over the length of the trace, this parameter plays a part in the temperature rise equation. Heating is proportional to the square of the current. Temperature rise is exponentially related
to the duration of current flow.
As the temperature level increases under heavy current loads, so does the resistance. This temperature rise serves to reduce the current present, if the source is voltage. If the source is current,
2
resistance increases with power dissipation per the equation P = I R.
The approximate fusing current of a wire, not a PCB trace, is given in Eq. (8.7) [10].
(8.7)
Get MathML
[1]
To illustrate this equation for an 18 AWG copper wire, d = 0.0403 in. and K = 10,244 (copper, the most common material used in PCB trace construction).
Get MathML
Since the melting temperature of copper is extremely high, one can largely ignore ambient temperature (e.g., the T in the equation).
Table 8.7 presents a conversion chart for PCB finished trace widths related to standard wire gauges. The numbers in this table are to be used for the d parameter of Eq. (8.7).
Table 8.7: Conversion Chart for PCB Finished Trace Widths Related to Standard Wire Gauges
Open table as spreadsheet
[1]
Equation and variables extracted from Reference Data for Engineers, 6th ed., ITT, July 1981, Table 39, pp. 454.
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Table of Contents
Chapter 8 - Additional Design Techniques
Chapter 8
8.1: LOCALIZED PLANES Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
8.2: 20-H RULE
by Mark I. Montrose
8.3: TRACE ROUTING FOR
CORNERS IEEE Press 2000
8.4: SELECTING FERRITE
COMPONENTS
8.5: GROUNDED HEATSINKS Recommend this title?
8.6: LITHIUM BATTERY
CIRCUITS
8.7: BNC CONNECTORS
8.8: CREEPAGE AND
CLEARANCE DISTANCES
8.9: CURRENT-CARRYING
CAPACITY OF COPPER
TRACES
8.10: FILM
8.10 FILM
REFERENCES
Because of the increasing density, the manufacturing process needs to be
monitored closely. Of special concern are test coupons, layer stackup
window, stacking stripes, and test points.
TEST COUPONS. Test coupons contain dummy traces that are routed on
an external, disposable part of the PCB. One test trace is provided per
routing layer. Test traces allow for easy measurement of the actual
impedance of the signal planes. These dummy traces validate the quality
control process of fabrication by the board vendor, assuring that the
assembly was manufactured within specified requirements. Test traces and
their pads are usually found on breakaway islands, not on the main artwork
or final assembly. For backplanes and PCBs with high-speed circuits, test
traces should be placed directly within the artwork, if not part of the design.
The multilayer process starts with core material and copper on both sides.
The inner layer surfaces are first etched, while the outer surface layers
remain fully copper-plated. The cores are then stacked together with
prepreg. After heating and curing, the dielectric constant of both materials
becomes the same value. Since prepreg partially melts during this process,
traces adjacent to the prepreg will sink into the glue material. Trace
separation between two layers is reduced by twice the thickness of a single
trace. This separation occurs because the glue spreads out over the
traces. Solid planes do not sink into the prepreg. After final assembly, any
prepreg that has been squeezed out of the sides of the PCB will be
trimmed away.
After curing, via holes are drilled. This drilling exposes the copper layers
and pads throughout the assembly, although connection is not made until a
plating material is inserted into the holes. This plating material covers both
the inside and outside surfaces of the board simultaneously. During this
plating process, a mask is applied to protect the PCB's outer layer except
for traces and via holes. After plating, outer traces will have accumulated
approximately 0.5-oz of copper. Impedance calculations for outer layer
traces must be calculated for a trace thickness of 1.5 oz, if a 1 oz copper
laminate is provided. After plating, the rest of the top layer is etched away,
leaving a finished product. The PCB is then protected with soldermask or
conformal coating and silk-screened.
In Fig. 8.17, all signal layers are oz. copper, while the reference planes
(voltage and ground), are 1 oz. The outer layer starts with 1 oz copper.
After plating, however, final thickness becomes 1.5 oz. For functionality
purposes, 1 oz copper is usually required, or two times the thickness of the
signal planes. This is because power planes must provide large amounts of
voltage and return currents to all components simultaneously. To prevent
overheating due to a large voltage (IR) drop within the plane, caused by
power consumption of all components, an additional layer of oz of
copper is required.
In a multilayer board, start by defining the core. These inner layers are
generally the reference planes (power and ground potential). If designated
as signal planes, etching is performed to define the trace structure. The
thickness between the opposing layers and core depends on the thickness
of the original laminate. If the overall height dimension of the board is 0.062
in. (1.6 mm), the thickness of the core for a four-layer stackup will be
greater than the spacing for a higher density board. This is because with
more layers, a smaller physical distance between layers must occur to
maintain the same overall height dimension. With a smaller distance
between layers, the trace width must be altered to maintain desired
impedance (see in Chapter 4). An example of height distance variation for
various stackup schemes is shown in Fig. 8.18.
All unconnected vias must be removed from the artwork prior to production
of the film. An unconnected via is defined as a pad on a plated through-
hole that has no physical connection to any trace on any signal layer. This
requirement does not apply to intentionally implemented ground vias that
are provided for layer jumping RF return current. The PCB designer must
perform this removal process prior to sending out film or gerber files for
processing. When a guard trace has been pulled away from a signal trace
by a via, pin escape, or through-hole device, there must be no connection
to this via on that layer. (Connection to this via must be made on a different
layer.)
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Table of Contents
Chapter 8 - Additional Design Techniques
Chapter 8
8.1: LOCALIZED PLANES Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
8.2: 20-H RULE
by Mark I. Montrose
8.3: TRACE ROUTING FOR
CORNERS IEEE Press 2000
8.4: SELECTING FERRITE
COMPONENTS
8.5: GROUNDED HEATSINKS Recommend this title?
8.6: LITHIUM BATTERY
CIRCUITS
8.7: BNC CONNECTORS
8.8: CREEPAGE AND
CLEARANCE DISTANCES
8.9: CURRENT-CARRYING
CAPACITY OF COPPER
TRACES
REFERENCES
8.10: FILM
REFERENCES
[1] Montrose, M. 1999. EMC and the Printed Circuit Board Design
Design, Theory and Layout Made Simple. Piscataway, NJ: IEEE Press.
[2] Montrose, M. 1998. "Time and Frequency Domain Analysis for Right
Angle Corners on Printed Circuit Board Traces." Proceedings of the
IEEE International Symposium on Electromagnetic Compatibility. New
York: IEEE, pp. 551556.
[4] Johnson, H. W., and M. Graham. 1993. High Speed Digital Design.
Englewood Cliffs, NJ: Prentice Hall.
[8] Coombs, C. 1997. Printed Circuits Handbook. 4th ed. New York:
McGraw-Hill.
[10] Reference Data for Engineers, 6th ed., ITT, July 1981.
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Table of Contents
Appendix A - Summary of Design Techniques
Appendix A
CHAPTER 1: Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
INTRODUCTION
CHAPTER 2: PRINTED by Mark I. Montrose
CIRCUIT BOARD BASICS
IEEE Press 2000
CHAPTER 3: BYPASSING
AND DECOUPLING
CHAPTER 4: CLOCK Recommend this title?
CIRCUITS, TRACE ROUTING,
AND TERMINATIONS
CHAPTER 5:
INTERCONNECTS AND I/O
CHAPTER 6:
ELECTROSTATIC
DISCHARGE PROTECTION
CHAPTER 7: BACKPLANES,
RIBBON CABLES, AND
DAUGHTER CARDS
Appendix A: Summary of Design
CHAPTER 8: ADDITIONAL
DESIGN TECHNIQUES Techniques
CHAPTER 1: INTRODUCTION
1. Application and use of the product should be considered for a specific
environmentresidential, commercial, light industrial, heavy
industrial, medical, telecommunications, and so forth. This
environment includes three areas of concern related to the EMC
environment: source, propagation path, and receptor (1.2).
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Table of Contents
Appendix A - Summary of Design Techniques
Appendix A
CHAPTER 1: Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
INTRODUCTION
CHAPTER 2: PRINTED by Mark I. Montrose
CIRCUIT BOARD BASICS
IEEE Press 2000
CHAPTER 3: BYPASSING
AND DECOUPLING
CHAPTER 4: CLOCK Recommend this title?
CIRCUITS, TRACE ROUTING,
AND TERMINATIONS
CHAPTER 5:
INTERCONNECTS AND I/O
CHAPTER 6:
ELECTROSTATIC
DISCHARGE PROTECTION
CHAPTER 7: BACKPLANES,
RIBBON CABLES, AND CHAPTER 2: PRINTED CIRCUIT BOARD BASICS
DAUGHTER CARDS
CHAPTER 8: ADDITIONAL 1. Passive components contain hidden behavioral characteristics.
DESIGN TECHNIQUES
Design engineers generally select a component for use only in the
time domain or at DC voltage levels. Because of digital logic transition
between high- and low-voltage levels, an AC switching element will
coexist based on the mathematics of the Fourier transform. This AC
element is identified as RF energy. Due to parasitics (characteristic
behavioral features within a device, such as capacitance between
windings of an inductor or capacitance between the leads of a
resistor), various effects will be observed. These effects are frequency
dependent and become more serious as frequency increases (2.1).
7. Where three or more reference planes are provided (e.g., one power
and two ground planes), optimal performance of high-speed signal
traces may be achieved when routed adjacent to a reference plane at
0V-reference, not adjacent to the power plane. The reason for this
statement is one of the basic fundamental concepts of designing EMI
suppression within a PCB (2.5).
22. The distant spacing between all ground locations is calculated based
on a straight-line distance not exceeding /20 of the highest
frequency generated on the board. A ground stitch is placed in the
middle between these two ground point locations (2.11).
25. One should never place three or more routing layers adjacent to each
other. Each routing layer must be adjacent to a solid reference plane
(2.12).
27. There must be optimal coupling of magnetic flux between both source
and return when connectors are used (2.12).
28. A solid image plane must never be violated with a trace route. Moats
are acceptable in an image plane, provided the adjacent routing layer
does not have traces crossing the moat (2.13).
32. The PCB can be partitioned into functional areas; high bandwidth
areas are separated from medium and low bandwidth; each section
can be isolated using partitions or moats, if required (2.14).
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Table of Contents
Appendix A - Summary of Design Techniques
Appendix A
CHAPTER 1: Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
INTRODUCTION
CHAPTER 2: PRINTED by Mark I. Montrose
CIRCUIT BOARD BASICS
CHAPTER 3: IEEE Press 2000
BYPASSING AND
DECOUPLING Recommend this title?
CHAPTER 4: CLOCK
CIRCUITS, TRACE ROUTING,
AND TERMINATIONS
CHAPTER 5:
INTERCONNECTS AND I/O
CHAPTER 6:
ELECTROSTATIC
DISCHARGE PROTECTION
CHAPTER 7: BACKPLANES, CHAPTER 3: BYPASSING AND DECOUPLING
RIBBON CABLES, AND
DAUGHTER CARDS
CHAPTER 8: ADDITIONAL
1. The capacitor must be selected based on intended use and
DESIGN TECHNIQUES application: decoupling, bypass, or bulk.
4. The inductance value of the lead lengths of radial and axial capacitors
must be included when determining use for a particular resonant
frequency. Include the total amount of equivalent series inductance
and equivalent series resistance internal to the capacitor (3.2.1).
10. When the power or ground trace and lead inductance are combined,
a higher impedance value will be presented between the component's
pin and its respective reference plane, which is undesirable. With
traces being inductive, a voltage gradient is developed between two
sources, creating undesirable RF development of common-mode
energy (3.2.4).
14. If the self-resonant frequency of the power and ground planes is the
same as the self-resonant frequency of the lumped total of all discrete
decoupling capacitors installed, there will be a sharp resonance
where these two frequencies meet. No longer will there be a wide
spectral distribution of decoupling (3.4.1).
19. Multilayer PCBs contain one or more pairs of voltage and ground
planes. These planes function as a low-inductance capacitor,
preventing the creation of RF currents generated from components
switching logic states. Multiple chassis ground connections to all
ground planes minimize voltage gradients between board, chassis,
and between/among board layers. These gradients also are a major
source of common-mode RF fields (3.5.1).
21. If the impedance of the loop is smaller than the rest of the system,
some fraction of high-frequency RF energy will transfer or couple to
the larger loop formed by the power distribution system. With this
situation, RF currents are developed in the loop structure and, hence,
higher EMI emissions (3.5.2).
22. Decoupling capacitors must be provided for devices with edges faster
than 2 ns and should be provided, placement wise, for every
component (3.5.3).
29. Capacitors can be used to shape the waveform of signal traces. The
capacitor, C, alters the signal edge (slew rate) by rounding the time
period the signal edge transition takes to change from logic state "0"
to logic state "1" (3.6.2).
32. Bulk capacitors must be used at all power connectors and at opposite
or far ends of the board. Also, bulk capacitors must be located at the
furthest location from the power entry connector. This is in addition to
all components that consume large amounts of DC voltage and
current. Bulk capacitors minimize DC voltage and current fluctuations
(dropout or droop) which cause degradation of circuit functions
(3.6.3).
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Table of Contents
Appendix A - Summary of Design Techniques
Appendix A
CHAPTER 1: Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
INTRODUCTION
CHAPTER 2: PRINTED by Mark I. Montrose
CIRCUIT BOARD BASICS
CHAPTER 3: BYPASSING IEEE Press 2000
AND DECOUPLING
CHAPTER 4: CLOCK Recommend this title?
CIRCUITS, TRACE
ROUTING, AND
TERMINATIONS
CHAPTER 5:
INTERCONNECTS AND I/O
CHAPTER 6:
ELECTROSTATIC
DISCHARGE PROTECTION
CHAPTER 7: BACKPLANES,
RIBBON CABLES, AND
DAUGHTER CARDS
CHAPTER 4: CLOCK CIRCUITS, TRACE ROUTING,
CHAPTER 8: ADDITIONAL
DESIGN TECHNIQUES AND TERMINATIONS
1. A transmission line is another word for PCB trace. A PCB is defined
as a rigid structure for supporting transmission lines sharing a
common substrate (4.1).
16. A trace that has many capacitive loads will slow down the velocity of
signal propagation. This delay in propagation may cause signal
integrity concerns (skew) to occur (4.4).
17. Components add capacitance to the trace route. The larger the value
of capacitance, the lower the impedance of the transmission line. A
lower impedance means that additional drive current is required
(Ohm's law), exacerbating EMI (4.4).
21. Reflections from signals on a trace are one source of RF noise within
a network. Reflections are observed when impedance discontinuities
exist in the transmission line. These discontinuities consist of (4.6)
Changes in trace width.
Improperly matched termination networks.
Lack of terminations.
T-stubs or bifurcated traces.
Vias between routing layers.
Varying loads and logic families.
Large power plane discontinuities.
Connector transitions.
Changes in impedance of the trace.
22. The PCB layout designer must determine if a physical trace route is
electrically long. If the trace is electrically long, termination may be
required (4.7).
23. If traces must be electrically long, the trace must be routed using
transmission line techniques (4.7).
27. Three phenomena by which planes and, hence, PCBs create EMI are
as follows (4.9):
Discontinuities in the image plane due to use of vias and jumping
clock traces between layers.
Peak surge currents injected into the power and ground network
(image planes) due to components switching signal pins at the
same time to propagate throughout the PCB.
Flux loss into the annular keep-out region of vias if 3-W routing is
not provided for the trace route. Distance separation of a trace
from a via must also conform to 3-W spacing.
28. Microstrip allows for faster transition of signal edges, while also
permitting a greater amount of RF current to radiate from the traces
(4.9.1).
30. If traces must jump between planes, ground vias must be used at
each and every layer jump to maintain image plane continuity (4.9.2).
31. The ground pin of a component can also be used as a ground via
(4.9.2).
34. To prevent crosstalk, the design and layout techniques listed below
are useful during PCB layout (4.10.2):
Group logic families according to functionality. Keep the bus
structure tightly controlled.
Minimize the physical distance between components during
placement.
Minimize parallel routed trace lengths.
Locate components away from I/O interconnects and other areas
susceptible to data corruption and coupling.
Provide termination for impedance-controlled traces, or traces rich
in RF harmonic energy.
Avoid routing of traces parallel to each other. Provide sufficient
separation between traces to minimize inductive coupling effects.
Route adjacent layers (microstrip or stripline) orthogonally. This
prevents capacitive coupling between adjacent layers.
Reduce signal-to-ground reference distance separation.
Reduce trace impedance and signal drive level.
Isolate routing layers that must be routed in the same axis by a
solid planar structure (typical of backplane stackup assignments).
Partition or isolate high noise emitters (clocks, I/O, high-speed
interconnects, etc.) onto different layers within the stackup
assignment.
Provide a band-limiting filter on specific transmission lines to
prevent RF frequencies from coupling between source and victim
traces.
35. The 3-W rule minimizes crosstalk within a PCB per the following
(4.11):
To minimize coupling between transmission lines or PCB traces.
The rule states that the distance separation between traces must
be three times the width of a single trace measured from centerline
to centerline. Otherwise stated, the distance separation between
two traces, edge to edge, must be greater than two times the width
of a single trace.
Use of the 3-W rule is mandatory for only high-threat signals, such
as clock, differential pairs, video, audio, reset line, or other system-
critical nets. Not all traces within a PCB have to conform to 3-W
routing. It is important to determine which traces are to be
classified as critical.
Use of the 3-W rule should not be restricted to clock or periodic
signal traces. Differential pairs (balanced, analog, ECL, and similar
sensitive nets) are also prime candidates for 3-W. The distance
between paired traces must be 1-W for the differential traces and
3-W from each of the differential pair to adjacent traces (4.11).
39. The need to terminate is based on several design criteria. The most
important criterion is the existence of an electrically long trace. When
a trace is electrically long, or when the length exceeds one-sixth of
the electrical length of the edge transition time, the trace requires
termination. Even if a trace is short, termination may still be required if
the load is capacitive or highly inductive to prevent ringing (4.13).
40. The easiest way to terminate is to use resistive elements. Two basic
configurations exist; source or end. Several methodologies are
available for these configurations. Refer to the referenced section for
details of implementation:
Series termination resistor (4.13.1).
End termination requirements (4.13.2).
Parallel termination resistor (4.13.3).
Thevenin termination (4.13.4).
AC (RC) termination (4.13.5).
Diode termination (4.13.6).
Differential signals (4.13.7).
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Table of Contents
Appendix A - Summary of Design Techniques
Appendix A
CHAPTER 1: Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
INTRODUCTION
CHAPTER 2: PRINTED by Mark I. Montrose
CIRCUIT BOARD BASICS
CHAPTER 3: BYPASSING IEEE Press 2000
AND DECOUPLING
CHAPTER 4: CLOCK Recommend this title?
CIRCUITS, TRACE ROUTING,
AND TERMINATIONS
CHAPTER 5:
INTERCONNECTS AND
I/O
CHAPTER 6:
ELECTROSTATIC
DISCHARGE PROTECTION
CHAPTER 7: BACKPLANES,
CHAPTER 5: INTERCONNECTS AND I/O
RIBBON CABLES, AND
DAUGHTER CARDS 1. Most RF emissions in I/O circuitry are generated from (5.0)
CHAPTER 8: ADDITIONAL
DESIGN TECHNIQUES Coupling of common-mode RF energy to I/O interconnects.
Power plane switching noise coupling into I/O circuits and cables.
Clock signals coupling to I/O cables through both conductive and
radiated modes.
Lack of data line filtering on signals traces (both common mode
and differential mode).
Improper connection of various ground methodologies (chassis,
signal, frame, digital, and analog).
Use of unacceptable I/O connectors (plastic versus metal or
unshielded versus shielded).
Ground potential difference between two circuits.
3. Driver and control logic must be located as close to the I/O connector
as possible in order to minimize routed trace length and RF coupling
of both common- and differential-mode currents to other signal lines
(5.0).
10. Noisy and quiet areas must be isolated through use of a partition or
moat. A moat is an absence of copper on all layers: power, ground
and signal. Connection between isolated areas is accomplished using
data line filters, isolation transformers, or a bridge (5.2).
12. When providing isolation between areas, care should be taken that all
trace routing occurs in the common connection area and does not
cross the moat (5.2).
13. Data line filters, ferrite beads, or isolation transformers are used for
connection between noisy and quiet areas (5.2.1).
14. Two areas of concern for selection of components used in I/O circuits
for isolation purposes are (5.2.1):
Proper bandwidth filtering.
Peak surge voltage capabilities for electrostatic discharge
protection.
16. All copper layers in the area between a data line filter and connector
should be removed. Removing the copper prevents coupling between
filtered and filtered signals (5.2.1).
21. All I/O brackets should be grounded to chassis ground unless single-
point or isolated grounding is required. Also, this I/O bracket can be
connected to the ground planes of the PCB, if the design permits.
Provisions should be made for multiple connections from the ground
plane to the bracket. This minimizes the aspect ratio between ground
points for optimal loop control. If no external I/O connections exist on
the adapter board, the chassis-mounting bracket must be isolated
from signal ground (5.3.3).
22. For local area networks, data signals must be filtered with common-
mode chokes if the protocol permits. Provision must be made for
complete isolation from digital switching noise from the main PCB
using a moat (5.4).
23. For video, a filter must be provided between the controller and I/O,
with the filter as close to the connector as possible. Provide isolated
analog ground from digital ground through a ferrite bead if the device
permits this type of ground connection. All analog traces and
components must be connected over the analog isolated planes (5.5).
24. Constant trace impedance must be maintained for all signals routed in
the video section. These traces may be a different impedance value
from other traces on the assembly. A design technique for
implementation involves removal of a reference plane (used for trace
impedance), allowing the trace to be impedance controlled from
another reference plane located at a further distance away within the
stackup (5.5).
26. Audio interfaces are partitioned into three areas: digital, analog, and
audio. The digital to analog connection must be made through a
bridge located directly under the audio controller or as close to it as
possible. All traces between digital and analog must be routed
through this bridge, including analog power. The analog section must
be isolated from the audio section by a second moat and additional
data line filters. Audio ground must not be connected to chassis or
analog ground. In addition, the signal return on unshielded audio
cables must not be connected to analog or chassis ground (5.6).
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Table of Contents
Appendix A - Summary of Design Techniques
Appendix A
CHAPTER 1: Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
INTRODUCTION
CHAPTER 2: PRINTED by Mark I. Montrose
CIRCUIT BOARD BASICS
CHAPTER 3: BYPASSING IEEE Press 2000
AND DECOUPLING
CHAPTER 4: CLOCK Recommend this title?
CIRCUITS, TRACE ROUTING,
AND TERMINATIONS
CHAPTER 5:
INTERCONNECTS AND I/O
CHAPTER 6:
ELECTROSTATIC
DISCHARGE
PROTECTION
CHAPTER 7: BACKPLANES,
CHAPTER 6: ELECTROSTATIC DISCHARGE
RIBBON CABLES, AND
DAUGHTER CARDS PROTECTION
CHAPTER 8: ADDITIONAL
DESIGN TECHNIQUES 1. Electrostatic discharge (ESD) is a natural phenomenon that affects
materials of different potential. This difference in potential occurs as a
result of accumulated electric charges. Electric charges produce an
electromagnetic field, which in turn can cause disruption to electrical
equipment (6.16.2).
4. Four basic failure modes from an ESD event are related to PCBs
(6.3):
Upset or damage caused by ESD current flowing directly through a
vulnerable circuit.
Upset or damage caused by ESD current flowing in the ground
circuit.
Upset caused by electromagnetic field coupling (indirect
discharge).
Upset caused by a pre-discharged (static) electric field.
6. The majority of direct ESD problems are cable related. The solution is
straightforwardprotect all lines, including signal, power, and the
ground path (6.4).
For components:
Spark gaps. Spark gaps are sharply pointed triangles created
within the copper of microstrip layers, aimed at each other. One
trace is connected to one triangle, and ground is connected to the
other. This is a poor technique for ESD control and should not be
used with high-technology devices.
High-voltage capacitors. High-voltage disc-ceramic capacitors
shunt ESD energy present on a signal line to ground.
Avalance Diodes (Tranzorbs[1]). Avalance diodes (tranzorbs) are
semiconductor devices specifically designed for transient voltage
suppression applications.
LC filters. A LC filter is a combination of both an inductor and a
capacitor connected in a desired configuration to chassis ground.
Non-ESD sensitive components must be selected, such as diode-
protected CMOS or TTL for use in circuits susceptible to
disruption.
Incorporate bypass capacitors with a high self-resonant frequency
between power and ground must be used.
Note that ferrite material, beads, and filters provide excellent
attenuation of ESD currents, in addition to enhancing suppression
of radiated emissions.
8. Install a guard band (both top and bottom layers) around the
periphery of the board to prevent ESD coupling into logic areas due to
handling of the board (6.5).
Connect the guard band to chassis ground every 1/2 in. (0.5 mm)
along the perimeter. This provides a low-impedance path for ESD
energy to dissipate to. Do not use solder mask on the guard band.
Do not incorporate the guard band as a complete circle around all
edges sides of the PCB. Ensure that a break is provided within the
band to prevent the band from becoming a loop antenna.
[1]
Tranzorb is a trademark of General Semiconductor.
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Table of Contents
Appendix A - Summary of Design Techniques
Appendix A
CHAPTER 1: Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
INTRODUCTION
CHAPTER 2: PRINTED by Mark I. Montrose
CIRCUIT BOARD BASICS
CHAPTER 3: BYPASSING IEEE Press 2000
AND DECOUPLING
CHAPTER 4: CLOCK Recommend this title?
CIRCUITS, TRACE ROUTING,
AND TERMINATIONS
CHAPTER 5:
INTERCONNECTS AND I/O
CHAPTER 6:
ELECTROSTATIC
DISCHARGE PROTECTION
CHAPTER 7:
BACKPLANES, RIBBON
CHAPTER 7: BACKPLANES, RIBBON CABLES, AND
CABLES, AND DAUGHTER
CARDS DAUGHTER CARDS
CHAPTER 8: ADDITIONAL
DESIGN TECHNIQUES 1. Proper pin assignment will maintain ground loop control. A large
number of ground pins help prevent crosstalk, maintain impedance
control, reduce radiated emissions, and provide for enhanced signal
quality performance (7.1).
10. With many connector slots, there will be a larger value of lumped
distributed capacitance presented to the circuit. With additional
capacitance, degradation of signal quality can occur, sometimes to
the point of nonfunctionality (7.5).
11. The interface connectors chosen must be appropriate for the edge
rate transition of the desired signal, along with proper impedance
matching between backplane and adapter cards (7.5).
13. During layout, sufficient real estate must be present to apply filtering
and termination for both signal traces and I/O interconnects (7.6).
14. Vias must be avoided when routing signal traces between planes for
high-threat signals. High-threat signals are defined as reset, clock,
audio, video, analog, high-speed transmission of data, and related
signals. Each via adds approximately 13 nH inductance and 2 pF to
the trace route (7.7).
19. To minimize crosstalk between traces and planes, the 3-W rule or
separate parallel traces is required (7.9).
22. Use of a shield partition is desired when several ribbon cables are
stacked against each other. Long cable routes allow crosstalk to be
developed (7.9).
23. For signal pair routing, twisting the traces using an even number of
twists enhances signal integrity. This is extremely difficult and
generally not practical to implement. This technique is currently
outdated and rarely used in high-technology products (7.9).
24. For one or two layer backplanes, a ground trace must be routed
parallel to each signal trace pair (7.10).
25. Signal traces must not be routed across through-hole connector pins
that overlap each other. This routing method prevents the image
planes from providing a low-impedance path for RF return currents.
Return currents must travel around the long edge of the I/O connector
to complete its path, thus maximizing generation of RF common-
mode noise (7.11).
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Table of Contents
Appendix A - Summary of Design Techniques
Appendix A
CHAPTER 1: Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
INTRODUCTION
CHAPTER 2: PRINTED by Mark I. Montrose
CIRCUIT BOARD BASICS
CHAPTER 3: BYPASSING IEEE Press 2000
AND DECOUPLING
CHAPTER 4: CLOCK Recommend this title?
CIRCUITS, TRACE ROUTING,
AND TERMINATIONS
CHAPTER 5:
INTERCONNECTS AND I/O
CHAPTER 6:
ELECTROSTATIC
DISCHARGE PROTECTION
CHAPTER 7: BACKPLANES,
RIBBON CABLES, AND CHAPTER 8: ADDITIONAL DESIGN TECHNIQUES
DAUGHTER CARDS
CHAPTER 8:
ADDITIONAL DESIGN
TECHNIQUES
Localized Planes (8.1) Localized Planes (8.1)
20-H Rule (8.2)
Trace Routing for Corners
(8.3)
1. During component placement, oscillators, crystals, and support
Selecting Ferrite
Components (8.4)
circuitry (buffers, drivers, etc.) must be located over a single localized
Grounded Heatsinks (8.5) plane. This plane is usually at ground potential, but can be at voltage
Lithium Battery Circuits (8.6)
BNC Connectors (8.7) potential. Locate clock generation circuits near a ground stitch
Creepage and Clearance
Distances (8.8) location.
Current-Carrying Capacity
of Copper Traces (8.9)
Film and Manufacturing
Issues (8.10)
2. When using localized planes, the following must be observed:
Locate clock circuitry and localized plane next to an adjacent
ground stitch location and bond the localized plane to chassis
ground, if ground is the chosen potential.
In addition, connect the localized ground plane, if ground is the
chosen potential, to the main 0V-reference plane using vias.
Include support circuitry, drivers, buffers, and resistors in this
localized plane area.
3. When using the 20-H rule, any traces on the adjacent signal routing
plane, located over the absence of copper area, must be rerouted
inward to be physically adjacent to a solid reference plane (voltage or
ground), with no exceptions allowed.
3. The main reason for not designing a PCB with right-angle corners lies
with manufacturing. When traces are etched, the chemicals start at
the corners. During the etching cycle, the corner will be etched back a
certain amount, thus causing the physical dimension to decrease.
This smaller trace width may not be able to carry current and can self-
destruct under maximum load conditions. Vendors thus cannot
manufacture a PCB with right-angle corners.
2. For applications where the shell of the BNC connector is signal return
and is not used as a RF return shield, the shell of the BNC connector
must be connected through a low-impedance path to the 0V-
reference of the signal return circuit. Do not connect the ground (outer
barrel) pin of the BNC connector to the I/O isolated (quiet ground)
area.
4. Pigtails are not to be used under any condition to connect the shell or
ground pin of the BNC connector to chassis ground or to any other
ground in the system, unless system functionality mandates this
ground connection.
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Table of Contents
Appendix B - International EMC Requirements
Appendix B
BRIEF SUMMARY OF Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
NORTH AMERICAN EMC
REQUIREMENTS by Mark I. Montrose
BRIEF SUMMARY OF
IEEE Press 2000
WORLDWIDE EMC
REQUIREMENTS
FCC/ INDUSTRY CANADA Recommend this title?
EMISSION LIMITS
EMISSIONSEN 55011
INDUSTRIAL SCIENTIFIC AND
MEDICAL (ISM) EQUIPMENT
SUMMARY OF CURRENT
INTERNATIONAL IMMUNITY
REQUIREMENTS
Digital computing products are classified into two categories: Class A and
B. The FCC and Industry Canada use the same definition.
Class A:
A digital device that is marketed for use in a commercial, industrial, or
business environment, exclusive of a device which is marketed for use
by the general public or is intended to be used in the home.
Class B:
A digital device that is marketed for use in a residential environment,
notwithstanding its use in a commercial, industrial, or business
environment. Examples of such devices include, but are not limited to,
personal computers, calculators, and similar electronic devices that are
marketed for use by the general public.
If a product contains digital circuitry and has a clock frequency greater than
9 kHz, it is defined as a digital device and is subject to the rules and
regulations of the FCC. Electromagnetic Interference (EMI) may occur as a
result of both time domain and frequency domain components of digital
and analog circuits. These products are subject to domestic and
international regulatory requirements.
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Table of Contents
Appendix B - International EMC Requirements
Appendix B
BRIEF SUMMARY OF NORTH Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
AMERICAN EMC
REQUIREMENTS by Mark I. Montrose
BRIEF SUMMARY OF
IEEE Press 2000
WORLDWIDE EMC
REQUIREMENTS
Basic Standards Recommend this title?
Generic Standards
Generic Standards (Sample
List)
Product Family Standards
International Definition,
Defined within EN 55022
and CISPR-22
FCC/ INDUSTRY CANADA
EMISSION LIMITS
EMISSIONSEN 55011
INDUSTRIAL SCIENTIFIC AND BRIEF SUMMARY OF WORLDWIDE EMC
MEDICAL (ISM) EQUIPMENT
SUMMARY OF CURRENT
INTERNATIONAL IMMUNITY
REQUIREMENTS
REQUIREMENTS
Two routes to compliance are available: self-certification and Technical
Construction File (TCF). Self-certification is the preferred route because of
its simplicity and faster time to market. This route depends on the
availability of test standards that have been published in the Official
Journal of the European Union (OJ), applicable to the product to be
evaluated. In many cases, a specific product category may not exist.
When a specific standard does not exist, or it is not possible to test all the
possible configurations because of a large number of variants, alternate
construction features, user options, and the like, a Technical Construction
File (TCF) may be a better choice. The caveat is that if use of a TCF is
required, mandatory assessment and approval must be issued by a
European Competent Body, certified by a European National Authority. A
National Authority is authorized by a country's government to oversee the
licensing of Competent Bodies and Notified Bodies. Notified Bodies were
established to issue approvals for telecommunication equipment.
Competent Bodies assess products to the EMC Directive and various
product safety directives. A Competent Body is issued a license to grant
approval to a particular range and type of product that they are considered
technologically knowledgeable to assess. Assessment must occur within
mainland Europe. Competent Bodies may, however, own and operate field
offices around the world.
Three tiers of standards are detailed in the EMC Directive: basic, generic,
and product family.
Basic Standards
Basic standards are referenced within generic and product family
standards as a basis for performing a particular test. The standards include
most IEC and CISPR standards. These standards are dedicated to aspects
of EMC that are of general interest to all committees working on, creating,
or developing other standards. This development work includes product
family standards. It is common for a product family standard to take the
appearance of a generic standard. Specific operational modes and
configurations are detailed, including performance criteria and test levels.
Generic Standards
Generic standards were developed for industry sectors for which no
product family standard is available. Generic standards encompass all
environments and applications, and are intended to represent the essential
requirements of a directive. These standards are divided into two basic
requirements: emissions and immunity. Environment is defined as
residential, commercial, light industrial, or heavy industrial.
Class A ITE:
Class A ITE is a category of all other ITE which satisfies the Class A
ITE limits but not the Class B ITE limits. Such equipment should not be
restricted in its sale but the following warning shall be included in the
instructions for use:
Class B ITE:
Class B ITE is a category of apparatus, which satisfies the Class B ITE
disturbance limits. Class B ITE is intended primarily for use in the
domestic environment and may include
equipment with no fixed place of use; for example, portable
equipment powered by built-in batteries;
[1]
EN 55022:1995 (CISPR 22:1993). Limits and methods of measurement
of radio disturbance characteristics of information technology equipment.
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Table of Contents
Appendix B - International EMC Requirements
Appendix B
BRIEF SUMMARY OF NORTH Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
AMERICAN EMC
REQUIREMENTS by Mark I. Montrose
BRIEF SUMMARY OF
WORLDWIDE EMC IEEE Press 2000
REQUIREMENTS
FCC/ INDUSTRY CANADA Recommend this title?
EMISSION LIMITS
International Emissions
Limits SummarySample
List
EMISSIONSEN 55011
INDUSTRIAL SCIENTIFIC AND
MEDICAL (ISM) EQUIPMENT
SUMMARY OF CURRENT
INTERNATIONAL IMMUNITY FCC/ INDUSTRY CANADA EMISSION LIMITS
REQUIREMENTS
For FCC and Industry Canada, the frequency range to be measured is based on the highest fundamental
internally generated clock frequency per the following list:
Note (1) The dash between two numbers (e.g., 66-56) means that the limit decreases with the
logarithm of frequency.
(2) EN 55013 has other limits for emissions from receivers and televisions.
(3) Absorbing clamp measurement is for the frequency range of 30300 MHz only.
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Table of Contents
Appendix B - International EMC Requirements
Appendix B
BRIEF SUMMARY OF NORTH Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
AMERICAN EMC
REQUIREMENTS by Mark I. Montrose
BRIEF SUMMARY OF
WORLDWIDE EMC IEEE Press 2000
REQUIREMENTS
FCC/ INDUSTRY CANADA Recommend this title?
EMISSION LIMITS
EMISSIONSEN 55011
INDUSTRIAL SCIENTIFIC
AND MEDICAL (ISM)
EQUIPMENT
Classification of ISM
Equipment
Line Conducted Emissions
SUMMARY OF CURRENT
EMISSIONSEN 55011 INDUSTRIAL SCIENTIFIC AND
INTERNATIONAL IMMUNITY
REQUIREMENTS MEDICAL (ISM) EQUIPMENT
For all other EN 55 XXX specifications, refer to the International Emissions
Limits Summary.
Group 1 [a]
Group 2
Frequency Quasi- Average Quasi-peak Average
band (MHz) peak
0.150.50 79 66 100 90
0.505 73 60 86 76
530 73 60 90 80
Decreasing Decreasing
with with
logarithm of logarithm of
frequency to frequency to
70 60
[a]
Mains terminal disturbance voltage limits for Group 2, Class A
equipment requiring input current greater than 100A are under
consideration.
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Table of Contents
Appendix B - International EMC Requirements
Appendix B
BRIEF SUMMARY OF NORTH Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
AMERICAN EMC
REQUIREMENTS by Mark I. Montrose
BRIEF SUMMARY OF
WORLDWIDE EMC IEEE Press 2000
REQUIREMENTS
FCC/ INDUSTRY CANADA Recommend this title?
EMISSION LIMITS
EMISSIONSEN 55011
INDUSTRIAL SCIENTIFIC AND
MEDICAL (ISM) EQUIPMENT
SUMMARY OF CURRENT
INTERNATIONAL
IMMUNITY
REQUIREMENTS
Comprehensive List of
SUMMARY OF CURRENT INTERNATIONAL IMMUNITY REQUIREMENTS
Immunity Standards
Performance Criteria for
Immunity Tests To be able to certify compliance to the EMC Directive, 89/336/EEC, manufacturers must construct
products that meet not only emissions requirements, but also immunity levels, or protection against
harmful disruption from other electronic equipment. Currently, only Europe requires immunity testing.
Since the IEC and CISPR are international organizations, the scope of their work is implememted
throughout the world. CENELEC adopts basic standards developed by both IEC and CISPR, and
publishes them as harmonized standards to meet the EMC Directive. The European harmonized
document and IEC publication numbers are similar. The IEC standard is prefixed with IEC 1000-4-X.
When referenced as a European harmonized document, this number is changed to EN 61000-4-X.
IEC standards for immunity are provided in the IEC 1000-4-X series. This series of standards describes
the test and measurement methods detailed within the basic standards. Basic standards are specific to
a particular type of EMI phenomenon, not a specific type of product. This series covers the following:
Terminology.
Instrumentation.
The most commonly used immunity standards adopted or recommended by CENELEC, the
international IEC 1000-X series of standards were reissued using an EN 61000-X specification number.
The EN 61000-4-X series of immunity specifications are as follows:
Standard Description
EN 61000-4- Electrostatic discharge (ESD)
2
EN 61000-4- Radiated electromagnetic field
3
EN 61000-4- Electrical Fast Transient (EFT)/Burst
4
EN 61000-4- Surge
5
EN 61000-4- Conducted disturbance by RF fields
6
EN 61000-4- General guide on harmonics and interharmonics measurements and
7 instrumentation (not a standard; procedure only)
EN 61000-4- 50/60 Hz magnetic field
8
EN 61000-4- Pulsed magnetic field
9
EN 61000-4- Oscillatory magnetic field
10
EN 61000-4- Voltage dips and interruption
11
EN 61000-4- Oscillatory waves "ring wave"
12
EN 61000-4- Oscillatory waves 1 MHz
13
EN 61000-4- Harmonics, interharmonics, and main signaling
14
EN 61000-4- Voltage fluctuations
15
EN 61000-4- Unbalance in three-phase mains
27
EN 61000-4- Variation of power frequency
28
Note Several EN 61000-4-x specifications have never been written or released. Titles have been
issued and working groups assigned. When performing compliance testing, verify which
standards are mandatory for your product along with required test levels and performance
criteria.
PERFORMANCE CRITERION B: The apparatus shall continue to operate as intended after the test. No
degradation of performance or loss of function is allowed below a performance level specified by the
manufacturer when the apparatus is used as intended. In some cases, the performance level may be
replaced by a permissible loss of performance. During the test, degradation of performance is, however,
allowed. No change of actual operating state or stored data is allowed. If the minimum performance
level or the permissible performance loss is not specified by the manufacturer, then either of these may
be derived from the product description and documentation (including leaflets and advertising) and what
the user may reasonable expect from the apparatus if used as intended.
PERFORMANCE CRITERION C: Temporary loss of function is allowed, provided the loss of function is
self-recoverable or can be restored by the operation of the controls.
[b]
Additional test requirements exist but are not detailed above. Refer to EN 55082-2 for details.
[c]
Severity levels and frequency ranges are subject to change. Consult test requirements for current
values in effect at date of testing and certification.
[d]
Additional test requirements exist but are not detailed above. Refer to EN 50082-2 for details.
CM: Common-mode
DM: Differential-mode
Performance criterion
Level A: The apparatus shall continue to operate as intended. No degradation of performance or
loss of function is allowed.
Level B: The apparatus shall continue to operate as intended after the test.
Level C: Temporary loss of function is allowed, provided the loss of function is self-recoverable.
Open table as spreadsheet
EN 61000- EN EN 61000-4-
4-6 61000-4- 11 Voltage EN 61000-3-
Conducted 8 Dips, 2 Power
RF Radiated Interruption, Line EN 61000-3-
SPECIFICATION Immunity Magnetic Variation Harmonics 3 Flicker
EN 50082-1 0.15-80 3 A/m +10%, 15% Required for Required for
MHz (A) specific specific
products. products.
Generic limit 3V 50 Hz 30%, 10ms Consult Consult
(B) standard for standard for
test details. test details.
light industrial 1 kHz 60% ,100ms (Emissions (Emissions
[c] requirement) requirement)
equipment (C)
80% AM, 95%,
5000ms (C)
150
Source
Criteria A Criteria A Criteria (x)
above
EN 50082-2 0.1580 30 A/m +10%, 15% Not required Not required
MHz (A)
Generic limit 10 V 50 Hz 30%, 10ms
(B)
heavy industrial 80% AM, 60% ,100ms
[d]
equipment (C)
1 kHz 95%,
5000ms (C)
150
Source
Criteria A Criteria A Criteria (x)
above
EN 55014-2 0.15230 Not yet Not yet Not yet Not yet
MHz proposed proposed proposed proposed
Appliances and Category II
power tools
0.1580
MHz
Category IV
1 V, Signal
3 V, Power
Criteria A
EN 60601-2 Not yet Not yet Not yet Not yet Not yet
proposed proposed proposed proposed proposed
Medical devices
[a]
Severity levels and frequency ranges are subject to change. Consult test requirements for current
values in effect at date of testing and certification.
[b]
Additional test requirements exist but are not detailed above. Refer to EN 55082-2 for details.
[c]
Severity levels and frequency ranges are subject to change. Consult test requirements for current
values in effect at date of testing and certification.
[d]
Additional test requirements exist but are not detailed above. Refer to EN 50082-2 for details.
Performance criterion
Level A: The apparatus shall continue to operate as intended. No degradation of performance or
loss of function is allowed.
Level B: The apparatus shall continue to operate as intended after the test.
Level C: Temporary loss of function is allowed, provided the loss of function is self-recoverable.
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Table of Contents
Appendix C - The Decibel
Appendix C
Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
by Mark I. Montrose
IEEE Press 2000
Get MathML
Get MathML
Get MathML
Get MathML
Most regulatory limits are described in V/m. For example, 100 V/m limit
translates to 40 dBV/m. The equations that describe this conversion are
Get MathML
Conversions between units are easy. For example:
Get MathML
Five commonly used variations exist for the decibel. An example of this
variation follows to present the concept of dBs using different units.
Get MathML
Several pitfalls are related to use of the decibel, owing to the impedance of
the system. Because not all systems have the same impedance, different
values will be obtained under this situation.
Get MathML
Get MathML
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Table of Contents
Appendix D - Conversion Tables
Appendix D
Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
by Mark I. Montrose
IEEE Press 2000
Suffix Refers to
dBm 1 milliwatt
dBW 1 watt
dBW 1 microwatt
dBV 1 volt
dBmV 1 millivolt
dBV 1 microvolt
dBA 1 amp
dBA 1 microamp
Ratio V or I in dB P in dB
6 120 60
10
5 100 50
10
4 80 40
10
3 60 30
10
2 40 20
10
10 20 10
9 19.08 9.54
8 18.06 9.03
7 16.9 8.45
6 15.56 7.78
5 13.98 6.99
4 12.04 6.02
3 9.54 4.77
2 6.020 3.01
1 0 0
-20 -10
-1
10
-2 -40 -20
10
-3 -60 -30
10
100 10
10
10
5
80 10
8
10
4
60 10
6
10
3
40 10
4
10
2
30 10
3 32
20 10
2 10
10 10.0 3.2
6 4.0 2.0
3 2.0 1.4
0 1.0 1.0
-3 0.50 0.71
-6 0.25 0.50
-10 0.10 0.32
-20 10
-2 0.10
-30 10
-3 0.03
-40 10
-4
10
-2
-60 10
-6
10
-3
-80 10
-8
10
-4
-100 10
-10
10
-5
-120 10
-12
10
-6
Conversion of dBV,
dBmV, and dBV
Open table as
spreadsheet
V/m dBV/m 2 2
mW/cm dBmW/cm
-6 0 -16 -155.8
1.00 10 2.67 10
-5 20 -14 -135.8
1.00 10 2.67 10
-4 40 -12 -115.8
1.00 10 2.67 10
-3 60 -10 -95.8
1.00 10 2.67 10
-2 80 -8 -75.8
1.00 10 2.67 10
-1 100 -6 -55.8
1.00 10 2.67 10
1.00 120 2.67 10
-4 -35.8
+1 140 -2 -15.8
1.00 10 2.67 10
+2 160 2.67 -4.2
1.00 10
+3 180 267 -24.2
1.00 10
+6 6 -15 -149.7
1.00 10 1.06 10
+6 12 -15 -143.7
2.00 10 4.24 10
+6 15 -15 -140.2
6.00 10 9.55 10
+6 18 -14 -137.7
8.00 10 1.70 10
FrequencyWavelengthSkin Depth
Open table as spreadsheet
FrequencyWavelength Conversion
Open table as spreadsheet
= wavelength, f = frequency
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Table of Contents
Bibliography and - Additional Reference Material
Bibliography and
Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
by Mark I. Montrose
IEEE Press 2000
Brown, R, et al. 1973. Lines, Waves and Antennas. New York: Ronald
Press Co.
Condon, G. P. No date. Printed Circuit Board and Wiring Design for EMI
Control. West Conshohocken, PA: R&B Enterprises.
Grasso, C. 1988. "Printed Circuit Board Design Concepts for the Control
of EMC." Proceedings of EMC EXPO 89, C1.15.
Hsu, Tony. 1991. "The Validity of Using Image Plane Theory to Predict
Printed Circuit Board Radiation." Proceedings of the IEEE International
Symposium on Electromagnetic Compatibility. New York: IEEE, pp. 58
60.
Hubing, T., et al. 1999. "Power Bus Reduction Using Power Islands in
Printed Circuit Board Designs." Proceedings of the IEICE International
Symposium on Electromagnetic CompatibilityEMC'99, Tokyo, pp. 14.
Motorola, Inc. 1996. Low Skew Clock Drivers and Their System Design
Considerations. #AN1091.
Oka, N., C. Miyazaki, and S. Nitta. 1998. "Radiation from a PCB with
Coupling between a Low Frequency and a Digital Signal Traces."
Proceedings of the IEEE International Symposium on Electromagnetic
Compatibility. New York: IEEE, pp. 635640.
Sasaki, H., et al. 1999. "A New Decoupling Technique for Suppressing
Radiated Emissions Arising from Power Bus Resonance of Multilayer
PCBs." Proceedings of the IEICE International Symposium on
Electromagnetic CompatibilityEMC'99, Tokyo, pp. 1720.
Violette, J. L. N., et al. 1991. "EMI Control in the Design and Layout of
Printed Circuit Boards." EMC Technology 5 (2): 1932.
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Table of Contents
Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
O
P
Q
R
Index
S
T
U
V
Symbols & Numbers
W
/20, 59
20-H rule, 214
3-W rule, 136
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Table of Contents
Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
Index
O
P
Q
R
A
S Absence of copper, 155
T
U AC plane, 195
V
W AC network
definition, 147
propagation delay, 147
time constant, 147
AC Termination, 147
Ampere's Law, 15, 17
Amplitude, 4
Analog components, 158
Anti resonance, 68, 75
Aspect ratio, 48
Asymmetrically placed components, 23, 24
Audio, 171
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Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
Index
O
P
Q
R
B
S Backplane
T
U
capacitive loading, 197
V connector slots, 200
W
construction, 195
crosstalk, 204
ground slots, 207
impedance control, 197
interboard coupling, 197
interconnects, 200
layer stackup, 199
mechanicals, 202
signal integrity, 196
signal routing, 230
terminations, 203
Backward crosstalk, 132
Base material, 243
Basic standards, 7, 274
Bead-on-leads, 224
Bifurcated traces, 122, 203
BNC connectors, 232
Bridging, 157
Bulk capacitors
definition, 66
selection of, 94
Buried capacitance, 79
Bypass capacitor
definition, 66
I/O connector, 161
selection of, 89
signal trace, 56
Bypassing
definition, 65
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Table of Contents
Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
O Index
P
Q
R
S C
T
U Cable braid
V bypassing RF energy, 171
W
Cable radidation
cause of energy development, 162
Capacitance
buried, 79
calculation of, 7778
distributive, 79, 113
efficiency, 78
parasitics, 72
power and ground planes, 79, 81
relative permittivity, 77
Capacitive
bypassing for signal traces, 56
coupling, 132
loading, 112
Capacitor
common-mode decoupling, 231
Capacitors
dielectric material, 69, 72
energy storage, 69
how to select the right value, 89
impedance, 68, 72
lead inductance, 82
pad connection, 88
parallel placement, 75
physcial characteristics, 68
power and ground planes, 7778
resonance, 71
retrofit, 84
selection, 89
self-resonance, surface mount, 74
self-resonance, through-hole, 72
standard placement, 85
CENELEC. See Committee for European Electrotechnical Standardization,
7
Chassis
ground, 200
Plane, 195, 199
Clearance distance, 233
Closed-loop circuit, 17
Code of the Federal Register, 5
Committee for European Electrotechnical Standardization, 7
Common-mode
current, 41
decoupling capacitor, 231
Competent Bodies, 274
Component
behavior, 14
placement, 114
radiation, 212
selection, 60
Conducted emissions
definition, 1
Conducted immunity
definition, 2
Connector pinout assignment, 194
Connector slots, 200
Connectors
BNC, 232
pigtails, 232
Containment
definition, 1
Corners
frequency domain analysis, 223
right-angle, 220
time domain analysis, 221
Creepage distance, 233
Critical frequency, 59
Crosstalk
backplanes, 204
backward, 132
capacitive coupling, 132
definition, 131
forward, 132
inductive coupling, 132
layout techniques to prevent, 134
Current rating of traces, 238
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Table of Contents
Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
Index
O
P
Q
R
D
S Daisychaining, 122
T
U Data line filters, 156
V
W
use in bridging, 156, 160, 162
Daughter cards, 193
Decoupling, 65
capacitor definition, 65
localized, 213
power and ground planes, 76
selection of, 89
Delta-I noise, 75
Device capacitive overhead, 61
Dielectric constant, 111
Differential signaling, 124, 149
Differential traces, 106
broadside coupled, 109
edge-edge coupling, 109
impedance, 107
microstrip/stripline, 106
Differential-mode
current, 40
Digital devicedefinition, 6
Dimensions, 4
Diode network
definition, 147
Direct dischargeESD, 177
Double-sided stackup, 24
Drain wire, 155
Dual stripline
characteristic impedance, 105
intrinsic capacitance, 105
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Table of Contents
Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
O Index
P
Q
R
S E
T
U
ECL. See emitter-coupled logic
V
W
Eddy currents, 46
Edge transition
calculating actual value, 63
Eight-layer stackup, 33
Electrically long trace, 116, 117
calculating, 117119
Electromagnetic compatibility
definition, 1
Electromagnetic field coupling, 179
Electromagnetic interference
definition, 1
Electromagnetic wave
propagation, 111
Electrostatic discharge
definition, 2
Electrostatic discharge, 2, 175
Elements of the EMC environment, 2
Embedded microstrip
characteristic capacitance, 103
characteristic impedance, 103
coated, 102
dielectric constant, 103
topology, 102
EMC. See electromagnetic compatibility
EMI. See electromagnetic interference
Emissions, 4
Emitter-coupled logic, 99
End termination, 144
Equivalent series inductance, 69
Equivalent series resistance, 69
ESD
circuit layout, 186
component damage, 176
design techniques, 180
direct discharge, 177
electromagnetic field coupling, 179
failure modes, 176
multilayer PCB, 183
operational disruption, 176
single- and double-sided assemblies, 181
system level protection, 188
ESD. See electrostatic discharge
ESL. See equivalent series inductance
ETSI. See European Telecommunications Standards Institute
European Telecommunications Standards Institute
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Table of Contents
Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
Index
O
P
Q
R
F
S Faraday partition, 199
T
U Faraday's Law, 15
V
W FCC. See Federal Communications Commission
Federal Communications Commission, 5, 273
Fence, 153, 230
Ferrite material, 224
applications, 224
bias, 227
environment, 227
resistivity, 227
Field transfer coupling, 197
Film, 241
Filtering
capacitive, 159
ferrite material, 159
inductive, 159
Flame retardant requirement, 244
Flammability ratings, 244
Flux cancellation, 18, 42
Forward crosstalk, 132
Four-layer stackup, 27
Frequency, 4
Fringing effects, 214
Functional partitioning, 58
Functional subsystems, 152
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Table of Contents
Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
Index
O
P
Q
R
G
S Gauss's Law, 15
T
U Generic standards, 8, 274
V
W Ground
bounce, 75, 181, 196
choke, 171
impedance, 45, 181
loop control, 207
loops, 47
plane, 51
slots, 55, 207
stitch, 57, 202
trace, 130
via, 130
Grounded heatsinks, 227
common-mode decoupling capacitor, 231
dielectric insulator, 231
Grounding
I/O connectors, 163
methodologies, 43
multi-point for I/O interconnects, 163
multipoint, 45
single-point, 44
Guard bands, 188
Guard traces
application, 139
definition, 137
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Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
O
P Index
Q
R
S
T H
U
V Heatsinks
W grounded, 227
Hidden
characteristics, 14
schematic, 14
High-voltage capacitors, 185
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Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
Index
O
P
Q
R
I
S I/O and interconnects, 151
T
U IC. See Industry Canada, 5, 273
V
W IEC. See International Electrotechnical Commission
Image plane
definition, 51
slots within, 55
violation, 53
Immunity, 3
definition, 2
requirements, 10, 280
Impedance, 4
causes of discontinuities, 117
matching, 116
Impedance control
video layout, 168
Impedance controlled connectors, 194
Indirect dischargeESD, 179
Inductance
trace, 208
Inductive coupling, 132
Inductive filtering, 162
Industry Canada, 5, 273
Information technology equipment
definition, 9, 275
Input surge currents, 61
Insulation
basic, 236
double, 236
operational, 236
reinforced, 236
supplementary, 236
Interconnects, 200
board-to-board, 204
Internal radiated noise coupling, 153
International Electrotechnical Commission, 6
International Standards Organization, 6
ISO. See International Standards Organization
Isolation, 154
ITE. See information technology equipment, 9, 275
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Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
Index
O
P
Q
R
L
S LAN. See Localized area network
T
U Layer jumping, 129
V
W Layer stackup
assignment, 21
window, 241
LCI. See Line Conducted Interference
Line Conducted Interference, 2
Lithium battery circuits, 232
Loaded characteristic impedance, 113
Loaded propagation delay, 113
Local area network
layout recommendations, 164
Localized decoupling capacitor, 213
Localized planes, 211
Logic crossover currents, 61
Logic families
ECL, 99
selection criteria, 60
TTL, 99
Loop area, 47, 51, 55, 182
impedance, 82
Loop currents, 47
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Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
Index
O
P
Q
R
M
S Magnetic
T
U
fields, 18
V flux, 18
W
Manufacturing process, 243
Maxwell's equations, 15, 18
Microstrip
characteristic impedance, 101, 103
embedded microstrip, 102
intristic capacitance, 101, 103
propagation delay, 102, 104
surface microstrip, 101
Microvias, 88
Moats, 154
Mounting pads, 86
Multipoint grounding, 45, 47
gasketing technique, 50
resonance between ground points, 47
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Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
O
P
Q
R Index
S
T
U
V N
W
National Authority, 274
Noise coupling, 153
Notified Bodies, 274
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Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
O
Index
P
Q
R
S
T
U O
V
W Ohm's law, 16
Operational disruption, 176
Overshoot
definition, 116
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Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
Index
O
P
Q
R
P
S Parallel capacitors
T
U
effectiveness, 75
V
W
Parallel resonance, 67
Parallel termination
definition, 145
noise margin, 145
power dissipation, 145
Partitioning, 57, 152, 154
functional subsystems, 152
internal radiated noise coupling, 153
quiet areas, 152
quiet ground, 152
Passive component behavior, 14
Pigtails, 188, 232
Planes
chassis, 194
localized, 211
placement, 81
power and ground, 76
Polution degrees, 237
Power plane purity, 196
video, 168
Prepreg, 243
Product standards, 8, 275
Propagation delay, 111
Propagation path, 3
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Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
O
P
Q
R
S
T
Index
U
V
W
Q
Quiet areas, 152
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Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
O
Index
P
Q
R
S
R
T Radial migration, 39
U
V Radial routing, 23
W
power and ground traces, 206
Radiated emissions
definition, 1
Radiated immunity
definition, 2
Radio frequency
definition, 1
Receptor, 3
Reflection coefficient, 222
Reflections
definition, 116
electrically long trace, 117
Regulatory requirements
North America, 5
Worldwide, 6
Resonance
anti, 68, 75
parallel, 67
review of, 66
series, 67
Return current, 17, 42
RF current
density distribution, 42
return path, 42
RF return currents
alternate return path, 139
RF. See radio frequency
Ribbon cable assemblies, 193
Ribbon cables, 204
Right-angle corners, 220
Ringing
definition, 116
electrically long trace, 117
Routing
differential pair, 106
traces, 115, 122, 124, 203
Routing layers
differential signaling, 124
microstrip, 128
requirement for traces, 126
stripline, 128
Routing topologies, 19
eight-layer stackup, 33
four-layer assembly, 27
microstrip, 19
single-sided, 22
six-layer stackup, 30
stripline, 19
ten-layer stackup, 35
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Table of Contents
Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
Index
O
P
Q
R
S
S Series resonance, 67
T
U Series termination, 143
V
W Shield ground, 155
Shield partition, 115, 197, 204
Shunt traces
application, 139
definition, 137
Signal loops, 47
Signal return loop control, 47
Single-point grounding, 44
Single-sided assembly, 22
Six-layer stackup, 30
Skin
depth, 57
effect, 57
Sockets, 113, 115
Source impedance
components, 99
Source termination, 143
Spark gaps, 184
Stacking stripes, 241
Stackup assignments
double-sided, 24
eight-layer, 33
four-layer, 27
single-sided, 22
six-layer, 30
ten-layer, 35
Standards, 274
basic, 7, 274
generic, 8, 274
product family, 8, 275
Static fields, 16
Stripline, 19
characteristic impedance, 104, 105, 107
differential, 106
dual or asymmetric, 105
intrinsic capacitance, 104, 105
propagation delay, 105, 106
single, 104
Suppression
definition, 2
Surge currents, 61
Susceptibility, 3
definition, 2
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Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
O
Index
P
Q
R
S
T
T T-stubs, 122, 203
U
V
See also bifurcated lines
W
TDR. See Time Domain Reflectometer
Ten-layer stackup, 35
Termination
clock traces, 123
need to terminate, 141
Termination methodologies
AC network, 147
differential signaling, 149
diode network, 147
end termination, 144
parallel, 145
series termination, 143
source termination, 143
Thevenin, 145
Test coupons, 241
Test points, 241
Theory of electromagnetics
Faraday's Law, 15
Gauss's Law, 15
static fields, 16
time-varying currents, 16
Thevenin termination
definition, 145
equivalent resistance, 146
Through-hole discontinuities, 55
Time, 4
Time Domain Reflectometer, 112
Time-varying currents, 16
Toroids, 224
Trace
inductance, 208
separation, 136
Trace length routing, 115, 122, 124, 203
Trace routing
broadside-coupled stripline, 109
daisychaining, 122, 203
differential pair, 107, 137
edge-coupled stripline, 109
orthogonal, 106, 134, 204
single-ended, 106, 131, 203
T-stubs, 122, 203
Trace width etching
crest, 100
finished etch, 100
Traces
current carrying capacity, 238, 271
fusing, 241
guard, 137
shunt, 137
Transistor-transistor logic, 99
Transmission lines
differential-pair, 124, 149
need for, 91
single-ended, 122
Triboelectric scale, 176
TTL. See transistor-transistor logic
Twisting trace pair, 206
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Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
O
P
Index
Q
R
S
T
U
V U
W
Undershoot
defintion, 116
Unloaded propagation delay, 112
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Table of Contents
Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
O
P Index
Q
R
S
T
V
U
V
Velocity of propagation, 111
W Vias, 113, 119
affects on performance, 53
ground, 130
Video, 167
Voltage (IR) drop, 196
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Index
Index
Symbols & Numbers Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
A
by Mark I. Montrose
B
C IEEE Press 2000
D
E Recommend this title?
F
G
H
I
L
M
N
O
P
Q
Index
R
S
T
U
W
V Wave shaping capacitor
W
calculation of, 91
White noise, 171
Working voltage, 237
Wound beads, 224
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Table of Contents
List of Figures
List of Figures
List of Figures Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
Chapter 1: Introduction
by Mark I. Montrose
Chapter 2: Printed Circuit
Board Basics IEEE Press 2000
Chapter 3: Bypassing and
Decoupling
Chapter 4: Clock Circuits, Recommend this title?
Trace Routing, and
Terminations
Chapter 5: Interconnects
and I/O
Chapter 6: Electrostatic
Discharge Protection
Chapter 7: Backplanes,
Ribbon Cables, and
Daughter Cards
Chapter 8: Additional
Design Techniques
List of Figures
Chapter 1: Introduction
Figure 1.1: Items associated with the three elements of the EMI
environment.
Figure 2.7: Single-layer stackup with radial structure for power routing
and flow migration.
Figure 2.8: Two-layer PCB with power and ground grid structure.
Figure 2.10: Example why two-layer stackups are not efficient for
removing RF energy.
Figure 3.8: Resonant effect from two capacitors in parallel. (Source: Ref
[2]. Reprinted by permissionIEEE Press.)
Figure 4.9: Maximum unterminated line length vs. signal edge rate (FR-
4 material).
Figure 4.22: Parallel differential pair routing and the 3-W rule.
Figure 8.5: Application of the 20-H rule and power plane isolation.
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Table of Contents
List of Tables
List of Tables
List of Tables Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
Chapter 1: Introduction
by Mark I. Montrose
Chapter 2: Printed Circuit
Board Basics IEEE Press 2000
Chapter 3: Bypassing and
Decoupling
Chapter 4: Clock Circuits, Recommend this title?
Trace Routing, and
Terminations
Chapter 6: Electrostatic
Discharge Protection
Chapter 8: Additional
Design Techniques
Appendix B: International
EMC Requirements
List of Tables
Appendix D: Conversion
Tables
Chapter 1: Introduction
Table 1.1: Additional North American Standards
Table 8.4: Additional Clearance Distances for Use with High- Voltage
Applications
Table 8.7: Conversion Chart for PCB Finished Trace Widths Related to
Standard Wire Gauges
2
Conversion of Volt/m to mW/cm for Linear and dB Scales
FrequencyWavelengthSkin Depth
FrequencyWavelength Conversion
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Books24x7 and Referenceware are registered trademarks of Books24x7, Inc.
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Personal account | University of Southern Queensland
Table of Contents
List of Examples
List of Examples
List of Examples Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition
Chapter 3: Bypassing and
by Mark I. Montrose
Decoupling
Chapter 4: Clock Circuits, IEEE Press 2000
Trace Routing, and
Terminations
Recommend this title?
List of Examples
Chapter 3: Bypassing and Decoupling
Example 1
Example 2
Stripline Example
Use of content on this site is expressly subject to the restrictions set forth in the Membership Agreement.
Books24x7 and Referenceware are registered trademarks of Books24x7, Inc.
Copyright 1999-2008 Books24x7, Inc. - Feedback | Privacy Policy (updated 03/2005)